JPS61169029A - Two-way time-division multiplex dpcm coding and decoding device - Google Patents

Abstract

PURPOSE:To obtain a two-way time-division multiplex DPCM coding and decoding device miniaturized and simplified by combining a forecast device having n stages of digital delay circuits operated by a clock frequency times the sampling frequency, a subtractor, an adder and a gate circuit. CONSTITUTION:An output data t an output terminal 62 of the forecast device 6 is delayed from data at an input terminal 61 by one sampling period at all times, and then the forecast device 6 having the n stages of digital delay circuits operated by the clock frequency n times the sampling frequency acts like a pre-forecast value device. Further, an input data is fed to the subtractor 1 as forecast data and outputted from an input/output terminal 102 via the gate circuit 8 as an output data of a local differentiation pulse code modulation DPCM decoder 7 during the decoding period. Thus, data flows from a terminal 102 to a terminal 101 at the coding period and from the terminal 101 to the terminal 102 at the decoding period and the circuit acts like a DPCM coding and decoding device with two-way time-division multiplex as a whole.

Description

[Detailed description of the invention] Industrial application field The present invention relates to high-precision transmission band compression of audio signals, etc.
P G M (Differential Pulse
CodeModulation) encoding and DPC
This invention relates to a DPCM code decoder that performs M decoding simultaneously in both directions.

Conventional technology In the past, in order to perform DPCM encoding and DPCM decoding simultaneously in both directions, the DPCM encoder and DPCM decoder were installed independently or combined with an appropriate time division multiplexing circuit. . The conventional techniques to be combined are basic ones, and are shown, for example, in (Electronic Communication Institute, Electronic Communication Handbook, Vol. 16, Section 3, 4.3).

Problems to be Solved by the Invention However, providing a DPCM encoder and a DPCM decoder independently leads to an increase in circuit scale and an increase in chip area when integrated circuits, and requires a large number of input/output terminals. Therefore, it has the drawback that it is not only inconvenient in terms of implementation, but also uneconomical.

Means for Solving the Problems The present invention solves the above problems.In a DPCM encoder consisting of a predictor, a subtracter, and an adder, at least the predictor is n times the sampling frequency (n is 2 or more). positive integer)
This circuit has an n-stage digital delay circuit operating at a clock frequency of 1, and is provided with a gate circuit to bidirectionally time-division multiplex the input/output signals of the DPCM encoder and its local DPCM decoder.

In order to reduce the number of input/output terminals, the gate circuit described above includes a first gate circuit and a second gate circuit, and a first input/output terminal which time-division multiplexes the encoder output and the decoder input, and the encoder input. and a second input/output terminal for time-division multiplexing the decoder output.

According to the present invention, with the above-described configuration, bidirectional time division multiplexed DPCM code decoding can be performed with a small number of parts, and the number of input/output terminals can be reduced.

Embodiment FIG. 1 is a block diagram showing the basic configuration of the present invention. In Fig. 1, 1 is a subtracter for obtaining the difference between the predicted value and input data, that is, a prediction residual, and 2 is a quantizer for performing non-linear quantization to reduce bits in order to compress the transmission band. , 3 is a gate circuit, 4 is an inverse quantizer, 6 is an adder, and 6 is a prediction having an n-stage digital delay circuit that operates at a clock frequency n times the sampling frequency (n is a positive integer of 2 or more). It is a vessel. 7 is a local DPCM decoder consisting of an inverse quantizer 4, an adder 5 and a predictor 6.

First, the operation of the DPCM encoder will be explained.

The analog input signal is pre-encoded into linearly quantized digital data by a MU/D converter (not shown) and then sent to the encoder input terminal 1.
Applied to 021L. The subtracter 1 obtains the difference between the predicted value and the input data, that is, the prediction residual, and the quantizer 2 performs nonlinear quantization to reduce bits in order to compress the transmission band, and then encodes the predicted residual data. device output terminal 1011
! Output to L.

At this time, the code/decoding control input terminal 20o is controlled to be in the encoding operation state, and a part of the output is applied to the inverse quantizer 4 through the gate circuit 3. The inverse quantizer 4 is for returning the non-linear quantized data to the original linear quantization.

This data is added to a prediction loop comprising an adder 5 and a predictor 6 to obtain a predicted value.

Next, the operation of the DPCM decoder will be explained.

The transmission band compressed digital data inputted from the decoder input terminal 101b is applied to the inverse quantizer 4 through the gate circuit 3. The data non-linearly quantized by the inverse quantizer 4 is returned to the original linearly quantized data, and in addition to the prediction loop consisting of the adder 5 and the predictor 6, the predicted value ie D
A PCM decoder output is obtained and output to the decoder output terminal 102b. At this time, the code/decoding control input terminal 200 is controlled to be in the decoding operation state. In this way, the DPCM decoder commonly uses the local DPOM decoder of the DPOM encoder.

The above describes the encoding and decoding operations, but the predictor 6 is a predictor that has an n-stage digital delay circuit that operates at a clock frequency that is n times the sampling frequency (n is a positive integer of 2 or more). When n=2, double time division multiplexing is possible. That is, by inverting and controlling the control signal applied to the code decoding control input terminal 200 of the gate circuit 3 every clock of the predictor 6, code decoding can be operated alternately. By doing so, both encoding and decoding operations can be performed within one sample period, and output data corresponding to each operation can be extracted.

That is, it can be a bidirectional time division multiplexed DPCM code decoder.

Next, another basic circuit of the present invention will be explained. FIG. 2 is a block diagram showing another basic configuration of the present invention. In FIG. 2, 3 is a first gate circuit, 8 is a second gate circuit, 101 is a first input/output terminal that time-division multiplexes the encoder output and decoder input, and 102 is the encoder input and decoder input. The basic operation of the output is the same. Second
The difference in the configuration shown in the figure is that a second gate circuit 8 is provided, and a control signal inverted for each clock of the predictor 6 described above is applied to a second control terminal 202 of the second gate circuit 8, which is the control terminal Lc of the second gate circuit 8. The device outputs are time-division multiplexed so that they can be input and output from the second input/output terminal 102.

Next, FIG. 3 shows a block diagram of a specific embodiment of the bidirectional time division multiplexing DPCM code decoder of the present invention, and FIG. 4 shows a timing diagram showing the operation of FIG. 3. This will be explained in more detail based on FIGS. 3 and 4.

In FIG. 3, the predictor 6 is a previous value predictor and is composed of a two-stage digital delay device. The first gate circuit 3 and the second gate circuit 8 use three-state gates, and when the respective control terminals 33 and 83 are set to H, the gate circuits are activated (on), and when set to L, the gate circuits are turned off and high. This causes the impedance to be in a floating state. 'Also, the control signal at the control terminal 200 is
The voltage is applied directly to the control terminal 83 of the gate circuit 8 and inverted by the inverter 9 to the control terminal 33 of the first gate circuit 3 .

In FIG. 4, (a) is the sampling clock of the M71 converter for preliminary encoding, and TI, T2 and T3 are sampling times, respectively. (b) is a control signal of the control terminal 200, which corresponds to the operating state of (C). During the encoding period, the second gate circuit 8 is turned off (high impedance) so that the output of the local DPCM decoder and the encoder input do not collide, and the 16-binot encoder inputs (iKl, iE, ...) is applied to the subtracter 1, and the first gate circuit 3 is activated (turned on). In the next decoding period, the first gate circuit 3 is similarly turned off (high impedance) (el).
An 8-bit decoder input (iDl) from the first input/output terminal 101 shown in FIG.

lD2. ...) is input to the local DPOM decoder 7, and the second gate circuit 8 is activated (turned on). (0 is the delay clock of the digital delay device of the predictor 6, which is twice the sampling frequency.

Other blocks except predictor 6 (subtracter 1, quantizer 2, etc.)
The operation time of the first gate circuit 32, etc.) is sufficiently short compared to the sampling period and the delay clock period and can be ignored.

For this reason, the encoder input (iKl, iK2+...
) is the subtractor 1. Quantizer 2. First gate circuit 3. After passing through the inverse quantizer 4 and the adder 5, (iK'1, iK'2
,...) and also the decoder input (iDl,
iD2. ...) becomes (iD'1, iD'2...) through the inverse quantizer 4 and adder 5,
The data at the input terminal 61 of the predictor 6 is time-division multiplexed data as shown in (g).

This input data is sequentially delayed by a two-stage digital delay device to obtain output data (0) that is shifted by two clocks. As is clear from the figure, the output data (0 is always the data (g ), so the predictor 6 operates as a previous value predictor. During the encoding period, the prediction data is applied to the subtractor 1, and during the decoding period, the prediction data is applied to the subtractor 1 as the output data of the local DPCM decoder 7. It is output from the second input/output terminal 102 via the 2-gate circuit 8.The decoder output (ODl, OD2...) is shown in (h).The encoder output is output from the subtracter 1 as described above. .The first input/output terminal 101 via the quantizer and the first gate circuit 3
Output from. This encoder output (oEl, oE2.
...) is shown in (1).

From the above, the data at the first input/output terminal 1o1 and the second input/output terminal 102 are (k) and Ci), respectively, and during the encoding period, the data is transferred from the second input/output terminal 102 to the first input/output terminal 101 for decoding. On the contrary, the first input/output terminal 1
Data flows from 01 to the second input/output terminal 102, and the entire device operates as a bidirectional time division multiplexed DPCM code decoder.

Compared to the conventional configuration that would require two local DPCM decoders, in this example, by sharing, only one local DPCM decoder is required, significantly reducing the number of parts. It can be reduced to

In addition, if the configuration is based on the conventional technology, the encoder input terminal (16
In this example, the first input/output terminal is Terminal (16
Since only 24 pins (8 pins) and 2nd input/output terminals (24 pins in total) are required, the number of pin terminals of the mounted pano cane can be reduced when fabricating a semiconductor integrated circuit, resulting in cost reduction.

In this embodiment, the predictor is Maesu prediction, but it may be a first-order linear predictor or a higher-order linear predictor using digital fill.

FIG. 5 is a block diagram showing a first-order linear predictor that can be used in the bidirectional time division multiplexing DPCM code decoder of the present invention. It can be multiplexed.

Further, in this embodiment, the digital delay device of the predictor is set to two stages, but the number of multiplexing may be two or more, and in this case, it is possible to further provide multiple channels.

Effects of the Invention As explained in detail above, according to the bidirectional time division multiplexed DPCM code decoder of the present invention, bidirectional time division multiplexed DPCM code decoding can be performed with a small number of parts. Simplification of equipment.

It is possible to achieve miniaturization, reduce the number of input/output terminals, and has a remarkable economical effect especially when integrated circuits are implemented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the first basic configuration of the present invention, FIG. 2 is a block diagram showing the second basic configuration of the present invention, and FIG. 3 is a specific implementation of the present invention. 4 is a timing diagram of main data in the embodiment of FIG. 3, and FIG. 5 is a linear linear diagram that can be used in the bidirectional time division multiplexing DPCM code decoder of the present invention FIG. 2 is a block diagram showing a predictor. 1...Subtractor, 2...Quantizer, 3...
...First gate circuit, 4...Inverse quantizer, 5.
...Adder, 6...Predictor, 7...
...Local DPCM decoder, 8...Second gate circuit, 9...Inverter, 101...First input/output terminal, 102...Second input/output terminal, 200...・・−
Code/decoding control input terminal, 300... Delay clock input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Diagram ← Shōshō shā shān yān mi t+-be blinded Ka

Claims (2)

[Claims] (1) It is characterized by comprising a subtracter, an adder, a predictor having an n-stage digital delay circuit that operates at a clock frequency n times the sampling frequency (n is a positive integer of 2 or more), and a gate circuit. A bidirectional time division multiplexed DPCM code decoder. (2) The gate circuit includes a first gate circuit and a second gate circuit, and has a first input/output terminal that time-division multiplexes the encoder output and decoder input, and a first input/output terminal that time-division multiplexes the encoder input and decoder output. A bidirectional time division multiplexed DPCM according to claim 1, characterized in that the second input/output terminal is provided with a second input/output terminal.
code decoder.