JPS61169028A - Time division multiplexed dpcm coder - Google Patents

Abstract

PURPOSE:To apply multi-channel DPCM coding with the less number of components by providing an A/D converter group, a digital multiplier, a quantizer and a forecast device or the like, allowing the forecast device to form a pre-forecast value and feeding back its output to a substractor as a forecast data. CONSTITUTION:The substractor 3 obtains a difference between an input data from the digital multiplier 2 and a forecast data, that is, a forecast residual value, the quantizer 4 applies nonlinear quantization for the purpose of bit reduction and gives an output 8. Then an output data of the quantizer 4 is inverted from the nonlinear into the linear data by an inverse quantizer 5, the bit is expanded and the result is fed to one input terminal of an adder 6. The output of the adder 6 is fed to the forecast device 7, delayed by a delay circuit and a part of the result is fed to the other input terminal of the adder 6. In this case, the forecast device 7 forms a pre-forecast value and its output is fed back to the subtractor 3 as a forecast data to constitute a differential pulse mode modulation DPCM coder.

Description

[Detailed description of the invention] Industrial application field The present invention relates to high-precision transmission band compression of audio signals, etc.
P G M (Differential Pulse
CodeModulation) This relates to the configuration of the time division multiplexing circuit of the encoder.

Conventional technology DP time division multiplexed from multi-channel analog signals
In order to obtain a CM code, the following two methods can be considered by combining conventional techniques. The first method is to multiplex analog signals as they are using an analog multiplexer and obtain the desired signal using a high-speed A/D converter and a DPCM encoder.The second method uses an A/D converter and a DPCM encoder. A digital signal output from each functional block is multiplexed to obtain a desired signal. The branches of conventional techniques that can be combined are basic ones, and are shown, for example, in (edited by the Society of Communication Studies, Electronic Communication), Ndo Book, Vol. 15, Section 3, 4.3).

Problems to be Solved by the Invention Generally, high-precision A/D conversion requires a longer conversion time. Therefore, it is difficult to realize a high-speed and high-precision A/D converter, and the first method that requires this has the problem of being expensive. Furthermore, since the first method multiplexes analog signals as they are, there is a problem in that it is difficult to set the sampling times of each channel at the same time.

In the second method, an A/D converter is provided for each channel, which allows sufficient conversion time and is easy to achieve high precision.However, as shown in Figure 4, a DPCM encoder is also provided for each channel, which increases the number of components and makes implementation difficult. There were also problems that were economically disadvantageous.

Means for Solving the Problems In order to solve the above problems, the present invention uses a DPCM encoder consisting of a group of A/D converters provided for each channel, a digital multiplexer, a predictor, a subtracter, and an adder. Therefore, at least the predictor is n times the sampling frequency (n is 2
The DPCM encoder is time-division multiplexed by having an n-stage digital delay circuit that operates at a clock frequency of a positive integer equal to or higher than the above.

Effect of the Invention With the above-described configuration, the present invention can perform multi-channel high-precision preliminary encoding using a relatively low-cost A/D converter group, and can perform multi-channel DP with a small number of parts.
It is capable of performing CM encoding.

Embodiment FIG. 1 shows the present invention in a four-channel time division multiplexed DPCM.
FIG. 2 is a block diagram illustrating an example implementation of an encoder. In FIG. 1, reference numeral 1 denotes an A/D converter group which converts four channels of analog signals into digital data. 2
is a digital multiplexer that time-division multiplexes digital data of four channels. 3 is a subtractor. 4
is a quantizer, and 6 is an inverse quantizer, which performs non-linear quantization to reduce pits in order to compress the transmission band. 6 is an adder, and 7 is a predictor consisting of a four-stage digital delay circuit. 8 is an output terminal.

First, the basic operation will be explained. A subtracter 3 calculates the difference between the input data from the digital multiplexer and predicted data, that is, a predicted residual, and a quantizer 4 non-linearly quantizes the data for the purpose of reducing pits, and outputs it to an output terminal 8. The output data of the quantizer 4 is converted from a non-linear state into a straight line by an inverse quantizer 5, subjected to pit expansion, and then applied to one input terminal of an adder 6. The output data of the adder 6 is input to the predictor 7, delayed by a digital delay circuit included therein, and a part of the data is applied to the other input terminal of the adder 6. That is, a previous value predictor is formed and its output is fed back to the subtracter 2 as prediction data, and this previous value prediction loop constitutes a DPCM encoding section.

The digital delay circuit in the predictor 7 of the DPGM encoder configured as described above has a four-stage configuration and is operated at a clock frequency four times the sampling frequency. FIG. 2 is a timing diagram of these signal data.

The following description will be given based on FIGS. 1 and 2.

In FIG. 2, the common sampling clock of A/D converter group 1 is S, and the sampling time is TI.

T2, T3... The A/D converter group output data are as shown in 12a, 12b, 12c, and 12d, and the respective data are divided into Mn, Bn, On, and Dn.
shall be. The data obtained by time-division multiplexing these by the digital multiplexer 2 is as shown in 22. This time division multiplexed data is applied to the DPCM encoder. The operation time of each of the subtracter 3, quantizer 4, inverse quantizer 5, and adder 6 of the DPCM encoder is sufficiently short compared to the delay operation time of the digital delay circuit of the predictor 7 and can be ignored. Therefore, the data input to the input terminal 71 of the predictor 7 is 71
and these iA'n, B'n, C'
Let n and D'n.

The delay clock of the digital delay circuit of the predictor 7 is shown in D. Input data 71 is sequentially delayed by four stages of digital delay circuits, and is shifted by four clocks, resulting in output data 72. It can be seen from the figure that the output data of the predictor 7 is always delayed from the input data by one sampling period. As mentioned above, the predictor 7 is removed (other blocks of the DPCM encoder operate in real time, so the output data output from the output terminal 8 is the data An, Bn, On and DniDPc
M encoded A"n, B'n, C"n and D
n is obtained.

As explained above, according to this embodiment, the time division multiplexing DPCM encoding section is configured by connecting only the digital delay circuits of the previous value predictor in multiple stages for each channel and setting the delay clock frequency according to the number of multiplexing. You can.

In this embodiment, the predictor is a previous value predictor, but it may be a first-order linear predictor or a higher-order linear predictor using a digital filter.

FIG. 3 is a block diagram showing a first-order linear predictor that can be used in the time-division multiplexed DPCM encoder of the present invention, and the DPCM encoder can be time-division multiplexed in exactly the same way as the previous value predictor. be.

Effects of the Invention As explained in detail above, the time division multiplexed DP of the present invention
According to the CM encoder, it is possible to perform multi-channel high-precision preliminary encoding using a relatively low-cost MU/D converter group, and it is also possible to perform multi-channel DPCM encoding with a small number of parts. It is something that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the time division multiplexing DPCM encoder of the present invention, and FIG. 2 is a block diagram showing an embodiment of the time division multiplexing DPCM encoder of the present invention.
FIG. 3 is a block diagram showing a first-order linear predictor that can be used in the time division multiplexed DPCM encoder of the present invention. FIG. 4 is a time division diagram constructed by a simple combination of conventional techniques. FIG. 2 is a block diagram of a multiplexed DPCM encoder. 1...M/D converter group, 2...Digital multiplexer, 3...Subtractor, 4...
...Quantizer, 5...Inverse quantizer, 6...
...Adder, 7...Predictor, 8...Output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
I+N1 Kyou WΦ Mi+N<R serious evil

Claims (1)

[Claims] It is characterized by comprising a group of A/D converters, a digital multiplexer, and a predictor having an n-stage digital delay circuit that operates at a clock frequency that is n times the sampling frequency (n is a positive integer of 2 or more). Time division multiplexed DPCM encoder.