JPH02501180A - Audio broadcasting signal encoding and decoding system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Audio broadcasting signal encoding and decoding system field of invention TECHNICAL FIELD The present invention relates to information transmission technology, and in particular to an audio broadcast signal encoding and decoding system.

Conventional technology The most widely known audio broadcast encoders and decoders use pulse code modulation with simultaneous companding. (G, Bellamy"Digital telep hony”, Moscow, Radio i 5vyaz, 1986. p. 116 (Russian)). Such equipment broadcasts via satellite communication channels. It is part of the equipment for transmission and is also a ground-referenced digital channel for audio broadcast transmission. is part of the equipment for establishing the This system has an encoder and a decoder. do. The encoder consists of a low-pass channel filter, a compressor, and an analog The output of this converter constitutes the output of the encoder. do. The decoder consists of a digital-to-analog converter, an expander, and a low The input to this digital-to-analog converter is the decoder. Configure input. The use of compressors and decompressors can reduce quantization at high input signal levels. steps and thus the signal/noise ratio during quantization is lower than the listener's actual noise. It can keep the sound at an undetectable level.

The system described above uses 10-bit analog-digital to establish a high-quality channel. A digital converter is used, which allows signal companding and 32 Signal digitization is carried out at kHz. Therefore, the encoder The digital flow velocity V at the output is V = 10 x 32 = 32 bits/s .

Conventional audio broadcasting signal encoding/decoding device (A, N, Golubevet a l,,”Equipment for digital transmission ion of 5ound broadcast signals"Elektr Osvyaz, 1980. No, 7. p, 6 (Russian)) is the pressure mentioned above. Unlike the digital decompressor, it uses pulse code modulation with simultaneous companding. ing. The compressed signal in these systems is sampled and converted into a 12-bit linear code, whose sampling frequency was also 32kHz, but Therefore, the bit rate V at the encoder output is V=12X32=384 bits/ S, which is 20% larger than the system described above. According to expert tests, this is the acoustic Increase playback fidelity. These conventional systems provide near-natural acoustic reproduction Therefore, the signal code by pulse code modulation by simultaneous companding has a length of 12 bits. sample code words are used.

This capacity is typical of conventional systems.

Improved pulse code modulation increases the bit rate of individual audio broadcast channels using simultaneous companding. lower than the bit rate of pulse code modulation.

Conventional audio signal broadcasting encoding/decoding system (M, V, Gitlits.

S, V, Chetkin” The use of adaptive d ifer’nential pulse-code modulation f or analogue-to-digital conversion of sound broadcast signals” Elektrosvya z, 1982. No, 1. p, 58 (Russian)), the encoder is The signal is digitized and the decoder performs the inverse transformation. The encoding unit is a channel The output of this low-pass filter is connected to the signal level control unit. The signal of this control unit is fed to the non-inverting input of the operational amplifier. . This op amp works in different modes and also drives a pulse amplitude modulator .

The output of the pulse amplitude modulator is connected to the input of an analog-to-digital converter, which The output of the converter constitutes the encoder output.

Additionally, the system consists of signal prediction and control circuitry.

The digital output of the encoder output is fed to a signal prediction unit, which is converted into an analog signal by a digital-to-analog converter, and then smoothed by an interpolator. Equalized.

The predicted signal thus generated is applied to the inverting input of the differential amplifier, and The amplifier generates a signal proportional to the difference between this input signal and the predicted signal. This difference signal is Analog-to-digital conversion for level quantization and double code conversion by pulse amplitude modulator Supplied to a digital converter. The control circuit also includes a digital-to-analog converter. This output signal is rectified and integrated, and the signal level expert of the encoder According to acoustic quality testing by The rate does not exceed 10% to 15% for analancer voices, various music, and reading signals. , also for piano, violin, symphonic orchestra and chamber orchestra. is slightly high <25% to 30%. Thus, bit rate 256kL:-t The sound provided by an encoder using improved differential pulse code modulation operating at /S Voice quality is determined using pulse code modulation with simultaneous companding, which produces no distortion that is perceivable to the listener. The audio quality is inferior to that of the encoder. The encoder using improved differential pulse code modulation is applied to the input of the input to control the encoder's transfer factors. In the decoder, the binary The code is subjected to logic conversion in a logic unit. The logical unit is a digital - in series with analog converter, integrator, low-pass filter and signal level control unit It is connected. The control circuit for the signal level control unit consists of series connected devices. Connected to the digital-to-analog converter, rectifier, and integrator. Output of integrator The power is connected to the input of the control unit. If the difference signal level is low, the decoder The gain of the signal level control unit at quantization accuracy can be increased. When the difference signal level is at the maximum level, the decoder The gain of the signal control unit is minimized, while the signal level control in the encoder The unit's gain is maximum.

The system described above has a bit rate of 256 bits/s in the 15 kHz frequency band. Acoustic broadcast transmission can be achieved using pulse code modulation with instantaneous companding. considerably lower than the equipment.

It is only used for audio signal compression when the requirements for audio playback quality are less stringent than those for audio broadcasting. It will be done.

Audio broadcasting signal encoding/decoding system using floating point per block (simultaneous companding) is known. (C0R0Caine, A.

K, English, J, M, 0°C1earey,’NICA! , 1=III: near-instan-teously compounded Digital transmission system for high h-quality 5ound programs", -Radio and Electronic Engineering, 1980. v ol, 50. No, 10. PP, 520-529). This system smell In this case, the encoder consists of a low-pass filter, an analog It is equipped with a log-to-digital converter and a code converter that outputs the encoder output. , also connected to the synchronization input of this analog-to-digital converter and code converter. It is equipped with a synchronous pulse generator with a synchronous output. analog to digital converter Digitalization of analog signals by pulse code modulation, which has recently been adopted. (actual 32k) (twice the low-pass filter cutoff frequency of z) done in frequency.

The sample coding capacity in different system variants depends on the dynamic level of signal reproduction. It varies from 14 to 16 according to the number. The code converter blocks the 16-bit code. Convert each block to floating point code. Here, the mantissa is 10 bits including the sign bit. The exponent is coded into a 3-bit word. per block The code block length with floating points is 32 samples, and the exponent is the highest in the block. Recode the samples of this block, defined by the magnitude sample (absolute value) used for.

The multiplexer in the conventional system consists of a series-connected code converter whose input is the decoder input; Equipped with a digital-to-analog converter and a low-pass filter whose output is the decoder output. ing. The decoder also has a synchronous pulse generator whose input is connected to the code converter The output of the code converter is connected to the output of the digital-to-analog converter and the code converter. connected to the sync input of the converter.

The code converter converts the block floating point code into 16-bit sample codewords. , this word is fed to the digital-to-analog converter in parallel code.

The recovered acoustic broadcast signal samples are fed to a low-pass filter for temporal smoothing. It will be done.

Bits at encoder output with block floating points for individual audio broadcast channels The speed is 323 bits/s, which is faster than for pulse code modulation with simultaneous companding. 20% lower and 12 bits in pulse code modulation with simultaneous companding transmission system. The quality of the reproduced signal is not worse than the output of the decoder. This is a block floating point technique While coding a block for a fixed value of exponent, quantization noise This is achieved by considering the effect of masking.

At the same time, the bit rate at the code output is High from the point. In other words, the transmission of such digital signals requires a large-capacity transmission channel. Requires the use of a file.

Disclosure of invention The objective of the present invention is that the design of the encoder and decoder is While lowering the bit rate, music signal band coding can be introduced into the spectral domain to improve reliability. This encoding critically masks the human auditory range, keeping signal reproduction high. An object of the present invention is to provide an audio broadcasting encoding/decoding system that takes into account effects.

The above purpose is connected directly to the low-pass filter and inputs the input of said low-pass filter. an encoder having an analog-to-digital converter; The code converter electrically connected to the converter and the clock of the analog-to-digital converter. a synchronous pulse generator connected to the clock input and the clock input of the code converter; converter, an analog-to-digital converter electrically connected to the code converter, a decoder; a low-pass filter having an output constituting a data output, and the analog-to-digital conversion decoder with a synchronous pulse generator whose output is connected to the clock input of the device In an audio broadcasting signal encoding/decoding system comprising: During signal encoding and decoding, the encoder an input connected bit by bit to the output of the pulse converter and each output of the synchronous pulse generator. a buffer memory having a clock input and a timing input connected to the Data input connected to the output of the buffer memory, each output of said synchronous pulse generator a cycle input and a clock input connected to and a data input of said code converter. an acoustic broadcast signal spectrum conversion unit having an output connected bit by bit to; a clock input connected to the output of the synchronous pulse generator and a control of the code converter; a control pulse generator having an output connected to a control input; a control input connected to the output, an output connected to the data input of said control pulse generator; power, and a number note with a clock input connected to the output of the synchronous pulse generator a data input connected to the output of the transcoder, a data input of the control pulse generator; a control input connected to the output, a clock connected to the output of the synchronized pulse generator; a multiplexer having an input and an output comprising a sign output; , the decoder has an input connected to the output of the multiplexer and forming a decoding input. , a data output connected to the input of the transcoder, and a data output of the synchronization pulse generator. a demultiplexer having an input and a clock input connected to the input of the transcoder; a data input connected bit by bit to the output of said transcoder; A clock input connected to the output of the pulse generator and the output of the demultiplexer. a buffer memory having a power and a bit-by-bit connection to the output of the buffer memory; a data input, connected to the output of the synchronization pulse generator and the output of the demultiplexer; connected clock input, and bit-by-bit input to the input of the analog-to-digital converter. an acoustic broadcast signal inverse spectral conversion unit having an output connected to the a clock input connected to the output of the multiplexer and a clock input of the code converter; a control pulse generator having an output connected to the control pulse generator; The output of the converter is connected to the control input of the code converter, the control input of the buffer memory, and the control input of the code converter. Connected to the control input of the demultiplexer and records the number of spectral components in the critical acoustic band. The number memory for storing a clock input connected to the output of the demultiplexer, and a clock input connected to the output of the demultiplexer; an acoustic broadcast signal characterized in that it has an output connected to a data input of a sound generator; is achieved by an encoding/decoding system.

The above object also includes an encoder and a decoder, the encoder receiving a code input. Main low-pass filter and main analog-to-digital filter connected in series with inputs configuring a converter and a main code converter electrically connected to the main analog-to-digital converter. and the clock input of the main analog-to-digital converter and the clock input of the nuclear code converter. a synchronous pulse generator connected to the main decoder input; a code converter and a main digital-to-analog converter electrically connected to the nuclear code converter; a converter and a main low-pass filter connected in series thereto and having an output constituting a decoded output; , having an output connected to the clock input of the main digital-to-analog converter. An audio broadcasting signal encoding/decoding system comprising: a synchronous pulse generator; During encoding and decoding of stereo audio broadcast signals, the encoder A sub-low-pass filter having an input constituting a sub-input and a sub-low-pass filter connected in series thereto and said synchronizing Secondary analog-to-digital with clock input connected to the output of the pulse generator The converter is connected bit by bit to the output of the main and sub analog-to-digital converters. a clock input connected to the output of the synchronized pulse generator; an arithmetic unit, and a data input and a data input connected bit by bit to the output of the arithmetic unit. and a clock input connected to the output of the synchronous pulse generator. connected to the filter unit and the output of the digital filter unit for each bit. 2m groups of data inputs connected to the output of the arithmetic unit, one group connected bit by bit to the output of the arithmetic unit. and a clock input connected to the output of the synchronized pulse generator. a signal converter for a signal having information about a stereo audio broadcast signal; output of the signal converter for a signal having information about the stereo audio broadcast signal; a data input connected bit by bit to the output of the synchronizing pulse generator; a sub-coder converter having a clock input, and a bit-by-bit input signal to the output of said main code converter. Data input connected, clock input connected to the output of the synchronized pulse generator , and a multiplexer having an output constituting a code output, Each of the sub-transcoders has two groups of outputs connected to the data inputs of the multiplexer. further, the encoder is connected bit by bit to the output of the arithmetic unit. a third group of data inputs having information about the stereo audio broadcast signal; a second group of data inputs connected bit by bit to the output of the signal converter for the signals; and a buffer memory having a clock input connected to the output of the synchronized pulse generator. a data input connected bit by bit to the output of the buffer memory; a cycle input and a clock input connected to each output of the pulse generator, and the main signal an audio broadcast signal spectrum with output connected bit by bit to the data input of the signal converter; a torque conversion unit and a clock input connected to the output of the synchronous pulse generator; an output connected to a control input of the main transcoder and an output of the multiplexer a control pulse generator having an output connected to the output of the control pulse generator; a connected control input; an output connected to the data input of said control pulse generator; and a number memory having a clock input connected to the output of the synchronized pulse generator; and the decoder is connected to the output of the multiplexer of the encoder. an input which constitutes the decoding input, an output connected to the input of the main transcoder of said decoder; and connected to the input of the synchronization pulse generator and the input of the main code converter of the decoder. a demultiplexer having a connected clock input; and a main code converter of the decoder. a data input connected to the output of the synchronous pulse generator, and a data input connected to the output of the synchronous pulse generator. A buffer memory with a clock input and an output of the buffer memory 'J (132) a data input connected bit by bit to a power output and a data input connected bit by bit to an output of the synchronizing pulse generator; an audio broadcasting transmission inverse spectral conversion unit having a clock input; a clock input connected to the output of a multiplexer and a main code converter of the decoder; a control pulse generator having an output connected to a clock input of the control pulse generator; The output of the control pulse generator is the control input of the main code converter of the decoder and the buffer. connected to a control input of the memory and a control input of the demultiplexer; The decoder includes a control input connected to the output of the control pulse generator, a control input connected to the output of the control pulse generator, and a control input connected to the output of the control pulse generator; a clock input connected to the output of the pulse generator, and a data input of the control pulse generator. to store the number of spectral components in the critical acoustic band with the output connected to the data input. a number memory and two data inputs connected to the output of said demultiplexer; and a clock connected to the output of the synchronous pulse generator and the output of the demultiplexer. m sub-code converters each having a clock input and connected to the output of the synchronizing pulse generator; a stereo signal restorer having a clock input and an output of the synchronous pulse generator; Clock input connected to the output, connected bit by bit to the input of the stereo signal restorer (m+1) outputs, and bits at the outputs of each of the m sub-code converters. a digital filter unit with inputs connected to each other and said inverse spectrum Data input connected bit by bit to the output of the conversion unit, and a synchronous pulse generator and a buffer memory having a clock input connected to the output of the demultiplexer. and a first output group of the buffer memory is connected to the digital filter. The second output group of the buffer memory is connected to the input of the unit, and the second output group of the buffer memory is connected to the input of the stereo signal Sub-digital analogue connected bit by bit to the input of the signal restorer and further connected in series is connected to a log converter and a sub-low-pass filter, and the output of the sub-low-pass filter is connected to the decoding The first group output of the stereo signal restorer constitutes the sub output of the main digital - connected bit by bit to the data input of the analog converter and of the stereo signal restorer; The other output group is connected to the data input of said secondary digital-to-analog converter; The clock input of the digital-to-analog converter is connected to the output of the synchronous pulse generator. achieved by an audio broadcasting signal encoding/decoding system characterized by Ru.

According to the present invention, compared to the recently used pulse code modulation by simultaneous companding, can reduce the bit rate of high-quality mono audio broadcast signals by as much as 2 times, and also Compared to transmission technology that encodes and transmits the left stereo channel independently, The bit rate of digital transmission can be reduced by about 1.4 times.

According to implementation of the present invention, instead of the 6 mono broadcasts currently being transmitted, 20 12 digital channels via a main standard digital channel capacity of 48 P/S Enables monaural high-quality broadcasting or 8 digital stereo high-quality broadcasts . This has important implications for satellite broadcasting systems where the cost of transmission channels is very high. do. Furthermore, the application of the invention in audio broadcast transmission via radio channels is There are significant benefits in the required transmission bandwidth.

Brief description of the drawing Hereinafter, the present invention will be explained in more detail with reference to examples and the accompanying drawings. here, FIG. 1 shows a block diagram of an encoder and decoder for monaural audio broadcasting signals according to the present invention. FIG. 2 is a block diagram of an encoder for a monaural audio broadcast signal according to the present invention; FIG. 3 is a block diagram of a code converter according to the present invention; FIG. FIG. 4 is a block diagram of a control pulse generator in an encoder for a transmitted signal; is the critical audio in the encoder for monaural audio broadcasting signals according to the present invention. is a block diagram of a memory unit for storing the number of spectral components of a band; FIG. 5 shows a synchronization pattern in an encoder for monaural audio broadcasting signals according to the present invention. FIG. 6 is a block diagram of a pulse generator; FIG. 6 is a block diagram of a monaural sound broadcast signal according to the present invention; 7 is a block diagram of a code converter in a decoder according to the present invention; FIG. 2 is a block diagram of a synchronization pulse generator in a decoder for a noral acoustic broadcast signal; FIG. Figure 8 shows the encoder and decoder equipment for monaural audio broadcasting signals according to the present invention. FIG. 9 is a timing diagram showing the performance of the stereo sound broadcast signal according to the present invention. is a block diagram of an encoder and a decoder for; FIG. 10 shows the numerical performance in the encoder for stereo sound broadcasting signals according to the present invention. FIG. 11 is a block diagram of a computing unit; FIG. 11 is a block diagram of a computing unit; is a block diagram of a digital filter unit in an encoder for; FIG. 12 shows the stereo signal in the encoder for stereo audio signal according to the present invention. 2 is a block diagram of a signal processor for signals carrying information about signals; FIG. 13 shows a buffer in an encoder for a stereo audio broadcast signal according to the present invention. FIG. 14 is a block diagram of a stereo sound broadcast signal according to the present invention. FIG. 15 is a block diagram of a buffer memory in a decoder for the present invention. of a stereo signal recovery unit in a decoder for such a stereo audio broadcast signal. FIG. 16 is a block diagram; FIG. 16 is a code for a stereo sound broadcast signal according to the present invention; 3 is a time chart showing the functions of the digital filter unit in the converter.

Preferred embodiment A system for encoding and decoding audio broadcasting signals according to the present invention includes an encoder and a decoder. Equipped with a sign.

The encoders for monaural audio broadcast signals are connected in series and the input is connected to the encoder. A low-pass filter 1 (FIG. 1) constituting the input, and an analog-to-digital converter 2 , the output of which is connected bit by bit to the corresponding input of the buffer memory 3. There is. The output of the buffer memory 3 is a spectral conversion unit for acoustic broadcasting signals. 4, and its output is connected bit by bit to the data input of code converter 6. It is continued. Control input cuff of code converter 6, 8 corresponds to control pulse generator 9 connected to the input. The inputs 10 and 11 of the generator 9 are the spectrum of the critical audio band. driven by a signal from the output of the memory unit 12 for storing the number of components; The control inputs 13, 14, 15 of are connected to the corresponding outputs of the generator 9.

The encoder also comprises a multiplexer 16 whose input is the output 17 of the transcoder 6. ．． 18. The control inputs 19, 20 of the multiplexer 16 are connected to the generator 9 is driven from an appropriate output. Furthermore, the encoder is equipped with a synchronization pulse generator 21. The output 22 is connected to the analog-to-digital converter 2, the buffer memory 3, and the spectrum Connected to clock inputs of converter unit 4, converter 6, and multiplexer 16 has been done. The output 23 of the generator 21 is connected to the buffer memory 3 and the spectrum clock conversion unit 4, generator 9, number memory 12 and multiplexer 16. connected to the dock input. The output 24 of generator 21 is connected to the corresponding clock of generator 9. output 25 is connected to the corresponding input of generator 9 and multiplexer 16. and its output constitutes the output of the encoder.

The decoder for monaural audio broadcast signals comprises a demultiplexer 26, whose input The power is the input of the decoder and is connected to the output of multiplexer 16. Demaru The outputs 27, 28 of the multiplexer 26 are connected to the data inputs of the transcoder 29. Ru.

The decoder further includes a direct link whose data input is connected bit by bit to the output of the converter 29. a buffer memory 30 connected to the column, an inverse spectral conversion unit for acoustic broadcasting signals; unit 31, digital-to-analog converter 32 and its output is the output of the decoder. A low-pass filter 33 is provided. Furthermore, the decoder is equipped with a control pulse generator 34. and its outputs 35, 36, 37, 38 drive converter 290 control inputs. Sara , output 38 is connected to the buffer memory 300 control input, and output 35.36 is connected to the buffer memory 300 control input. 2. Drive the corresponding input of multiplexer 26. The control input of the generator 34 can be critical. Output 39 of number memory unit 41 for storing the number of spectral components of the hearing band ．． 40 and its control input is connected to the output 42.43 of the generator 34. Ru.

The decoder further comprises a synchronization pulse generator 44, the input of which is connected to the demultiplexer 2. 6 and the corresponding inputs of the transcoder 29 and the generator 34. There is. The output of the demultiplexer 26 is connected to the generator 34, the number memory unit 41, the buffer connected to the file memory 30 and the corresponding inputs of the inverse spectral transformation unit 31. It is. The output 47 of generator 44 is connected to the clock input of converter 29 and generator 34. It is continued. The output 48 of the generator 44 is connected to the buffer memory 30 and the reverse stream, respectively. The clock input of the spectral conversion unit 31 and the digital-to-analog converter 32 connected to power.

The low-pass filter 1 is realized by a known circuit (M, U, Bank.

0, A, Klimova, “Low-pass filter of di digital receiver''.

Moscow, 1984. Tekhnika 5redsto avyaz i, TRPA 5eries.

1ssue 3. vol, V, p, 90- (Russian)). analog-de The digital converter 2 is designed with a commercially available A2884 integrated circuit manufactured by Motorola. bag The file memory 3 is realized by a known circuit (B, F).

designed with integrated circuits'', Moscow, Radio 1Avyaz, 1984. p, 56-(ro) Sian)). Commercially available integrated circuits, such as AM manufactured by Advanced Micro Devices A 29540 Fourier transform processor can be used as the spectral transformer 4.

A block diagram of the code converter 6 is shown in FIG. Converter 6 is the exponent of the largest component A detector 49 and a buffer memory 50 are connected to each other for code conversion. configuring the data input of converter 6. The control input of the detector 49 is the control input of the code converter 6. cuff, connected to the corresponding control output of the pulse generator 9 (FIG. 1); The clock input of the detector 49 is connected to the output 22 of the synchronous pulse generator 21 (Fig. m1) It's there. connected to the corresponding input of the detector. The control input of register 51 is The code converter 60 comprises a control input cuff and a control pulse generator 9 (FIG. 1). The clock input of register 51 (Fig. 2) is connected to the corresponding output, and the clock input of register 51 (Fig. 2) is connected to the output 22 of the gas generator 21. The output of register 51 (Figure 2) is The output 17 of the code converter 6 and the corresponding data of the multiplexer 16 (m1 diagram) input and the corresponding group of data inputs of floating point encoder 52 (FIG. 2). connected, the output of which constitutes the output of the transcoder 6 and the multiplexer 16 (Fig. ) is connected to the corresponding data input of the The remaining data inputs of encoder 52 The groups are connected bit by bit to the output of the buffer memory 50, and connected to the encoder 52 and the buffer memory 50, bit by bit. The clock input of the buffer memory 50 is the output 22 of the synchronous pulse generator 21 (FIG. 1). It is connected to the.

A block diagram of the control pulse generator 9 is shown in FIG.

The control pulse generator 9 is equipped with a pulse counter 53, and its output is compared bit by bit. connected to one group of inputs of comparator 54 and the other group of inputs of comparator 54 constitutes the input 10 of the generator 9 and is connected to the corresponding output of the memory 12 (FIG. 1). It is. The output of comparator 54 is one of the outputs of generator 9 and memory unit 12 is connected to the control input 13 (FIG. 1) of the. Generator 9 is further connected in series. The inputs of the counters 53,55 are connected to each other, and the inputs of the counters 53,55 are connected to each other. The input of counter 56 constitutes the clock input of generator 9 and synchronized pulse generator 21. They are connected to outputs 23, 24, and 25 of (Figure 1), respectively. Coun The output of the generator 55 (Fig. 4) constitutes the output of the generator 9 and is 1) is connected to input 15 of FIG. The output of counter 56 (FIG. 3) is bit connected to one group of inputs of comparator 57 and connected to the other group of inputs of comparator 57. The loop constitutes the generator 90 input 11 to the corresponding memory unit 12 (FIG. 1). connected to the output. The output of the comparator 57 (FIG. 3) is sent to the memory unit 12 ( Drives control input 14 of FIG. 1) and one input of pulse counter 58 (FIG. 3). However, the other input of the pulse counter 58 is the clock input of the generator 9, which is a synchronous pulse input. It is driven from the output 25 of a pulse generator 21 (FIG. 1). The output of counter 58 is connected to the input 59 of the flip-flop 60 and connected to the input 59 of the flip-flop 60 is connected to the output of the comparator 57, and the output of the flip-flop 60 is connected to the output of the generator 9. One controller 19 of the multiplexer 16 (FIG. 1) and the inverter 62 (the third (Figure) is connected to the input. The output of the inverter 62 constitutes the output of the generator 9. It is connected to a control input 20 of multiplexer 16 (FIG. 1). Generator 9 (No. 3) is also equipped with a pulse counter 63, one input of which is connected to the output of the comparator 54. The other input constitutes one of the clock inputs of generator 9 to generate synchronized pulses. 21 (FIG. 1). Output of counter 63 (Fig. 3) power is connected to one input of flip-flop 64 and the other input to comparator 5. 4, the output of the flip-flop 64 constitutes the output of the generator 9. The controller cuff of the transducer 6 (FIG. 1) is connected. The output of counter 63 is It is also connected to the inputs of the pulse counter 65 and flip-flop 66 which are connected in series. the other input of counter 65 constitutes one of the clock inputs of generator 9 The flip-flop 66 (third The output of the converter 6 (Fig. It is connected.

A block of memory unit 12 for storing the number of spectral components of the critical audio band. A block diagram is shown in FIG. The memory unit 12 includes a pulse counter 67. one input constitutes the memory unit 120 input 13 and is connected to the generator. 9 and the other input is connected to the corresponding output of memory unit 12. It is an input and is connected to the output 23 of the synchronous pulse generator 21 (Figure 2). mosquito The output of counter 67 (Figure 4) is connected bit by bit to the input of read-only memory 680. The output constitutes the output of the memory unit 12 and is connected to the generator 9 (Fig. 1). ) is connected to input 10 of the The memory unit 12 (Figure 4) is a pulse counter. 69, the input of which is connected to the controllers 14 and 15 of the memory unit 12. connected to the corresponding output of generator 9 (Fig. 1), whose output is bit by bit is connected to the input of the read-only memory 70, and the output of the read-only memory 70 is constitutes the output of the memory unit 12 and is connected to the input 11 of the generator 9 (FIG. 1). ing.

Counters 67 and 69 are designed using commercially available integrated circuits 5N7400 series. The read-only memories 68 and 70 use integrated circuits MM6300 series. Designed with

The synchronous pulse generator 21 (Fig. 5) is equipped with a crystal controlled oscillator 71, whose output is Drive frequency dividers 72, 73, 74, 75, their outputs are respectively generators 21 outputs 22.23.24.25. The crystal controlled oscillator 71 is a known circuit. Road (L, M, God’denberg, “Digital devices Designed with integrated circuits in "communications technology", -Moscow , 5vyaz.

1979, p. 76, (Russian)). Frequency divider 72°7 3.74.75 is realized by a commercially available 5N7400 series counter.

The multiplexer 16 and the demultiplexer 26 are constructed using known circuits (L, S, Levin , M, A, Plotkin Digital 1nfor+r+ationtr anmission systems'', -Moscow, Radio i 5vyaz, 1982゜p, 87. (Russian)).

The code converter 29 of the decoder is realized as shown in block D7 of FIG. A code register 76 is provided, the first input of which constitutes the data input of the code converter 29. is connected to the output 27 of the demultiplexer 26 (FIG. 1), and its second input constitutes the control input of the code converter 29 (FIG. 6) and controls the control pulse generator 34 (first (Fig. 1) and its third input is connected to the output 37 of the demultiplexer 26 (Fig. 1). is connected to output 45 of. The output of register 76 (Figure 6) is compared bit by bit. The output is connected to the input of the register 790 input cuff 8 and the pulse counter 80 and one of its inputs.

The output of pulse counter 80 drives the input of comparator 77 bit by bit. counter 80 and the remaining two inputs of register 79 are connected at a common point to the clock of sign converter 29. Serves as a lock input and is connected to the output 47 of the synchronization pulse generator 44 (Figure 1). It is.

The code converter 29 (FIG. 6) further includes a mantissa sign register 81, one of which The input of the converter 29 constitutes the data input of the demultiplexer 26 (FIG. 1). ), one other input of which is connected to the output 4 of the demultiplexer 26. 5, the third input of which constitutes the transcoder 290 control input and outputs the control pulse. is connected to the output 36 of a gas generator 34 (FIG. 1). Each input of register 79 is are respectively connected to the inputs of the counter 80 and serve as control inputs of the code converter 29. and is connected to the output 35 of the control pulse generator 34 (FIG. 1). register The output group 82 of 81 (Fig. 6) is connected bit by bit to the input of the register 79 and output 83 is connected to one of the register 840 inputs and its remaining inputs are connected to the sign converter 29. A control input is configured and connected to the output 38 (FIG. 1) of the control pulse generator 34. Ru. The output of register 79 (FIG. 6) corresponds bit by bit to the corresponding input of register 84. The output of the converter 29 is connected to a buffer memory for each bit. It is connected to the data input of memory 30 (FIG. 1).

Registers 76, 79, 81, 84 (Figure 6), comparator 77, and counter 8 0 is realized with a commercially available integrated circuit 5N7400 series, and the configuration of the buffer memory 30 is The total capacity is the same as that of buffer memory 3.

The inverse spectral conversion unit 31 is the same integrated circuit as the converter 4 (FIG. 1). . The digital-to-analog converter 32 is designed with a Motorola A2854 integrated circuit. It will be done. The low-pass filter 33 has a similar circuit configuration to the low-pass filter 1 of the encoder.

The control pulse generator 34 is realized in the same way as the generator 9 and includes a memory unit 41 and and 12 are of the same design.

A block diagram of the synchronous pulse generator 44 is shown in FIG. 5, the input of which constitutes the generator 440 input and demultiplexer 2 6's output 45 (Fig. 1), and its output is connected to the frequency divider 86 and and 87 inputs. The outputs of frequency dividers 86 and 87 are output to generator 4. 4 constitute outputs 47 and 48, respectively. The frequency multiplier 85 is a known circuit. road technology (1,Kh.

Rizkin “Frequency multipliers and di viders”, Moscow.

5vyaz, 1976, p, 124. -In　Ru5sian) , frequency dividers 86 and 87 are designed with commercially available 5N7400 series counters. Figure 8 shows the functions of a system for encoding and decoding monaural audio broadcasting signals. Fig. 1 is a time chart showing the output of the spectrum converter 4 (Fig. 1). Denote a sequence of code words representing spectral components at t, where t. oh and tl are the spectral components of the acoustic broadcasting signal sample consisting of N values of interest. are the start and end points of the codewords, respectively, and b, c, d, e) converter 60 input cuff, 8 and input 19 of multiplexer 16 ．． The signal wave arriving at the output of the encoder control pulse generator 9 (first field) applied to the encoder control pulse generator 20 where t2 and t are the spectral components of the sample of the acoustic broadcast signal. These are the start and end times of the pulse train that controls the encoding process, f, g, h, i) are the outputs 37, 36.35.3 of the control pulse generator 34 of the decoder 8 (Fig. 1), where t4 and t are acoustic broadcast signals. A pulse sequence that controls the process of decoding the spectral components of a sample of N values of These are the start and end times of each session.

The system for encoding and decoding a monaural audio broadcast signal according to the present invention is as follows. functions.

A sequence of acoustic broadcast signal values is divided into samples of N values, and a sequence of N components is divided into samples of N values. The spectrum is calculated. The resulting components for the instantaneous spectrum are 24 critical It is divided into 24 groups according to the listening band. The boundaries of these bands are mono In E, Zveker and R, Fe1dkeller''Thee ar as an information receiver’ (Mosco W, 5vyaz, 1971) are shown in Table 27.1. 24 pieces Each frequency group is defined as “the largest spectral component in absolute value is separated”. used to set the exponent in code with block-by-block floating point numbers. and then the spectral components of this frequency group are coded according to the value of this index. become a standard. The number of bits of the sign (code) of the mantissa is given by the frequency group. is chosen to guarantee the desired coding error for the largest spectral component of the group.

The number of bits in the exponent code must cover the entire variation range of the spectral components. Since the variation range is 16 bits, =4 is selected in the end. each All other components in the frequency group that have a level less than the level of the largest component. The coding error of all spectral components may exceed a predetermined value. Because so This is because they cannot be heard within the critical audible band due to the effect of masking. maximum The tolerance for the coding of the components is at least 30 dB, which is the margin of coding error. below the level of the coded component to ensure audibility. 30dB code In order to obtain a good signal-to-noise ratio, the bit length of the mantissa code is sufficient to be 5 bits. , that is, =5. Therefore, to code a sample of N values, For this purpose, a binary symbol of NK and +24KP is required. The sample length N is The interval T of spectrum analysis is approximately equal to the audible resolution, that is, T = (N/Fd) =30 msec, where Fd is the discrete repetition rate. discrete At the repetition rate Fd = 32 to 7, the sample length N is N = 1024, and Therefore, 1024.5+24.4 binary symbols are used to encode the sample value. It becomes necessary. Since the sampling rate is Fd/N, the bits at the encoder output Trait V = 163 bits/sec (1) That is, it is less than half of the pulse code encoder using floating points per block. .

Sequence of initial values from codewords for exponent and mantissa parts of spectral components In order to recover the code and performs inverse spectral transformation to obtain samples of N values of the acoustic signal as It is restored in the intermediate area. Fourier transform, discrete cosine transform, Hadamard transform, etc. Any of the known orthogonal transforms can be used, such as the discrete cosine transform This is preferable because the quality of the audio signal is high.

The encoder for mono signals works as follows.

The analog audio broadcast signal reaches low-pass filter 1 (Figure 1) where it is input The signal bandwidth is limited to a maximum frequency F=15 kHz. low pass filter The signal from the output of 1 reaches the analog-to-digital converter 20 input, where The signal is sampled at a discrete frequency Fd = 32kHz and the result is It is encoded into a 16-bit linear code. of the value from analog-to-digital converter 2 The code word is generated at the Ft clock frequency and goes to the input of the buffer memory 3. be introduced.

The capacity of buffer memory 3 is 2N x 16 bits, where N is the spectral analysis is the number of signal sample values used for Buffer memory 3 stores a series of code words. The output of the analog-to-digital converter 2 is delayed by N/r seconds and the output of the analog-to-digital converter 2 is converted into N codes. The word is matched to the input of the spectral converter 4 which processes it.

N codewords corresponding to the first N values of the audio broadcast signal are stored in the buffer memory. 3, they are serially read out and introduced into the spectral converter 4. where the spectrum of a series of N values is calculated. Thus, time The acoustic broadcast signal is subjected to spectrum analysis in real time during ΔT=N/Fd.

The 16-bit codeword of the spectral component, that is, the coefficient of the discrete spectral transform is It is generated serially at the output of the spectral converter 4. Pitch f=Fd/N The N coefficients of the spectral decomposition uniformly distributed along the frequency axis are the N signal values (usually N is chosen such that N=23, where and S is a natural number S=1. 2. ...-9s1, which is a fast spectral conversion algorithm. ). The first coefficient corresponds to f0=0 and the last coefficient corresponds to the frequency of f N-+ = Fd (11/N). Therefore, N The spectrum of a sample of an audio broadcast signal consisting of values is converted into a 16-bit linear code. is represented by N numbers. These at the output of the spectral converter 4 The timing of the number codeword is shown in the time chart of Figure 8a, which Here, blocks of 16-bit codewords are shown as rectangles.

The code converter 6 (Fig. 1) converts the 16-bit linear code of the spectral components into blocks. Code with floating point, i.e. pulse code change with floating point per block. Convert to the code used in the key (habo simultaneous companding). The difference in this invention is First, the sequence of spectral component signals is a temporal acoustic emission. used instead of a sequence of transmitted signal samples, and secondly, a constant exponent value The length of a block encoded with the coefficient method (i.e., coefficient method) is variable, and the control parameter It is determined by the signal reaching the input cuff of the code converter, 6, 8 from the output of the pulse generator 9. The length of the block is set. The time charts of these signals are shown in the 8th column. This is shown in Figures b and 8c.

The code word of the spectral component reaches the data input 5 of the code converter 6 (Fig. 1). At the same time, the input of the detector 49 (Fig. 2) and the buffer memory 50 is also reach. The latter operates on codewords (whose capacity is N) and converts them into Shift as soon as the next code word arrives. Detector 49 compares the code words; Then, the code word is selected according to the maximum value (absolute value) of the spectral component. determine the exponent value equal to the number of zeros in the most significant bit of the exponent sign word; occurs. Once the required number of code words have been compared, the output of generator 9 (FIG. 1) is The signal from the force (igb diagram) is input to the detector 49 which constitutes the code converter 60 input cuff. power is applied to enable reading of the generated exponent code word. At the same time, this The signal inputs this exponent sign code to the exponent sign register 51 (Figure 2). . Buffer memory of all N code words of the spectral components of the signal samples When the input to the generator 9 (Fig. 8b) is completed, the signal from the output of the generator 9 (Fig. 8b) is The control power 8 of the converter 6 is reached and the writing of the last code word, i.e. the detector 49 (Figure 2) of the value of the 24th sample from the output of the sign word register. Enables writing to 51. The last 24th code word is placed in register 51. When written, a rising pulse (FIG. 8c) is applied to the control input 8 of the code converter 6. and the arrival of this pulse at a particular input of register 51 causes the register to Rewriting the code word of the first exponent from the output of register 51 to encoder 52 , but now floating point code is implemented. The output of this code converter 6 The code word from power 17 reaches a particular input of multiplexer 16 (FIG. 1). . At the same time, the sign word of the first spectral component of the signal sample mentioned so far is A code is generated at the output of buffer memory 50 and at the input of encoder 52. where the code word is the code word designation from the output of register 51. shift at the encoder 520 input by the number of bit positions set by the number will be played. In this way, the code word for the mantissa of the spectral component is generated, from the output 18 of the code converter 6 to the input of the multiplexer 16 (m1 diagram) . Special spectral components encoded by fixed values of exponents are stored in register 51 to the other input of encoder 52 which receives the new exponent code word from the output of This causes the codeword of the spectral component to change to the sign of this new exponent. shifted by the number of positions set by the number word. This operating procedure is currently The code words of all 24 exponents of the current signal sample are read from register 51. Continue until Subsequent N value samples are encoded in a similar manner .

The multiplexer 16 (Figure 1) is configured so that a regular pulse train appears at its output. In this way, the exponent and mantissa parts of the code word are reorganized in time. Multiplexer 1 The repetition rate of the pulses at the output □ of 6 is described by the following equation.

Fout = (2Kp 1NK,) F d/N, (2) Here, KP is The capacity of the exponent bits, K, is the capacity of the mantissa bits, and N is the capacity of the value in the sample. It is a number.

Analog-digital converter 2, buffer memory 3, spectrum converter 4, code converter 6, control pulse generator 9, number memory 12 of spectral components, and multi The function of the plexer 16 is regulated by a synchronization pulse generator 21. This synchronization Pulses with a repetition rate F, /H are generated at the output 22 of the pulse generator 21, and the output 23 A pulse with a repetition rate Fd is generated at the output 25, and a pulse with a repetition rate Fout is generated at the output 25. Su appears.

Control pulse generator 9 functions as follows. Counter 53°55, 63.65 The count input of constitutes the clock input of generator 9, and the count input of synchronous pulse generator 2 1 (FIG. 1) receives a pulse train with a repetition rate of 16Fd from the output 24. The repetition rate of corresponds to the bit rate of the codeword of the spectral component. same Pulses with a repetition rate Fd/H from the output 23 of the periodic pulse generator 21 (Fig. 1) The column is applied to the set inputs of counters 53 and 55 and used to calculate the spectrum. Determine the start of N sample values of the acoustic broadcast signal to be used and similarly Sets the start of the spectral component of the sample value. Output 2 of synchronous pulse generator 21 The pulses from 3 trigger counters 53 and 55 (FIG. 3). spectrum composition The sign number of the minute is generated at the output of the counter 53 and the first group of the comparator 54 , whose second group of inputs is this cycle from the output of number memory 12. Receives the sign number of the last spectral component in the wavenumber group, where criticality is possible. The number of spectral components in the hearing band is stored. Comparator 54 (Figure 3) At the same time that the sign is input to the inputs of group 1 and group 2, this comparator This signal triggers the counter 63 and the flip-flop 6. 4 is set to logical value "1". Furthermore, the output signal of the comparator 54 is stored in the number memory 12. (FIG. 1), the next frequency from a particular output of number memory 12 is transmitted to input 13 of FIG. Enables reading of the code number of the last spectral component of the group. counter 6 3 (Figure 3) counts and receives the required number of pulses that reach its count input. When a signal is generated and the flip-flop is switched from logical value “1” to logical value “0”, Together, the flip-flop 66 is set to the logical value "l". Furthermore, the counter The output signal of 63 triggers a counter 65 where the required number of pulses is counted. Similarly to the counter 63, the flip-flop 66 is changed from the logical value "1" to the logical value " In this way, flip-flops 64 and 6 6 has a pulse train (8th b.

80) and controls the function of the code converter 6 (FIG. 1).

After counting the required number of pulses, the counter 55 (Figure 3) emits a signal. triggers a counter 56 whose input is connected to the synchronous pulse generator 21 ( It receives a pulse train with a repetition rate Fout from the output 25 of the m1 diagram). counter The sign number of the pulse reaching the input of 56 appears at its output and is transmitted to the comparator 57. , the frequency given to the second input of the comparator 57 from the output of the memory lJ12 (Fig. m1) A comparison is made with the number of codes of the least significant bits among the codes of the exponent parts of several groups. child Simultaneous input of these numbers generates a signal in the comparator 57 (Fig. 3), and the counter 5 8 is operated and the flip-flop 60 is set to the logical value "1". Furthermore Also, the signal from the output of the comparator 57 reaches the input 14 of the memory 12 (Fig. 1). and reads the code number of the exponent part of the next frequency group from a specific output of the memory 12. make it possible. Counter 58 (FIG. 3) represents the bit capacity in the code word of the exponent. When the number of pulses equals the amount, it stops counting and generates a signal, and the flip-flop 60 to switch it to a logic "0" value. flip flop 60 A pulse is generated at the output of multiplexer 1 (Fig. i8d), and this pulse 6 (Fig. 1) is transmitted to the control human power 19 and the input of the inverter 62 (Fig. m3), and then Then, a pulse is generated at the output of the inverter 62 (Fig. i8c), and the multiplexer 16 ( ilEn) is applied to the control input 20 of the ilEn).

The number memory 12 in which the number of spectral components in the critical audio band is stored operates as follows. function. The count inputs of counters 67 and 69 are connected to specific outputs of generator 9 (Figure 3). These set inputs are connected to the synchronous pulse generator 21 (fourth It receives pulses from the output 23 of the generator 9 (FIG. 3) and a particular output of the generator 9 (FIG. 3). child These pulses operate counters 67 and 69 (FIG. 4). Output of counter 67 The address code of the last spectral component of the frequency group is emitted at the read-only memory 68 is accessed where these code numbers are stored. From there, these code numbers are read out and sent to the input 10 of the generator 9 (Fig. 3). Reportedly. The parameter corresponding to the least significant bit of the code word of the exponent of the frequency group. An address code of the number of russ codes is generated at the output of the counter 69 (FIG. 4). . These addresses are used to access read-only memory 70; The code number is transmitted from the output of the read-only memory to the generator 90 input 11 (Figure 3). It will be done.

The system decoder works as follows. Output of multiplexer 16 (Fig. 1) floating point code bits per block representing the spectral content of the audio broadcast signal from are passed to the input of multiplexer 26, where the input column is the exponent part Separated into a sequence of code word bits and a sequence of significand code words . Demultiplexer 26 also senses the pulse repetition rate Fout and The repetition rate sequence is communicated to the output 45 of the demultiplexer 26. Furthermore, demultiplexing The lexer 26 extracts a periodic lock signal from the input continuous pulses and uses this signal. The signal is a spectrum corresponding to N sample values of a continuously transmitted acoustic broadcasting signal. Specifies the start of a block of file components. Periodic locking pattern with repetition rate F, /H The signal appears at the output 46 of the demultiplexer 26.

The code converter 29 converts the floating point numbers in each block into 16-bit linear fixed point numbers. Convert code to code word.

The sign bit of the exponent from the output 27 of the demultiplexer 26 is the repetition rate Fou It is input to the register 76 (FIG. 6) at t, and the output 45 of the demultiplexer 26 is read out. The control signal (Fig. 8f) from the output 37 of the generator 34 (Fig. 1) ) arrive, these sign bits are stored in register 76 in the form of a parallel code. to the input of the first group of comparator 77 (FIG. 6), and the second group receives the signal from the output of counter 80, and its count input receives the signal from the output of counter 80, and its count input Pulses of clock frequency Fout from output 47 of pulse generator 44 (FIG. 1) receive. Comparator 77 (FIG. 6) generates a signal to control register 79. At the same time, the sign bit of the mantissa of the counter 80 is reset and the sign bit of the mantissa of the frequency Fout is input. Every one bit of the mantissa is transmitted to the sign register 81 (FIG. 6). Generator 34 Simultaneously with the arrival of the control signal (Fig. 8g) from the output 36 (Fig. 1) of the register The signal bits from 81 are rewritten into 16-bit register 84 (Figure 6). enters, becomes the signal bit position in fixed-point notation, and the other K, − The 1-bit mantissa is stored in the least significant bit of the 15-bit register 79 in the form of a parallel code. where they are transmitted to the output 47 of the synchronous pulse generator 44 (the 1) at a clock frequency pout reached from 1). Generator 3 The signal specifying the start of shifting of the mantissa bits from the output 35 of 4 (Fig. 8h) is is applied to the control input of register 79 (FIG. 6).

This signal also triggers counter 80 (Figure 6) to count the number of shifts. Ru. When the preset number of shifts is completed, the counter 80 is stored in the register 76. generate a code combination that matches the code word of the exponent. this combination The output reaches the second input of comparator 77 and transfers the contents of register 79 to register 84. Generates an instruction to rewrite the bit position. At the same time, this instruction causes counter 80 to Reset to 0. In this way, the fixed-point 16-bit code word is generated by register 84 and from output 38 of generator 34 (FIG. 1). The signal is transmitted to the buffer memory 30 simultaneously with the arrival of the control signal (Fig. igi). bag The frame memory 30 delays the arrival of successive code words by a period twice Fd/N. ie, delayed by the duration of code word 2N.

A buffer memory 30 receives the code words of the spectral components from the output of the converter 29. The delivery speed is adjusted to match the processing speed of the inverse spectral conversion unit 31. where N sample values are recovered from their N spectral components. . The 16-bit code word of the audio broadcast signal is inversely spectral coded in the form of parallel codes. The output of the conversion unit 31 is transmitted to the digital-to-analog converter 32, where The quantized value of the audio broadcast signal is recovered. Digital-analog converter 3 2 is equipped with a low-pass filter 33, where the quantized value is smoothly output, In this way, the first analog acoustic broadcast signal with a bandwidth of up to F = 15kHz was created. It will be restored.

In this way, the input signal at the output of the system's encoder satisfies equation (1). is represented by a bitstream transmitted at a rate specified by Recover the first analog signal from this bitstream.

An experimental study of this system for encoding and decoding acoustic broadcast signals was Pull length N = 1024, sign word bit capacity of exponent part = 4, sign of mantissa part No. word pit capacity, = 5, and discrete repetition rate Fd = 32 Hz. . The bit rate ■ at the output of the encoder is 163 kilobits per second, i.e. This is half the speed of the IP system. A sound evaluation expert can use the system according to the present invention. The quality of the audio broadcast signal after encoding and decoding in the system is 16 bits. The quality of the initial digital signal is inferior to that of the value encoded with the original linear code. It points out that there is no.

The encoder for stereo audio broadcast signals is for the left channel of the stereo connected in series. in series with the main low-pass filter 88 (FIG. 9) and the main analog-to-digital converter 89. An auxiliary low-pass filter 90 for the right channel of the connected stereo and an auxiliary analog-to-digital A digital converter 91 is provided. The inputs of the low pass filters 88 and 90 are the inputs of the encoder. Configure input. The output of the analog-to-digital converter 89 is a numerical calculation unit. The input 94 of the numerical calculation unit 93 is connected bit by bit to the input of the numerical calculation unit 93. Each bit is connected to the output of the analog-to-digital converter 91. Numerical calculation unit The group of outputs 95 of the unit 93 is the first group of data inputs of the buffer memory 96. connected to the loop bit by bit, and also connected to the input of the digital filter unit 97. is also connected. The output 98 group of the numerical calculation unit 93 is a digital filter. Connect each bit to the corresponding input of the filter unit 97 and the input of the signal converter 99 where the signals carrying the information of the stereo sound broadcast signal are processed.

Output group 100 of digital filter unit 97. ,...

100,,100□3. . . , 100□ is a bit input to a specific input of the signal converter 99. The group of outputs 101 of the signal converter 99 is connected to the buffer memory. connected to a second group of data inputs of memory 96. Signal converter 99-1 02. ,..., 10. The outputs of the groups are sent to the auxiliary code converter 103. ,... , 103. of such a transcoder. Each piece has two groups of outputs. Code converter 103. ,..., 1 The output of the first group of 03° is the input 1041+... of the multiplexer 105. , 10 bills, and a code converter 103. ,..., 103. the second of The output of the group is the input 106. of the multiplexer 105. ,...

106, is connected to.

The encoder for stereo audio broadcast signals further comprises a spectral conversion unit 107. The input 108 of the spectral conversion unit is connected to the output of the buffer memory 96. The output of the spectrum conversion unit is connected bit by bit, and the output of the spectrum conversion unit is connected to the data of the main code converter 109. Each bit is connected to the data input. Control input 110 of main code converter 109 and 111 is connected to a specific output of the control pulse generator 112. Code converter 1 Outputs 113 and 114 of 09 are connected to specific inputs of multiplexer 105. Ru.

The encoder further comprises a memory 115 in which the spectrum of the critical audio band is stored. The number of components is stored, and inputting this number 116.117.118, Outputs 119 and 120 provide bits to specific outputs and inputs of control pulse generator 112, respectively. The outputs 121 and 122 of the control pulse generator are connected to each 105. In addition, the symbol for stereo sound broadcast signals is The encoder is equipped with a synchronous pulse generator 123 whose output 124 is connected to a buffer memory. memory 96, spectrum converter 107, code converter 109, and multiplexer 105 specific clock input. The output 125 of generator 123 is buffer memory 96, spectrum converter 107, control pulse generator 112, memory 115, and a particular clock input of multiplexer 105.

The output 126 of the synchronization pulse generator 123 is a special clock signal of the control pulse generator 112. drive input. The output 127 of the synchronization pulse generator 123 is the control pulse generator 1 12 and a particular clock input of multiplexer 105. sync pal The output 128 of the signal generator 123 is converted to an analog-to-digital converter 98.91, a numerical value Arithmetic unit 93, digital filter unit 97, signal converter 99, sign conversion exchanger 103. ,...

1031, buffer memory 96, and multiplexer 105 specific clocks connected to the input. The output 129 of the synchronous pulse generator 123 is sent to the signal converter 9 9, code converter 103. ,..., 1031, buffer memory 96, and multiple It is connected to a particular input of multiplexer 105.

The decoder for stereo sound broadcast signals comprises a demultiplexer 130, which One input is the input of the decoder, this demultiplexer is the main transcoder 131 , buffer memory 132, inverse spectrum conversion unit 133, and buffer memory 132, It is connected in series with the memory 134. Outputs 135 and 1 of demultiplexer 130 36 is connected to a specific input of the code converter 131.

The decoder also includes m auxiliary code converters 137 . ,..., 137. equipped with Each transcoder has two data inputs.

Code converters 13L,..., 137. The first data input of 130 output 138. , ..., receives the signal from 13L, and converts the code to the code converter 13. 7. ,..., 137. The second data input of is the output of demultiplexer 130 139. ,..., 139. It is connected to the. Code converter 137. ,... , 137. The output of the stereo signal decoder 141 is the data output 140 . ,... , 140. are connected bit by bit. Furthermore, the decoder is a digital filter A unit 142 is provided, and the data input of this unit 142 is a buffer memory. The buffer memory 134 is connected to the output group 143 of the buffer memory 134 bit by bit. Output group 144 is connected to a particular input of stereo signal decoder 141 and Input 145 . of rheo signal decoder 141 . , -..., 1451. ,, are digital It is driven by the output of filter unit 142.

The output 146 of the stereo signal decoder 141 is the main digital-analog signal connected in series. output 149 is connected to the converter 147 and the main low-pass filter 148. An auxiliary digital-to-analog converter 150 and an auxiliary low-pass filter 151 are connected to each other. The outputs of low-pass filters 148 and 151 constitute the output of the decoder. Ru.

The decoder further includes a control pulse generator 152, in which the number of spectral components in the critical audio band is recorded. It is provided with a number memo 1J153 to be stored and a synchronization pulse generator 154. control Outputs 155°, 156, 157, and 158 of the pulse generator 152 are output to the code converter 131. outputs 155 and 156 are further demultiplexed by 1300 Å. connected to power. The outputs 159 and 160 of the control pulse generator 152 are number memories. 153, and the outputs 161 and 162 of the number memory are connected to specific inputs of the control pulse generator. Each bit is connected to a particular data input of generator 152 .

The output 163 of demultiplexer 130 is connected to generator 154, buffer memo! J13 4, and a code converter 137. ,..., 137. connected to a specific input of There is. The output 164 of demultiplexer 130 is connected to generator 152, converter 131 and and a particular input of generator 154, and output 165 of generator 154 is connected to The control pulse generator 152 is connected to a specific input. Synchronous pulse generator 154 The output 166 of the buffer memory 132 and 134 and the inverse spectral transformer connected to a specific clock input. The output 167 of generator 154 is memory 132 and 134, control pulse generator 152, and code converter 131. Connected to a specific clock input. The output 168 of the synchronous pulse generator 154 is , buffer memory 134, code converter 137 . ,..., 13L, Digitalf filter unit) 142, stereo signal decoder 141, and digital-analog 147.150.

A unit compatible with a system that encodes and decodes monaural audio broadcast signals. and low-pass filter 88.90.148°151, analog-to-digital conversion 89 and 91, code converter 103, ..., 103yo 109.131.13 7. ,-...,137. , spectral signal converter 107, control pulse generator 11 2 and 152, a number memory 115 in which the number of spectral components of the critical audio band is stored; 153, synchronous pulse generators 123 and 154, multiplexer 105, demultiplexer Lexer 130, inverse spectral converter 133, and digital-to-analog converter 147 and 150 are specifically mentioned.

A block diagram of the numerical calculation unit 93 is shown in FIG.

The numerical calculation unit 93 includes an adder 169 and a subtracter 170. Inputs 92 and 94 of unit 93 are connected to adder 169 and subtractor 1700A, respectively. The output of the adder 169 constitutes the output 95 of the numerical calculation unit 93. , the output 98 of the numerical calculation unit 93 is the output of the subtracter 170. Adder 169 and the subtracter 170 are realized by known circuits (U, Titze, K.

5henk “Sem1conductor circuitry”, ar ference book, 1982゜pp, 334.335. -Russian ).

A block diagram of digital filter unit 97 is shown in FIG. This uni The cut consists of two groups of digital filters 171 +, . . . , 171 . and 171. ,,,..., 1712. It consists of Digital filter 1 71. ,..., 171□ and 17L,,..., 1712. .

The inputs of each group are connected to each other, and the 2' inputs of the unit 97 are configured. has been completed. Digital filter 171. ,...

The clock input of 1712 is connected to the output 128 (FIG. 9) of generator 123. The outputs of the digital filters are 1001, ..., 100, respectively. ．． and 100-, , ・-+, 1002. It is composed of.

Digital filter 171. ,..., 171□, using a known circuit configuration It can be realized (U, Titze, K, 5henk"Sem1conduc tor circuit-try”, a reference book, 1 982. p, 429. −Russia; I).

A block of the signal converter 99 for processing information-bearing signals in the stereo sound signal. A track diagram is shown in FIG. The signal converter 99 has m channels. , each channel has an adder 172, a multiplier 173, an adder 174, and a register connected in series. output 1 of switch 176. 77 is connected to a particular input of adder 174. Each channel of m channels The module also includes a register 178 whose data input connects to the output 179 of switch 176. and an adder 180 whose one input connects to the output 179 of switch 1767; A frequency divider 181 is provided, and each input of the frequency divider 181 is connected to a register 178. and an adder 180. Furthermore, each channel has a subtractor connected in series. 182, multiplier 183, adder 184, register 185, and switch 186 The output of switch 186 is connected to specific inputs of adders 180 and 184. It is continued. The first channel adder 172 and subtracter 1820 inputs are digital Output 100 of filter unit 97. ,..., IOL, (Fig. 9) are connected to the adders 172 and subtractors of all other m-1 channels. The input of the calculator 182 is the output 100□ to 100 of the digital filter unit 97. ．． ．． 2.1003-100. ,! ,..., 1000~100□1 Figure 9) are connected to each other. The output of the frequency divider 181 (Fig. 12) is the output of each channel. and the output 102. of the signal converter 99. ,...,102. configure ing. The converter 99 further includes an adder 187 and a subtractor 188 (first 12), and the input of the adder 187 is connected to a specific input of the digital filter 97. Output 100. , , ..., 100□, and the output of the subtracter 188 constitutes the output 101 of the converter 99. Converter 99 furthermore registers 18 9, whose input is connected to the output 98 (Fig. 9) of the numerical calculation unit 93. constitutes one input of a subsequent converter 99, and the output of register 189 is connected to the other input of subtractor 188. Adder 172.174°184, 187, subtracters 182, 188, multipliers 173, 183, and registers 175. The clock input of 185 and 189 is the output 128 of the synchronous pulse generator 123 (Fig. )It is connected to the. Switches 176, 186 (jJ!12 diagram), register 1 The clock inputs of 78, adder 180, and subtracter 181 are output 1 of generator 123. 29 (Fig. 9).

Adder 172.184.180.187 (FIG. 12), subtracters 182 and 188, and multipliers 173 and 183 are realized by known circuit design techniques (U, Titze, K, 5henk''Sem1conductor circuit try'', reference book, 1982.pp, 335.34 0. -Russian).

The frequency divider 181 has a circuit configuration of known technology (P, Rahiner.

P, Gould “Digital signal processing” theory and applications”, Moscow, M IR, 1978, p, 584. -InRu5sian).

Register 175.185. 178, 189 and switches 176, 186 are , is realized by the commercially used integrated circuit 5N7400 series.

A block diagram of buffer memory 96 is shown in FIG.

Buffer memory 96 includes switches 190 and 191. switch 1 The input 90 constitutes one of the inputs of the buffer memory 96 and is connected to the numerical calculation unit 9. 3 (FIG. 9). Input of switch 191 (Fig. 13) is connected to the output 101 (FIG. 9) of the signal converter 99. switch 190 The outputs 197 and 198 of 192.193 of the working memory bit by bit Connected to data input. Outputs 199 and 200 of switch 191 are 194 and 195 data inputs of the recording memory. switch The control input of 190.191 is the output 125 of the synchronous pulse generator 123 (FIG. 9). Driven from. Working memory 192.193.194.195 clock The input is connected to the output 124.128 (Fig. 9) of the synchronous pulse generator 123. , the output of working memory 192.193.194.195 (Figure 13) is Each is connected to an input of switch 196. The switch 196 control input is It is connected to the output 125° 129 (Fig. 9) of the synchronous pulse generator 123, and the switch The output of 196 (FIG. 13) constitutes the output of buffer memory 96 and the spectral It is connected to input 108 (FIG. 9) of signal converter 107.

Switches 190, 191, 196 (Figure 13) are commercially used integrated Circuit SN? 400 series, working memory 192.193. 194.195 is realized by integrated circuits of type MM2141-5.

A block diagram of buffer memory 134 is shown in FIG.

Buffer memory 134 is connected to switches 201, 202, 203 and working memory. It is equipped with 204.205.206.207. Control input for switch 201 are the output 167 (FIG. 9) of the synchronous pulse generator 154 and the demultiplexer, respectively. Connected to the output of lexer 130, the data input of switch 201 (FIG. 14) is Configures the input of buffer memory 134. Output 208.209 of switch 201 ．． 210.211 is bit by bit working memory 204.205.206.2 The clock input of the working memory is connected to the data input of 07, and the clock input of the working memory is outputs 166 and 168 (FIG. 9) of signal generator 154. Work The output of the operating memo IJ 204.205 (Fig. i14) is the input of the switch 2020. The output of the working memory 206, 207 is connected to the input of the switch 203. connected to power. The outputs of switches 202 and 203 (Fig. 14) are constitutes outputs 143 and 144 of buffer memory 134, and outputs 143 and 144 of buffer memory 134, respectively. digital filter unit) 142 (FIG. 9) and stereo signal decoder 141. connected to the input.

Switches 201, 202, 203 (Figure 14) are commercially used integrated Realized by circuit 5N7400 series, working memory 204.205. 206.207 is realized by integrated circuits of type MM2141-5.

A block diagram of stereo signal decoder 141 is shown in FIG. Stereo signal recovery The encoder 141 includes an adder 212 and a register 213 connected in series, and an adder 212 and a register 213 connected in series. It includes a subtracter 214 and a register 215 connected in columns. Adder 212 and certain inputs of subtractor 214 are interconnected to provide input 145 of decoder 141. and is connected to the output 144 (FIG. 9) of the buffer memory 134. . The output of register 213 (FIG. 15) is connected to input 216 of adder 217. , the output of register 215 is connected to the input 218 of adder 219. decryption The multiplier 141 further includes a multiplier 220 . ...2202, register 2211... 221. and 222+...2221 and subtracters 2231...2231 It has m equivalent channels with . All multipliers 220. ...2 20. One input of is the data input of the decoder 141, and the code converter ]371 ...13'L (Fig. 9) is connected to the output. Multiplier 2201...2 The other input of 20° (FIG. 15) is the register 2211...221. to the output of inputs connected to the output of the digital filter unit 142 (FIG. 9). Power 1452...], 45. ．． It constitutes l.

Multiplier 220. ...220. The output of (Figure 15) is sent to register 2 for each bit. 21. ...221. Data input and subtractor 223.・・・・・・223. Other inputs to registers 222 . ...222. receives a signal from the output of It is being done. The outputs of registers 2211...2212 correspond to the channel outputs. inputs 224, . . . 224 . is connected to the input of

The outputs of the subtracters 2231...223° constitute the other channel outputs, and adder 2 19 inputs 2251... are connected to the inputs of 2251. Adder 217 and The outputs of 219 constitute outputs 146 and 149 of decoder 141, respectively, and connected to the inputs of digital-to-analog converters 147 and 150 (Figure 9), respectively. has been done. Adder 212.217.219 (Figure 15), subtracter 214.22 3. ...223. , register 213.215°2211...221. ,2 221...222. The clock input of is the output 168 of the synchronous pulse generator 154. (Fig. 9).

Adders 212.217.219 and multipliers 22071...220. (1st Figure 5) shows the circuit configuration of the known technology (U, Titze, K.

5henk “Sem1conductor circuit”, a re ference book, 1982゜pp, 334.335.340. -1n This is realized by Ru5sian). Register 213.215.221.・・・ ・221. is implemented by the commercially used integrated circuit 5N7400 series. be revealed.

FIG. 6 shows the digital filter 17 in the digital filter unit 97. 1. . . . shows the amplitude-frequency response characteristics of 171□yo (Fig. 11).

FIG. 16a shows filters 1711 and 171 . , , (Fig. 11) amplitude - shows the frequency response characteristics, where f and fl are filters 171 . and 17 1□, is the critical frequency of the passband.

FIG. 16b shows filters 171□ and 171. , -2 (Fig. 11) where f and f2 are filters 171□ and 171. ．． 2nd line This is the critical frequency in the overband.

FIG. 16c shows filter 171. and 171□, (Fig. 11) frequency response is where f, -1 and f are filters 171, 1712 . passing of is the critical frequency of the band.

The functions of the stereo audio broadcast signal encoding and decoding system of the present invention are as follows. It is.

In the encoder of the system, the encoded analog signals of the left and right stereo channels are , is applied to the input of the low-pass filter 88.90 (Fig. A digital converter 89.91 is introduced. The low pass filter 88.90 is a low pass filter. Analog-to-digital converter 89.91 is similar to router 1 (Figure 1). , analog to digital converter 2 (FIG. 1).

The code words for the readings from the left and right stereo channels are analog-to-digital. The code word is generated by a numerical converter 89.91 (Figure 9). calculation unit 93, where half sum x and half differential X- is calculated. Half sum X+ of left and right stereo channels from output 95 The representing code word is applied to a particular input of buffer memory 96.

Stereo information is divided into half-sum X and half-sum of the left and right stereo channels, respectively. The bandpass filter in the digital filter unit 97 for the f-difference X- is derived and encoded according to the corresponding code word by performing the wave ◇The digital filter unit 97 has half sum X+ and half differential m filters 171, -1712 . for signals of lens X-; and 171m+, = 1712. - two equivalent comb filters. Filter The frequency response characteristics of 171, . . . 1712□ are shown in FIG. As a result Then, m filtered half-sum signals X−ゝ,X?ゝ...XC? is di Output 100 of digital filter unit 97 (FIG. 11). ...100° smell m half-difference signals x(j), X (3), , , X (%1 is generated at output 100., , -1002= Ru. These sequences of readings are the half data from the output 98 of the numerical unit 93. It is applied to converter 99 (FIG. 9) along with a signal corresponding to the reference X-.

The converters 99 each receive a pair of filtered signals X, , X-(i = 1.2. . . m), calculate the ratio P.

This is the energy of the channel signal X2' and X.

Energy is calculated in time interval T=N/Fd corresponding to N input signals . Thereby, the energy is thus reduced during the time interval corresponding to N values. Therefore, the ratio P* (i=1.2...-m) is also calculated at this time. One is defined between the intervals. Furthermore, converter 99 converts zero to f according to the equation: . A value of the filtered difference signal X- with a bandwidth up to is also generated.

The converter 99 (FIG. 12) consists of m equivalent filtered signals for )((il and and one channel test is satisfied. filtered The code word of the value of the signal X peeled y, (1) is From the outputs 100 and 100□ of At the input of the subtractor 182, at the output of which the code words are left and right, respectively generated corresponding to the first filtered signals xL and XR of the stereo channels of Ru. The code word is applied to a multiplier 173 and ]83, and the output of the multiplier is , the square of the filtered signal cx'; 2.　cx’;’〕Code word corresponding to 2 code is generated. The energy EL and ER values of the filtered signal are determined by the adder 176 and 186, registers 175 and 185, and switches 176 and 186 is calculated with the help of . The addition cycle is started by the synchronization pulse generator 123. The input of converter 99 is set by the clock signal from output 129 (FIG. 9). to connect the output of register 175 to a particular input of adder 174. This is done by activating switch 176 (FIG. 12).

The second group of adders 1740 inputs the square of the value of the left channel filtered signal EXL ] Receive the code word corresponding to 2.

The result of the addition is added to register 175. Therefore, at the end of the addition cycle Therefore, the register 175 is set to the square of the value of the left channel filtered signal according to equation (6). Memorize the sum. Here, the sum represents the energy EL of the filtered signal. filter The energy of the right channel of the wave signal is also stored in adder 184, register 185 and switch. similarly calculated using switch 186.

When the addition cycle is completed, the output 129 of the sync pulse generator 123 (FIG. 9) The clock signal arrives and switch 176 (FIG. 12) outputs register 175. power to the input of resistor 17g, and switch 186 connects the output of resistor 185 to the input of resistor 17g. Connect to the input of adder 180. Register 178 is used for addition in adder 180. The duration of the operation corresponds to the energy of the filtered signal of the left stereo channel. Delay the code word to be used. At the output of register 178, the code word is Corresponding to the sum EL+E11, which is the energy of the filtered signal of the right stereo channel. is generated and applied to a specific input of frequency divider 181. The other inputs of frequency divider 181 are , receives a code word corresponding to the value EL, i.e. the energy of the left channel signal. take. The frequency divider 181 generates a code word corresponding to the value of the ratio P according to equation (3). Occur.

In channel processing, the ratio p2+...p- is calculated in a similar way. . In the operation of adders 172, 174, 184, multipliers 173, 183, registers The stars 175, 185 and the subtracter are connected to the output 128 of the synchronizing pulse generator 123. by clock pulses due to the repetition rate of the value of the signal reaching the converter 99 (FIG. 9). The time is specified. In the operation of register 178, adder 180 and Shuki 18H! 12) is the output from the output 128 of the synchronous pulse generator 123 to the converter 99. Sets the duration of the addition cycle that reaches the input of and calculates the energy of the filtered signal. synchronized by gate pulses.

The difference signal x"' is filtered in the band from zero to fo, and the adder 187 and the subtracter 18 8 and register 189 (FIG. 12). converter 99 Input 100yo...1002. , that is, the input of adder 187 is filtered. The filtered signal x'2x(-ゝ-...X(') from the output of adder 187 is received. The code word corresponding to the sum of the wave signals is applied to the first input group of subtractor 188. and the second group of inputs of the subtractor 188 defines the operation of the adder 187. receives the difference signal X- which is delayed in register 189 for this purpose. As a result, the subtractor 188 generates at its output a code word corresponding to the signal value X- according to equation (8). I will do it.

Output 102 of converter 99. ...102. Iteration rate F from d/N ratio P The sequence of code words corresponding to 1...P is processed by code converter 103 . ...103. (Figure 9) is given to the input. of the code word of the signal value X- with the repetition rate Fd The sequence is from the output 101 of the converter 99 to the characteristics of the buffer memory 96 (FIG. 9). given to the specified input.

The buffer memory 96 stores input signals, that is, signal values of left and right stereo channels. a sequence of half-sum codewords X+ and the filtered half-difference signal X- to match their ratio to the flow at the input of spectral converter 107. There will be a delay. The end signals X+ and X3T are the adder signals that set the gate signals. applied to the input of the switch 190°190 (Fig. 13) controlled by the cycle. Ru. This gate pulse sets the duration of the process in converter 99 (FIG. 9). and thereby the time interval in which the spectral analysis is performed is equal to the energy bits and It is equal to the time interval during which the signal values are root-mean-squared for the calculation of E'+2 and E'+2.

Therefore, for the first N clock periods, switches 190 and 191 are respectively working compensate for the signal values X and X〒 to be added to the programming memories 192 and 194; Join working memories 193 and 195, respectively, for the next N clock periods. The signal value to be compensated for can be compensated for. During this time, working memory 192 and 19 The contents of 4 will be read out. The data is clocked at the clock rate of Fd. 192.193.194.195, and 2Fd clock It will be read out at the same rate. Switch 196 alternately switches the buffer memory Connect the input of memory 96 to the output of working memory 192.193.194°195 As a result, the sequence of code words for signal values X and X- has a repetition rate of 2F. Ru. Here, N groups of code words of signal value x3 are first generated and signal value ’Th will be followed by N groups of codewords and the same will be repeated. .

Signal value X and Xl? The sequence of code words of ) from the control nolus generator 112 and the number memory 115. is introduced into a transcoder 109 controlled by the signal, where the The number of spectral components is stored. Control pulse generator 112 and number memory 11 5 functions as previously described for monaural signal encoding.

Code converters 1031...103. As in the known technology system, The code words corresponding to the ratios P, . . . P, are re-encoded in floating point notation.

The exponent and mantissa code words from the outputs of the code converters 1031...103 are , the combination of single digital streams with a repetition rate F defined by The inputs of the multiplexer 105 for 1041--10 bills and 1061-1 06. given to.

F　s　=　F　x+　+　F　M2+　F　p　(9) Here, F　Ml is the sign 7<sle repetition rate in the code word X+, and F M2 is the repetition rate in the code word X-. and FP is the pulse repetition rate of codewords P,...P, rate.

During stereo signal encoding and decoding, the demultiplexer 1 of the decoder 30 (FIG. 9) is a sequence of binary codes of an encoded audio broadcast digital signal. of the received cycle, take the repetition rate F5 from it, and A gate signal with a repetition rate Fd/N is extracted from the timing code. Demultiplex The filter 130 also converts the received data stream into a codeword of the encoded filtered signal. the exponent and mantissa sequences of the nodes and the nodes of the left and right stereo channel signals. Separate into h-fusum signals. The exponent and mantissa sequence of the code word is From the output of the multiplexer 130, the ratio P from floating point notation to fixed point notation is determined. , . . . code converters 131, 137, .・・・ ・Given to 137 inputs. Code converter 137. ...by 1371 The generated signals are input to inputs 1401...1401 of the stereo signal restorer 141. Given.

The code converter 131 converts block floating small signals in a manner similar to converters for monaural signals. The spectral components of the signals X+ and x lol from number notation to fixed point notation are Re-encode. The code converter 131 receives the output 155.1 of the control pulse generator 152. 56.1.57.158 and controlled by signals arriving from number memory 153. The number of spectral components of the critical acoustic band is then stored. Code converter 13 The spectral components of the code word from 1 are introduced into a buffer memory 132 and stored therein. and is provided to the inverse spectral transformation unit 133. code converter 131, buffer family memory 131, inverse spectral transformation unit 133, number memory 153, and The function of the control pulse generator 152 is similar to that of a similar unit in a decoder for mono signals. It is similar to knitting.

The sign value of the signal X from the inverse spectral transformation unit 133 and the value of To separate the codes into their delay and signal value code words X, and furnace: is introduced into buffer memory 134. Therefore, the buffer memory 134 The opposite is true when compared with the buffer memory I796 (Fig. 349) in the signal encoder. This process will be executed. The sequence of signal value code words X+ with repetition rate F6 is: It is applied to the input of digital filter unit 142 (FIG. 9). This digi The tall filter unit 142 receives f from direct current. Another one with a passband up to Digital filter unit 9 having auxiliary (m+1) digital filters of It is different from 7. Filtered signal X from the output of digital filter unit 142 ”:+X”++...X (w+J is the input of the stereo sound restorer 141 1451...145□1 is given.

Further, the signal value code word X〒 is recovered from the output 144 of the buffer memory 134. is applied to the input of the device 141.

The stereo signal restorer 141 adds left and right signals to the sum of energies of the filtered signals of the left and right channels. Channel signal energy ratio P1...Pyo values are used to adjust left and right stereo. Half-sum filtered signal of O channel signal X"+ *X"+ *... Left and right stereo channel signals from X37 and low-pass filtered difference signal x3'2 restore. f from DC. The left stereo channel signal is filtered in the band up to , is a component of the following equation.

X'7 = x3 + x te (10) Also, the right stereo channel is as follows.

X, =X, -X- (11) The remainder of the filtered signal 1 is restored according to the following relationship:

X'2 = x (2P, (i = 1.2.-, m) (12) x electric = x cheap ( 1-PI > = x”: -xLP (13) Total recovered left channel signal teeth, The total recovered right channel signal is In the stereo signal restorer 141, the signals X'-2 and x (05 code word is applied to the input of adder 212 (FIG. 15), and at the output of the adder, A code word of the signal read value xL:) is generated and applied to the register 213. Ru. The signal X- is also reached at the input of subtractor 214 and at the output of said subtractor , a code word for the signal readout xR is generated and provided to register 215. . The code word for the values X of the filtered signal is input to the first input of multiplier 220 and 2211.

Multiplier 220. The second input of the restorer 141 is the input 140 . and change the sign It receives code words of ratio P from the output of converter 1371 (FIG. 9). left side The code word of the value X(1) of the reconstructed filtered signal of the teleo channel is appears at the output of 0 and advances to the first input of register 2211 and subtractor 2231. It will be done. The second input of the subtracter 223I is the right stereo input in the register 222□. filtered signal X(R) delayed by one clock period of the multiplication code word of the channel receive. Using a similar method, the filtered signal x(H)...x'':'OyoU　X'g ゝ－’! ”, 'Restore ft, 7).Register 213.215.222゜... ・222. is the subtractor 223. ...223. The signal xCT is determined by the operation period of , x(:ゝ, XT...Xl).

Adders 217.219 have inputs 216.2241...224□ and 2 18.225. ...225. The recovered filtered signal x(2 and Performs the addition of R (i=1.2...,i+), thereby restoring it to the output code words for the left and right channel signals are generated and digital-to-analog conversion is performed. 147, 150 (FIG. 9) and low-pass filters 158 and 151. It will be done. The recovered signals of the left and right stereo channels are passed through a low pass filter 148 and 151 output.

Therefore, during the encoding of a stereo signal, the system encodes Outputs a stereo signal represented by a digital stream transmission.

Vs = VMl + V, 2 + VP (16) Here, V Ml is the left and right stereo is the repetition rate of the half-sum encoded signal X+ of the signal of the channel, and is mono equal to the repetition rate of the digital stream at the output of the encoder for audio broadcast signals. stomach. Therefore, VMl = (24KP + NK,) Fd/N (17)■, 42 is DC? Half-division of the filtered left and right stereo channel signals in the band from is the bit rate of the reference encoded signal X-. The above frequency f. Nii Therefore, the energy of the signal X- is zero, and the above number N, = Nfo/(Fd/2 ) is also zero and therefore does not need to be encoded . Therefore, the bit rate of the digital stream is VM2=(22-m)Kp+N, Fd/N [bits/second:l] (18) where m is the number of high frequency critical audio bands, where the ratio P, ...P is calculated. vP in equation (16) is given by the ratio P,...P, is the bit rate of the digital stream of the corresponding encoded signal, which is V, = m (KP = =, -) Fd/N [bits/sec] where, KP, and 1. are the bit capacities of the exponent and mantissa of the code of the ratio P, ...P, , respectively. It is quantity.

Experimental studies of the system of the present invention show that the critical audio band f0 = 6400 The bandwidth f is chosen as follows. , fl... fl. Therefore, 20 In the frequency band corresponding to the group of low-pass filters, the stereo effect is maintained.

Pseudo-stereo is provided in each of the other four critical audio bands.

The human ear is practically insensitive to stereophonic sound in high frequency ranges. Therefore, a pseudo-stereo band with a frequency of about 6400 Hz compensates for stereoscopic perception. is sufficient. In the above, the following encoding parameters were used: K, ,=4. K,,=5. M=4. N, = 412, remaining parameters are model The same was selected as the Noral sound broadcast signal. of the decoded stereo sound broadcast signal The acoustic characteristics will not differ from the original signal. At the output of the system's encoder The bit rate of the digital stream is given by Equations (16), (17), (1g) and 223 bits/sec corresponding to (19), i.e. left and right stereo channels. frame 1 encoder for stereo signals independent of channel code signals. The structure was 1.4 times lower than that of the previous model.

Industrial applicability The system of the present invention is applicable to digital broadcasting, multi-function communications, ground stations, and satellite digital broadcasting. Digital audio broadcast transmission system and digital audio broadcast transmission system on television Digital system for transmitting, recording, storing and reproducing signals in physical systems Intended for use in

gθ　C nE, 4 nE ) Mi)) (q Mi Ku) December 27, 1999 1. Display of incidents PCT/SU8710 OO95 2. Name of the invention Audio broadcasting signal encoding and decoding system 3. Person who makes corrections Relationship to the incident: Patent applicant Address: 8-10-5 Toranomon-chome, Minato-ku, Tokyo 105, Date of amendment order 6. Subject of correction (1) "Inventor's Address" column of the document pursuant to the provisions of Article 184-5, Paragraph 1 of the Patent Law (2) Translation of the description and claims 7. Contents of correction (1) As per attached sheet (2) Translation of the description and claims (no change in content) 8. List of attached documents (1) Amended Article 184 of the Patent Act 5 One document pursuant to the provisions of paragraph 1 (2) Translation of the description and claims: one copy each of the international search report

Claims (1)

[Claims] 1. Connected directly to the low-pass filter (1), with the input of the low-pass filter as the sign input. an analog-to-digital converter (2); a code converter (6) electrically connected to the converter and an analog-to-digital converter The synchronous pin connected to the clock input of (2) and the clock input of code converter (6) a pulse generator (21), a code converter (29), and an electrical connection to the code converter (29). Connected analog-to-digital converter (32), output forming decoder output of the analog-to-digital converter (32); A synchronous pulse generator (44) having an output (48) connected to a clock input. In an audio broadcasting signal encoding/decoding system comprising a decoder with a During encoding and decoding of the audio broadcast signal, the encoder Inputs connected bit by bit to the output of the log-to-digital converter (2) and said synchronization A clock input and a clock input connected to each output (22, 23) of the pulse generator (21) a buffer memory (3) having a timing input and an output of the buffer memory (3); a data input connected to each output (22, 23) of said synchronous pulse generator (21). ) and the clock input of the code converter (6). an audio broadcast signal spectrum conversion unit with outputs connected bit by bit to data inputs; (4) and the output (23, 24, 25) of the synchronous pulse generator (21). a connected clock input and an output connected to a control input of said code converter (6). a control pulse generator (9) having a control pulse generator (9) connected to the output of said control pulse generator (9); control inputs (13, 14, 15), data inputs of the control pulse generator (9) (10, 11) and the output of the synchronizing pulse generator (21) ( 23) a number memory (12) having a clock input connected to the code converter; (6) data inputs connected to outputs (17, 18) of said control pulse generator ( control inputs (19, 20) connected to the outputs of the synchronization pulse generator (21); ) and an output constituting the sign output connected to the outputs (23, 25) of a multiplexer (16) having a power; an input connected to the output of the multiplexer (16) and constituting the decoding input; said code conversion; a data output connected to the input of the generator (29) and said synchronization pulse generator (44); and a clock input connected to the input of said code converter (29). connected bit by bit to the multiplexer (26) and the output of the code converter (29); data input, and the output (48, 46) of said synchronization pulse generator (44) and a buffer having a clock input connected to the output of said demultiplexer (26); a buffer memory (30) and a buffer memory (30) connected bit by bit to the output of the buffer memory (30). data input, the output (48, 46) of the synchronization pulse generator (44) and the a clock input connected to the output of the multiplexer (26) and said analog output an acoustic broadcasting transmitter having an output connected bit by bit to the input of a digital converter (32); the output of the signal spectrum conversion unit (31) and the demultiplexer (26) ( 45, 46, 47) and the clock input of the code converter (29). a control pulse generator (34) having an output (47) connected to the lock input; The outputs (35, 36, 37, 38) of the control pulse generator (34) are control input of the code converter (29), control input of the puffer memory (30), and is connected to the control input of the demultiplexer (26) and transmits the spectrum of the critical acoustic band. The number memory (41) for storing the number of components is connected to the control pulse generator (34). ) a control input connected to the output (42, 43) of said demultiplexer (26) a clock input connected to an output (46) of the control pulse generator (34); an acoustic emitter characterized in that it has an output (39, 40) connected to a data input of the A system that encodes and decodes transmitted signals. 2. an encoder and a decoder, the encoder having an input constituting a code input; The main low-pass filter (88) and the main analog-to-digital converter ( 89) and a main analog-to-digital converter (109) electrically connected to the main analog-to-digital converter (109). Clock of the code converter (109) and the main analog-to-digital converter (89) Synchronous pulse generation connected to the input and clock input of the main code converter (109) The decoder includes a main code converter (131), and a main code converter (131). a main digital-to-analog converter electrically connected to the main code converter (131); (147) and a main low-pass filter having an output connected in series thereto and constituting the decoded output. clock input of the main digital-to-analog converter (147). a synchronous pulse generator (154) having an output connected to a power source; In a transmission code encoding/decoding system, encoding and decoding of stereo audio broadcast signals During encoding, the encoder has a sub-lowband filter whose input constitutes a code sub-input. filter (90) and the output of the synchronous pulse generator (123) connected in series thereto. a secondary analog-to-digital converter (91) having a clock input connected to; Connect each bit to the output of the main and sub analog-to-digital converters (89, 91) data inputs (92, 94) and the output of the synchronization pulse generator (123) ( an arithmetic unit (93) having a clock input connected to the arithmetic unit (93); The data input and the synchronization pulse generator are connected to the output of the unit (93) for each pit. a digital clock input connected to the output (128) of the generator (123); Filter unit (97) and output of the digital filter unit (97) (1001,...,100...,100m+1,...,1002m) 2m groups of data inputs (m=1,...,24) connected to each unit, a group of data inputs connected bit by bit to the output of the unit (93), and said synchronization The clock input connected to the output (128, 129) of the pulse generator (123) Signal converter for signals with information about stereo sound broadcast signals ( 99) and a signal modification for a signal having information about the stereo audio broadcast signal. The data connected to the output (1021,...,102m) of the converter (99) for each bit Connected to the data input and the output (129, 128) of the synchronous pulse generator (123) a sub-code converter (1031, . . . , 103M) having an input clock input; Each pit is connected to the output (113, 114) of the main code converter (109). Data input, output (124, 125, 127) of the synchronous pulse generator (123) , 128, 129) and the output constituting the sign output. a multiplexer (105) having the m sub-code converters (105); 31,..., 103m) are data inputs of the multiplexer (105). 2 groups connected to (1041,..., 104m, 1061,...106m) Further, the encoder has an output (9) of the arithmetic unit (93). 5) a first group of data inputs connected for each pit to the stereo audio broadcast signal; At the output (11) of the signal converter (99) for a signal having information about the bit a second group of data inputs connected to each other, and an output of the synchronization pulse generator (123). buffer memory (96) with a clock input connected to inputs (124, 125); ) and a data input (1) connected to the output of the buffer memory (96) for each pit. 08), connected to each output (124, 125) of the synchronous pulse generator (123). cycle input and clock input, and data of the main code converter (109) Acoustic broadcasting signal spectrum conversion unit with output connected pit by pit to input (107) and the outputs (125, 126, 12) of the synchronous pulse generator (123). 7), the control input (11) of said main code converter (109) 0,111) and the output of the multiplexer (105). a control pulse generator (112) having connected outputs (121, 122); Control inputs (116, 117, 1) connected to the output of the control pulse generator (112) 18), connected to the data input (119, 120) of the control pulse generator (112); connected output, and connected to the output (125) of said synchronous pulse generator (123). a number memory (115) having a decoder clock input; is connected to the output of the multiplexer (105) of the encoder and provides a decoding input. configuring input, an output ( 135, 136), and an input of the synchronization pulse generator (154) and the decoder has a clock input (164) connected to the input of the main transcoder (131) of at the output of the demultiplexer (130) and the main code converter (131) of the decoder. a connected data input, and an output (166, a buffer memory (132) having a clock input connected to the buffer memory (132); The data input and the synchronization connected to the output of the buffer memory (132) for each pit The clock input connected to the output (167, 168) of the pulse generator (154) an audio broadcasting signal spectrum conversion unit ▽ (133) having a clock input connected to the output (164, 165) of the has an output (167) connected to the clock input of the main code converter (131) of the encoder. a control pulse generator (152), the control pulse generator (152) The outputs (155, 156, 157, 158) of the main code converter (1 31), a control input of the buffer memory (132), and a control input of the demultiplexer (132). connected to a control input of a multiplexer (130); a control input connected to the output (159, 160) of the pulse generator (152), said a clock input connected to the output (167) of the synchronous pulse generator (154); and Outputs (161, 16) connected to data inputs of said control pulse generator (152) 2) number memory (15) for storing the number of spectral components of the critical acoustic band with 3) and the output (1381,...,138m) of the demultiplexer (130) , 1391,..., 139m) and a synchronization pulse The output (168) of the generator (154) and the output of the demultiplexer (130) m sub-code converters (137) each having a clock input connected to (163) 1,..., 137m) and the output (168) of the synchronous pulse generator (154) a stereo signal restorer (141) having a clock input connected to said synchronizer; A clock input connected to the output of the pulse generator (154), said stereo signal recovery Each pit is connected to the input (1451,..., 145m+1) of the return device (141). (m+1) outputs, and the m sub-code converters (1371, . . . , 1 Inputs (1401, ..., 140) connected for each pit to each output of m) and a digital filter unit (142) having said inverse spectral transform. Data input connected bit by bit to the output of the unit (133), and synchronization pulses outputs (166, 167) of the generator (154) and the demultiplexer (130); , 168, 163) with a clock input connected to the buffer memory (134). ), and the first output group (143) of the buffer memory (134) is It is connected to the input of the digital filter unit (142), and the buffer memory ( The second output group (144) of 134) is the input of the stereo signal restorer (141). A sub-digital-to-analog converter (1 50) and a sub low pass filter (151), the sub low pass filter (151) The output of the stereo signal restorer (141) constitutes the sub-output of the decoder. The first group output (146) is the data input of the main digital to analog converter (147). the other output group (14) of the stereo signal restorer (141). 9) is connected to the data input of the auxiliary digital-to-analog converter (150); The clock input of the sub-digital-to-analog converter (150) is connected to the synchronization pulse generator. an acoustic broadcast signal connected to an output (168) of a generator (154); Encoding/decoding system.