NL8720747A - SYSTEM FOR CODING AND DECODING SOUND PROGRAM SIGNALS. - Google Patents

Description

87 2 0 7 4 7.. -iV

N.O. 35901

System for encoding and decoding sound program signals. ^

Applicants cite as inventors: 1. MIKHAIL UROVICH BANK, 2. ALEXEI STEPANOVICH GRUDININ, 3. JURY ALEXEEVICH KOVALGIN, 4. SERGEI VASILIEVICH K0Z0D0I, 5. VIKTOR MIKHAILOVICH KOLESNIKOV, 6. VALENTIN A VLOVIMILEXNOVILLEX ODANDILILEXNOVILLEX 7. SEMENOVICH GORODNIKOV.

Field of the invention

This invention relates to information transfer technology and more particularly to devices for encoding and decoding audio broadcast signals.

5 State of the art

The most accepted are sound program signal encoders and decoders, which use pulse compression modulation with direct compression expansion (G. Bellamy "Digital telephony". -Moscow,

Radio i Svyaz, 1986, p. 116. In Russian). Such devices are a component part of the equipment assembly intended for transmission of a broadcast program via a satellite communication channel, and also of the equipment assembly for determining terrestrial digital channels for transmission of a sound program. The system is provided with an encoding and a decoding device. The encoder includes a series-connected low-pass filter, a compressor and an analog-to-digital converter, in which the converter output constitutes the encoding output. The decoder is provided with a series-connected digital-analog converter, an expander and a low-pass filter, in which the input to the digital -20 analog converter forms the decoder input. The use of a compressor and an expander allows the quantization step to be increased at higher input signal levels, thereby maintaining a signal-to-noise ratio during quantification, during which the listener is practically oblivious to noise.

The above system employs a 10-bit analog-to-digital converter to form high-quality channels, where the signal compression expansion is accomplished by analog devices and signal digitization is performed at a 32 KHz frequency 8720 747 ο * 2 tie. Consequently, the digital flow rate V at the encoding output is V = 10 x 32 = 320 kilobits per second.

Known in the art are devices for encoding and decoding sound broadcast signals (AN Golubev et al.s "Equipment for 5 digital transmission of sound broadcast signals". - Elektrosvyaz, 1980, No. 7, p. 6. - In the Russian) which use direct compression expansion pulse code modulation which differ from the above in that the compander used is digital. The compressed signal in these systems is sampled and encoded in a 10 12-bit linear code, so the sampling frequency is 32 KHz, so the bit rate on the encoding output is V = 12 x 32 = 384 kilobits per second, ie 20¾ higher than in the above system. This higher bit rate provides higher reliability of sound reproduction, as confirmed by expert testing. These systems known in the art provide an almost natural sound reproduction, and therefore the signal encoding by pulse code modulation with direct compression expansion uses sample code words of 12 bit length. This capacity is typical for systems known in the art.

Adaptive pulse code modulation allows the application of a lower 20 bit rate in individual sound transmission channels, compared to that of pulse code modulation with direct compression expansion.

Encoding and decoding systems for sound signal programs are known in the art (MV Gitlits, SV Chetkin "The use of adaptive differential pulse-code modulation for analog-to-digital conversion of sound broadcast signals" - Elektrosvyaz, 1982, no. 1, p. 58. - In Russian), wherein an encoder provides signal digitization and a decoder performs the reverse conversion. The encoder unit is a channel low-pass filter, the output of which is connected to a signal level control unit, the output of which is transferred to the non-inverting input of an active amplifier operating in the differential mode and a pulse amplitude modulator. drives. The output of the pulse amplitude demodulator is connected to the input of an analog-digital converter, the output of which forms the encoding output. The system is further provided with a signal prediction and control circuit. The digital signal from the encoding output is transferred to the input of the signal prediction unit, in which the signal is converted into an analog signal by a digital-analog converter and then averaged into an interpolator.

40 The predict signal produced in this way is applied to the input 0720747? 3 digesting input of the difference amplifier so that a signal proportional to the difference between the input signal of the amplifier and the predict signal at the amplifier output is produced. This difference signal is transferred by the pulse amplitude modulator to an analog-to-digital converter for level quantification and conversion into a binary code. The control circuit also includes a digital analog converter, the output signal of which is rectified, integrated and applied to the correct input of the encoder signal level control unit for controlling the encoder transfer factor. In the decoder, the binary code is subjected to logic conversion into the logic unit connected in series with a digital analog converter, integrator, low pass fliter and signal level controller. The control circuit for the signal level control unit includes a series-connected digital-to-analog converter, a rectifier and an integrator whose output is connected to the correct input of the control unit. At low difference signal levels, the gain of the signal level controller in the decoder is maximum and that of the signal level controller in the encoder is minimal, thus ensuring a higher accuracy of difference signal quantification than without adaptation. At maximum levels of the difference signal, the gain of the signal control unit in the decoder is minimal, while that of the signal level controller in the encoder is maximum.

This system allows sound program transmission with a 15 kHz bandwidth at a bit rate of 256 kilobits per second, which is considerably lower than in pulse code modulation with direct compression expansion equipment. Sound quality tests by experts have shown that with adaptive differential pulse code-30 modulation, the detectability of distortions does not exceed 10¾ to 15¾ for broadcasting, entertainment music, recitation signals and slightly higher, 25¾ to 30¾, for signals reproducing the sounds of a piano forte, violin , symphony and chamber orchestras. Thus, the sound quality provided by encoders with adaptive differential pulse code modulation operating at a bit rate of 256 kilobits per second is lower compared to encoders with pulse code modulation and direct compression expansion, with distortions undetectable by the listener . Accordingly, codecs with adaptive differential pulse code modulation 40 are only used for speech signal compression, with the requirements for 8720747; 4 sound reproduction quality is less stringent than for sound programs.

Known in the art is a system for sound program signals that encode and decode with a near-block floating-point (almost direct-5 compression expansion) (CR Caine, AK English, JM 0'Clearey. "NICAM = III: near - instantaneously companded digital transmission system for high-quality sound programs. "- Radio and Electronic Engineering, 1980, vol. 50, no. 10, biz. 520-529). In this system, the encoder is provided with a series-connected low-pass filter, the input of which is the encoder input, an analog-to-digital converter and a code converter, the output of which is the encoder output and also a sync pulse generator whose output connected to the sync inputs of the analog-to-digital converter and code converter. The analog-to-digital converter provides digitization of the analog signal by pulse code modulation, at a sampling frequency equal to twice the cut-off frequency of the low-pass filter according to current practice and consisting of 32 kHz.

The sample coding capacity in different system versions varies from 14 to 16, depending on the dynamic region 20 of signal display. The code converter performs a conversion of the 16-bit code into an at-block floating-point code, in which the mantissa is encoded into a 10-bit word including the sign bit and the power is encoded into a 3- bit word. The length of a code block with a sub-block floating point is thirty-two samples, the energy is defined by the highest (in absolute value) sample in the block and used for recoding the samples of this block.

The decoder of the known system is provided with a series-connected code converter, the input of which constitutes the decoder input 30, a digital-analog converter and a low-pass filter, the output of which is the decoder output. The decoder also includes a sync pulse generator, the input of which is connected to the input of the code converter and the output of which is connected to the sync inputs of the digital-analog converter and code converter.

The code converter converts the code with at-block floating point into 16-bit sample code words which are transferred to the digital-analog converter in a parallel code. The stored audio program signal samples are again fed to the low-pass filter for time smoothing.

40 The bit rate at the output of the encoder with at-block 87ZO 747Γ 5 floating point for an individual sound program channel is 323 kilobits per second, ie 20¾ lower than that of a pulse code modulation with a direct compression expansion encoder, with sound quality of the recovered signal no worse than that of the output of a 12-bit decoder in pulse code modulation with direct compression expansion transfer systems. This is accomplished due to the fact that at-block floating-point encoding takes into account the effects of quantization noise masking during the interval at which a block is encoded with a fixed value of power.

At the same time, the bit rate on the code output remains high from the viewpoint of effective application of the digital transfer channel, i.e., the transfer of such a digital signal requires the use of a high-capacity transfer channel.

Summary of the invention

The present invention is to provide a system for the encoding and decoding of sound program signals, the encoder and decoder arrangement allowing a lower bit rate in an individual sound program channel while maintaining a high quality signal reproduction during the decoding by introducing a sound program signal frequency band coding into a spectral region, this coding taking into account the effects of masking in frequency bands critical to human hearing.

This object is achieved by a system for the coding and decoding of sound program signals with an encoder provided with a series-connected low-pass filter, the input of which forms the coding input and an analog-to-digital converter, an analog-to-digital converter electrically connected code converter, a synchronization 30 pulse generator, the output of which is connected to the correct clock inputs of the analog-digital converter and of the code converter and a decoder with a code converter and a series-connected digital analogue converter electrically connected to the code converter and low-pass filter, the output of which constitutes the decoding output, which also comprises a synchronization pulse generator, an output of which is connected to the clock input of the digital-analog converter according to the invention; during the encoding and decoding of mono sound program signals, the encoder further includes a buffer memory unit having inputs bit-connected to 40 appropriate outputs of the analog-digital converter and timing and cycle 8720747 6-clock inputs which are connected to correct outputs of the synchronization pulse generator, an audio signal converter with data inputs connected to the outputs of the buffer memory and time and 5 cycle clock inputs connected to the correct outputs of the synchronization pulse generator and the bit to the data inputs of the code converter a connected signal generator converter outputs, a control pulse generator connected with the clock inputs to the correct outputs of the synchronization pulse generator and the correct outputs being connected to the control inputs of the code converter, a memory unit for storing numbers of spectral components of critical audio frequency band n with control inputs connected to correct outputs of the control pulse generator and with outputs connected to data inputs of the control pulse generator and with the clock input connected to the correct output of the synchronization pulse generator, one with data-in-15 outputs on the outputs of multiplexer connected to the code converter and clock inputs connected to the correct outputs of the synchronization pulse generator and wherein the output forms the encoding output, the decoder further comprising a demultiplexer, the input of which is the encoding input and is connected to the multiplexer output, with demul-tiplexer data outputs connected to the correct inputs of the code converter and a clock output connected to the correct inputs of the synchronization pulse generator and of the code converter, a buffer memory with at-bit connected to the correct outputs of the code converter and to the correct outputs of the synchronization pulse generator and of the demu Tip-connected clock inputs, a reverse-spectral converter for restoring the sound program signals with data inputs connected to the correct outputs of the buffer memory at the bit and clock inputs connected to the correct outputs of the synchronization pulse generator and at the correct bit 30 inputs of the digital-analog converter connected outputs, a control pulse generator with clock inputs connected to the correct outputs of the demultiplexer and of the synchronization pulse generator and the correct output being connected to the clock input of the code converter, in which the outputs of the control pulse generator are respectively are connected to the control inputs of the code converter, the buffer memory and the demultiplexer, a memory unit for storing the numbers of spectral components of critical audio frequency bands with control inputs connected to the correct outputs of the control pulse generator and to a correct output of the the plywood connected clock input and output connected to data inputs of the control pulse generator 8720747? 4 7 gen.

This is also achieved by the system for encoding and decoding sound program signals, comprising an encoder with a series-connected main low-pass filter, the input of which forms the 5 encoder input and a main-analog-digital converter, one on the main-analog -digital converter electrically connected master code converter, a synchronization pulse generator connected to the clock inputs of the master-analog-digital converter and of the master code converter and a decoder with a master code converter and connected in series to the master digital analog converter electrically connected to the master code converter and master low-pass filter, the output of which constitutes the decoding output, further comprising a synchronizing pulse generator, an output of which is connected to the clock input of the main digital-analog converter according to the invention for 15 the encoding and decoding of stereo sound program signals using the encoder further comprising a series-connected supplementary low-pass filter, the input of which forms the supplementary input of the encoder and a supplementary analog-to-digital converter whose clock input is connected to the correct output 20 of the synchronization pulse generator, one with the data inputs, respectively bit-connected arithmetic unit connected to the outputs of the main and auxiliary analog-to-digital converters and a clock input connected to the correct output of the synchronization pulse generator, a digital filter unit having at-bit connected to the correct outputs of the 25 arithmetic unit connected data inputs and a clock input connected to a correct output of a synchronization pulse generator, a signal processor for signals carrying information about the stereo sound program signals with 2m data input groups, m = 1, 24 connected at bit to the correct outputs the digital filter-30 unit and a group at-bit on you nth outputs of the arithmetic unit connected data inputs and clock inputs connected to correct outputs of the synchronization pulse generator, m additional code converters with at-bit data inputs connected to m outputs of the signal processor for signals carrying information on the stereo-35 sound program signals and m clock inputs connected to correct outputs of the synchronization pulse generator, a multiplexer connected to data outputs at the bit of the master code converter outputs and clock inputs connected to correct outputs of the synchronization pulse generator, and an output constituting the encoding output. m 40 Supplemental Code Converters are provided with two groups on correct date 8720747? -t 8 ta inputs of the multiplexer connected outputs, a buffer memory with a group of data connected at a bit connected to a correct output of the arithmetic unit and a second group of inputs connected to a correct output of the signal processor for a second group of inputs signals carrying information on the stereo sound program signal and clock inputs connected to the appropriate outputs of the synchronization pulse generator, a sound program signal spectral converter having data inputs connected to the outputs of the buffer memory at bit and connected to correct outputs of the synchronization pulse generator time clock inputs and 10 inputs connected to the data inputs of the master code converter, a control pulse generator with clock inputs connected to the correct outputs of the synchronization pulse generator and outputs connected to control inputs of the master code converter and the multiplexer, respectively, a memory unit for storing the numbers of spectra-15 l e-components of critical audio frequency bands with control inputs connected to correct outputs of the control pulse generator and outputs connected to data inputs of the control pulse generator and with the clock input connected to the correct output of the synchronization pulse generator, the system decoder further provided with a demultiplexer, the input of which is the decoder input and is connected to the output of the encoder multiplexer and the outputs of which are connected to correct data inputs of the master code converter of the decoder and a clock output of which is connected correct inputs of the synchronizer pulse generator of the decoder and of the master code converter of the decoder, a buffer memory with at-bit data inputs connected to the correct outputs of the master code converter and clock inputs connected to the correct outputs of the synchronizer pulse generator, a reverse spectral conversion unit for sound program signals with at-bit data inputs connected to 30 correct outputs of a buffer memory and clock inputs connected to correct outputs of the synchronization pulse generator, a control pulse generator with clock inputs connected to correct outputs of the multiplexer and of the synchronization pulse generator, of which the correct output is connected to the clock input of the decoder master code converter, the control pulse generator outputs being connected to the control inputs of the decoder master code converter, a buffer memory and a demultiplexer, a memory unit that stores the numbers of spectral stores components of critical audio frequency bands with inputs connected to appropriate outputs of the control pulse generator 40 and to the appropriate output of 8720747.

9 clock input connected to the synchronization pulse generator and outputs connected to the data inputs of the control pulse generator, m additional code converters each having two data inputs connected to appropriate demultiplexer outputs and to the inputs of the synchronization pulse generator, respectively, and clock inputs connected to the demultiplexer, a stereo signal regeneration unit connected to the clock input to the correct output of the synchronization pulse generator, a digital filter unit with a clock input connected to the correct output of the synchronization pulse generator and with its (m +1) 10 outputs and also the outputs of each of the m supplementary code converters at bit connected to correct outputs of the stereo signal regeneration unit, another buffer memory with at bit at the outputs of the reverse spectral converter for sound program signals connected data inputs and respectively to the outputs of the 15 synchronis pulse generator and the demultiplexer connected clock inputs, with a group of other buffer memory outputs bit-connected to correct outputs of the digital filter unit and another group of outputs connected to correct inputs of the stereo signal regeneration unit and a bit series-connected digital-20 analog converter and supplementary low-pass filter, the output of which forms the supplementary output of the decoder, with a group of outputs of the stereo signal regeneration unit bit-connected to the data inputs of the main digital analog converter and its other group of outputs are connected bit by bit to the data inputs of the additional digital analog converter and with the clock input connected to the appropriate output of the synchronization pulse generator.

This invention allows for a twice lower bit rate of high quality mono sound program signals, compared to the currently used pulse code modulation with near-direct compression-30 expansion, while reducing the bit rate for stereo digital transmissions by a factor of 1.4 compared to that of the transmission technique, in which the left and right stereo channels are encoded and transmitted independently. Application of the present invention allows the transmission of twelve high quality digital mono or eight stereo sound programs via a basic standard digital channel at 2048 kilobits per second, instead of the currently transmitted six mono programs . Of particular interest is this result for satellite broadcast systems in which the cost of a transmission channel is very high. Furthermore, the application of this invention in sound program transmissions through radio 8720747 ".

s 10 channels allow significant savings in the required transmission bandwidth.

Brief description of the drawings

The invention is described in more detail below with proper reference to embodiments thereof and accompanying drawings.

Fig. 1 shows the schematic diagram of the encoder and decoder for mono sound program signals according to the invention;

Fig. 2 shows the schematic diagram of the code converter in the coder for mono sound program signals according to the invention;

Fig. 3 shows the schematic diagram of the control pulse generator in the encoder of mono sound program signals according to the invention; FIG. 4 shows the schematic diagram of the memory unit for storing spectral component numbers of critical audio frequency bands in the mono sound program signal encoder according to the invention;

Fig. 5 shows the circuit diagram of the synchronization pulse generator in the encoder for mono sound program signals according to the invention;

Fig. 6 shows the schematic diagram of the code converter in the decoder! device for mono sound program signals according to the invention; FIG. 7 shows the schematic diagram of the synchronization pulse generator in the decoder for mono sound program signals according to the invention;

Fig. 8 shows schedules illustrating the operation of the encoding and decoding apparatus for mono sound program signals 30 according to the invention;

Fig. 9 shows the principle diagram of the encoder and decoder for stereo sound program signals according to the invention;

Fig. 10 shows the principle diagram of the arithmetic unit in the encoder for stereo sound program signals according to the invention;

Fig. 11 shows the circuit diagram of the digital filter unit in the encoder for stereo sound program signals according to the invention;

Fig. 12 shows the schematic diagram of the signal processor for 40 signals carrying information about the stereo signal in the encoder for stereo sound program signals according to the invention;

Fig. 13 shows the circuit diagram of the buffer memory in the encoder for stereo sound program signals according to the invention; FIG. 14 shows the circuit diagram of the buffer memory in the stereo sound program signal decoder and according to the invention;

Fig. 15 shows the circuit diagram of the stereo signal regeneration unit in the stereo sound program signal decoder according to the invention;

Fig. 16 depicts schedules illustrating the operation of the digital filter unit in the stereo sound program signal encoder and according to the invention.

PREFERRED EMBODIMENTS The system for encoding and decoding sound program signals and according to the invention is provided with an encoding and decoding device.

The encoder for mono sound program signals is provided with a series-connected low-pass fliter 1 (fig. 1), the input of which forms the encoder input and an analog-to-digital converter 2, the outputs of which are connected at-bit to correct inputs of buffer memory 3 The outputs of buffer memory 3 drive the data inputs of spectral converter 4 for sound program signals, the outputs of which are connected at bit to the data inputs 5 of code-25 converter 6. Control inputs 7, 8 of code converter 6 are connected to appropriate inputs of control pulse generator 9. Inputs 9, 10 of generator 9 are driven by signals from the outputs of memory unit 12 for the storage of spectral component number1 and of critical audio frequency bands, whose control units 13, 14 , 15 are connected to correct outputs of generator 9.

The encoder is also provided with multiplexer 16, the data inputs of which are connected to outputs 17, 18 of code converter 6. Control inputs 19, 20 of multiplexer 16 are driven by the correct outputs of generator 9. Furthermore, the encoder is provided for of synchronization pulse generator 21, whose output 22 is connected to the clock inputs of analog-digital converter 2, of buffer memory 3, of spectral converter 4, of converter 6 and of multiplexer 16. Output 23 of generator 21 is respectively connected to the clock inputs of buffer memory 3 , of spectral converter 40, of generator 9, of number memory 12 and of multiplexer 16.

8720747? 12

Output 24 of generator 21 drives the correct clock input of generator 9, while output 25 is connected to correct inputs of generator 9 and multiplexer 16, the output of which is the encoding output.

5 The decoder for mono sound program signals is provided with demultiplexer 26, the input of which is the decoder input and is connected to the output of multiplexer 16. Outputs 27, 28 of demultiplexer 26 are connected to the data inputs of code converter 29. The The decoder further comprises a buffer memory 30 connected in series 10, the data inputs of which are connected bit by bit to the outputs of converter 30, reverse spectral converter 31 for sound program signals, digital-analog converter 32 and low-pass filter 33, the output of which the decoding output. Furthermore, the decoder is provided with control pulse generator 34, 15 whose outputs 35, 36, 37, 38 drive the control inputs of converter 29. In addition, output 38 is connected to the control input of buffer memory 30 and outputs 35, 36 drive correct inputs. to the multiplexer 26. The control units of generator 34 are connected to outputs 39, 40 of the number memory unit 41 for storing spectral component numbers of critical audio frequency bands, the control inputs of which are connected to outputs 42, 43 from generator 34.

The decoder further includes sync pulse generator 44, the input of which is connected to output 45 of multiplexer 26 and also to correct inputs of code converter 29 and generator 34. The output of demultiplexer 26 is connected to correct inputs of generator 34 , from number memory unit 41, from buffer memory 30 and from reverse spectral converter 31. Output 47 of generator 44 is connected to clock inputs of converter 29 and of generator 34. Output 48 of generator 44 is connected to clock inputs of buffer memory 30, respectively. of reverse spectral converter 31 and of digital-analog converter 32.

Low-pass filter 1 can be implemented with the circuit art known in the art (MU Bank, 0.A. Klimova. "Low-pass filter of 35 digital receiver", Moscow, 1984, Tekhnika sredstv svyazi, TRPA series, edition 3, part V, p. 90. - In Russian). Analog-digital converter 2 can be set up with the commercially available A2884 integrated circuit marketed by Motorola. Buffer memory 3 can be implemented with the circuit diagram 40 known in the art (B.F. Visotsky "Digital filters and signal processing devices designed 8720747 13 with integrated circuits", Moscow, Radio i Svyaz, 1984, biz. 56. - In Russian). Commercially available integrated circuits, for example the AM29540 Fourier transform processor from Advanced Micro Devices, can be used as a spectral converter 4.

5 The schematic diagram of code converter 6 is shown in fig. 2. Converter 6 is provided with maximum component power detector 49 and buffer memory 50, the inputs of which are connected data-inputs 5 of code converter 6. The control input of detector 49 is the control input 7 of code converter 6 and is connected to the correct output of control pulse generator 9 (fig. 1), the clock input of detector 49 is connected to output 22 of synchronization pulse generator 21 (fig. 1). The outputs of detector 49 (fig. 2) are connected bit by bit to correct inputs of the exponent code register 51. The control inputs of register 51 form the control inputs 7 and 8 of code converter 156 and are connected to correct outputs of the control pulse generator 9 (Fig. 1); the clock input of register 51 (fig. 2) is connected to output 22 of synchronization pulse generator 21. The outputs of register 51 (fig. 2) are outputs 17 of code converter 6 and are connected to correct data inputs of multiplexer 16 (fig. 1) ) and also to the correct group of data inputs of floating-point encoder 52 (FIG. 2), the outputs of which form the outputs of code converter 6 and are connected to correct data inputs of multiplexer 16 (FIG.

1). The other group of data inputs from encoder 52 is connected bit by bit to the outputs of buffer memory 50, the clock inputs of encoder 51 and of buffer memory 50 being connected to output 22 of synchronization pulse generator 21 (FIG. 1).

The basic diagram of control pulse generator 9 is shown in Fig. 3. Control pulse generator 9 is provided with pulse counter 53, the outputs of which are connected by-bit to a group of inputs of comparator 54, the other group of which inputs are inputs. 10 forms generator 9 and is connected to the correct outputs of memory 12 (fig. 1). The output of comparator 53 is one of the outputs of generator 9 and is connected to control input 13 (fig. 1) of memory unit 12. Generator 9 is further provided with series-connected pulse counters 55, 56 with series in between. connected inputs of counters 53, 55 and wherein the input of counter 56 constitutes the clock inputs of generator 9 and is connected to outputs 23, 24 and 25 of synchronizing pulse generator 21, respectively (Fig. 1). The output of counter 55 (fig.

4) forms the output of generator 9 and is connected to input 15 40 of memory unit 12 (fig. 1). The outputs of counter 56 (fig. 3) 87207477 i $ 14 are connected bit by bit to a group of inputs of comparator 57, the other group of which are inputs-11 of generator 9 and are connected to correct outputs of memory unit 12 (fig. 1). The output of comparator 57 (FIG. 3) drives control input 14 of memory unit 12 (FIG. 1) and also an input of pulse counter 58 (FIG.

3), the other input of which is the clock input of generator 9 and is driven from output 25 of synchronizing pulse generator 21 (FIG.

1). The output of counter 58 is connected to input 59 of flip-flop 60, input 61 of which is connected to the output of comparator 57 and whose output is one of the outputs of generator 9 and is connected to control unit 19 of multiplexer 16 ( Fig. 1), and also at the input of inverter 62 (Fig. 3). The output of inverter 62 forms the output of generator 9 and is connected to control input 20 of multiplexer 16 (FIG. 1). Generator 9 (fig. 3) is also provided with pulse counter 63, one input of which is connected to the output of comparator 54 and the other input is one of the clock inputs of generator 9 and is connected to output 24 of synchronization pulse generator 21 (fig. 1). The output of counter 63 (fig.

3) is connected to an input of flip-flop 64, the other 20 input of which is connected to the output of comparator 54 and the output of which forms the output of generator 9 and is connected to control unit 7 of code converter 6 (fig. 1) . The output of counter 63 is also connected to the inputs of a series-connected pulse counter 65 and flip-flop 66, the other input of counter 65 being one of the 25 clock inputs of generator 9 and connected to output 24 of synchronization pulse generator 21 (FIG. 1) and wherein the output of flip-flop 66 (FIG. 3) forms the output of generator 9 and is connected to control input 8 of code converter 6 (FIG. 1).

The basic diagram of memory unit 12 for storing the 30 numbers of spectral components of critical audio frequency bands is shown in Fig. 4. Memory unit 12 comprises pulse counter 67, an input of which forms input 13 of memory unit 12 and is connected to a correct output of generator 9 and another output of which is the clock input of memory unit 12 and is connected to output 23 of synchronizing pulse generator 21 (fig. 1). The outputs of counter 67 (FIG. 4) are connected bit by bit to the inputs of dead memory 68 whose outputs form the outputs of memory unit 12 and are connected to inputs 10 of generator 9 (FIG. 1). Memory unit 12 (Fig. 4) also includes pulse 40 counter 69, whose inputs control inputs 14 and 15 form memory 8720747 '15 unit 12 and are connected to proper outputs of generator 9 (fi, <1). and the outputs of which are connected at bit to the inputs of dead memory 70, the outputs of which form the outputs of memory unit 12 and are connected to inputs 11 of generator 9 (Fig. 1).

Counters 67 and 69 can be set up with commercially available SN7400 series integrated circuits; dead memories 68 and 70 can be set up with MM6300 series integrated circuits.

Synchronization pulse generator 21 (Fig. 5) is provided with crystal-controlled oscillator 71, the output of which drives frequency dividers 72, 73, 74, 75, the outputs of which form outputs 22, 23, 24, 25 of generator 21, respectively. Crystal-controlled oscillator 71 can be performed with the circuit art known in the art (L.M.

15 Gol'denberg, "Digital devices designed with integrated circuits in communications technology". - Moscow, Svyaz, 1979, biz. 76. - In Russian). Frequency devices 72, 73, 74, 75 can be equipped with commercially available SN7400 series counters. Multiplexer 16 and demultiplexer 26 can be implemented with a circuit known in the art (L.S. Levin, M.A. Plotkin "Digital information transmission systems". - Moscow, Radio i Svyaz, 1982, biz. 87. - In Russian).

Code converter 29 of the decoder is implemented as shown by the principle diagram in Fig. 6 and is provided with a code power register 76, a first input of which forms the data input of a code converter 29 and is connected to output 27 of demultiplexer 26 ( Fig. 1), a second input of which forms the control input of code converter 29 (Fig. 6) and is connected to output 37 of control pulse generator 34 (Fig. 1), and of which a third input is connected to output 45 of demultiplexer 26 (Fig. 1). The outputs of register 76 (Fig. 6) are connected bit by bit to the inputs of comparator 77, the output of which is connected to input 78 of register 79 and to one of the inputs of pulse counter 80. The output of pulse counter 80 drives the inputs of comparator 77 at bit. The other two inputs of counter 80 and of register 79 are connected to a common point and serve as the clock input of code converter 29, which is connected to output 47 of synchronization pulse generator 44 (Fig. 1).

Code converter 29 (Fig. 6) is further provided with mantissa-codere-40 yesterday 81, an input of which forms the data input of code converter 29 8720747 ^ 16 and is connected to output 28 of demultiplexer 26 (Fig. 1), of which an the other input is connected to output 45 of demultiplexer 26 and a third input of which is the control unit of code converter 29 and is connected to output 36 of control pulse generator 34 (fig.

5 1). A respective input of register 79 is connected to a respective input of counter 80 so that it serves as the control input of code converter 29 connected to output 35 of the control pulse generator 34 (fig. 1). Output group 82 of register 81 (fig. 6) bit is connected to the inputs of register 79 and output 83 is connected to one of the inputs of register 84, the other input of which is the control input of code converter 29 and is connected to output 38 (fig. 1) from control pulse generator 34. The outputs of register 79 (Fig. 6) are connected bit by bit to the group of correct inputs of register 84, the outputs of which are the outputs of code converter 29 and bit are connected to the data inputs of buffer memories 30 (FIG. 1).

Registers 76, 79, 81, 84 (Fig. 6), comparator 77 and counter 80 can be performed with commercially available SN7400 series integrated circuits, the structure of buffer memory 30 is similar to that of buffer memory 3. Inverted spectral conversion unit 31 can be implemented with the same integrated circuit as converter 4 (fig. 1). Digital-to-analog converter 32 can be set up with Motorola's A2854 integrated circuit. The low-pass filter 33 is similar in circuit arrangement to that of the low-pass filter 1 of the encoder. Control pulse generator 34 is constructed similar to generator 9, and memory units 41 and 12 are identical in design.

The schematic diagram of synchronization pulse generator 44 is shown in FIG. 7 and is provided with frequency multiplier 85 30, the input of which forms the input of generator 44 and is connected to output 45 (FIG. 1) of demultiplexer 26 and whose output is connected to the inputs of frequency dividers 86 and 87. The outputs of frequency dividers 86 and 87 form outputs 47 and 48 of generator 44, respectively. Frequency multiplier 85 can be performed with a circuit diagram known in the art (I.Kh. Rizkin "Frequency multipliers and dividers ", Moscow, Svyaz, 1976, p. 124. - In Russian), frequency dividers 86 and 87 can be set up with commercially available counters of the SN7400 series.

Fig. 8 shows the schedules for displaying the operation of the mono encoding and decoding system 8720747? 17 program signals: a) represents codeword sequences-describing spectral components on the output of spectral converter 4 (FIG. 1), wherein tg and ti are the start and end codewords of spectral components of the N-readout respectively sound program masseal sample being studied; b, c, d, e) display signal waveforms at the outputs of the coding control pulse generator 9 (Fig. 1) which are applied to inputs 7, 8 of converter 6 and to inputs 19, 20 of multiplexer 16 wherein 10 t2 and t3 are the times of the start and end of a pulse train, respectively, which controls the method of encoding the spectral components of a sample of a sound program signal; f, g, h, i) represent signal waveforms at outputs 37, 36, 35, 38 (Fig. 1) of the decoder control pulse generator 34, where t4 and t5 are the times of the start and the end of a pulse sequence, which directs the process of decoding a spectral component of a sample of N readings from the gel program.

The system for encoding and decoding mono sound program signals according to the invention functions as follows.

The sequence of sound program signal readings is divided into samples of N readings and the spectrum of N components is calculated. The resulting direct spectrum components are divided into twenty-four frequency groups according to twenty-four critical audio frequency bands. The boundaries of these bands are listed in Table 27.1 in the monograph of E. Zveker and R. Feldkeller "The ear as an information receiver" (Moscow, Syyaz, 1971). Each of the twenty-four frequency groups is examined for the absolute value maximum spectral component that is used to set the power in the code with an at-block floating-point, after which the spectral components of this frequency group are encoded with this value of the energy. The number of bits, km of the mantissa code is chosen so that the desired coding error value is assured of the maximum spectral component of the given frequency group. The number of bits in the power code, kp, should cover the entire range of spectral e-component variation, which is equal to sixteen bit, and therefore kp = 4 is chosen.

In any frequency group, the error of encoding all other 40 spectral components with levels below that of the maximum component 87207477 18 may exceed the preset value because they will not be audible due to the effect of masking within critical audio frequency bands. The allowable error of maximum component coding should be at least 30 dB below the level of the coded component 5 to ensure inaudibility of the coding error. To provide a 30 dB encoding, a five bit signal-to-noise ratio of the mantissa codeword is sufficient, i.e. km = 5. Thus, encoding a sample of N readings requires Nkm + 24 kp binary symbols. The sample length, N, is chosen so that the spectral analysis interval T is approximately equal to the interval of hearing inertia, i.e. T = (N / Fd) = 30 ms, where Fd is the discrimination repetition rate. At a discretization repetition rate Fd = 32 kHz, the sample length is N = 1024 and therefore the coding of readings of a sample requires 1024.5 + 24.4 binary symbols. The sampling rate is equal to Fd / N and therefore the bit rate V on the encoding output will be: F 32 V = - (Nkm + 24 kn) = - (1024.5 + 24.4) = 163 kilobit 20 N p 1024 per second (1) ie, twice lower than in a block-by-block floating-point decoder.

To rearrange the initial sequence of readings from the power and mantissa codewords of spectral components, the decoder converts the code by block floating point to a fixed point code and then using of the reverse spectral conversion, the respective sample of N readings of the sound program signal is again stored in the time region. Any of the known orthogonal transformations such as the Fourier transform, discrete cosine transform, Adamer transform, etc. can be used, discrete cosine transform being preferred because it provides the highest quality sound of the stored sound program signals.

The encoder for mono signal and functions as follows.

The analog sound program signal arrives at the input of low-pass filter 1 (Fig. 1), limiting the input signal bandwidth to an upper frequency F = 15 kHz. The signal from the 40 output of low-pass filter 1 is transferred to the input of analog-to-digital converter 2, the signal being sampled at the 8720747.1 19 discrimination frequency Fd = 32 kHz, and the results quantified and encoded in a 16-bit linear code . The code words of analog-frequency converter 2 readings are generated at an Fc clock frequency and transmitted to the input of buffer memory 3, the power of which is 2N 16-bit words, where N is the number of readings in the signal sample used for spectral analysis -star. Buffer memory 3 delays the sequence of codewords for N / F (j seconds) to provide a coupling of the output of the analog-to-digital converter 2 with the input of the spectral converter 4 to which blocks of N codewords are processed. After N code words corresponding to the first N readings of the sound program signal are stored by buffer memory 3, they are serially read and transferred to the input of spectral converter 4, in which the spectrum of the sequence of N readings is calculated.

Thus, during a time interval of ΔΤ = N / F (j, the sound program signal is subjected to real time spectrum analysis.

16-bit code words with spectral components - coefficients with discrete spectral transformation - are generated serially at the output of spectral converter 4. N coefficients with a spectral decomposition are distributed uniformly along the frequent! Axis with a pitch of f = Fd / N corresponding to a signal sample consisting of N signal readings (usually N is chosen as N = 2S, where S is a natural number, S = 1, 2, ..., S, because this is one of the most simple in the application spectrum transformation algorithm 25). The first coefficient corresponds to fo = 0 and the last coefficient corresponds to a frequency of ffj_i = Fd (1-1 / N). Therefore, the spectrum of a sample of the sound program signal composed of N readings is represented by N digits in a 16-bit linear code. The timing of the codewords of these digits on the output of spectral converter 4 is shown in the timetable in Fig. 8a, where a block of a 16-bit codeword is represented as a rectangle.

Code converter 6 (Fig. 1) converts the 16-bit linear code of spectral components into a code with at-block floating-point, ie, at a code with at-block-floating-point applied in pulse code modulation (almost direct compression -expansion). In this invention, the difference is that firstly a sequence of signal-spectral components is used instead of a sequence of sound program signal samples over time, and secondly, the length of a block encoded with a constant power value ( ie the coefficient-

8720747J

20) and is set by signals arriving at control inputs 7 and 8 of code converter 6 from the outputs of control pulse generator 9. The schedules of these signals are shown in Figures 8b, c, respectively.

5 Code words with spectral components arrive at data inputs 5 of code converter 6 (fig. 1) and at the same time at the inputs of detector 49 (fig. 2) and of buffer memory 50. The latter accumulates code words (its capacity is N) and shifts them upon arrival of the next codeword. Detector 49 compares the codewords and selects the codeword corresponding to the maximum (in absolute value) spectral component to produce the power value equal to the number of most significant zero bits of the codeword and the power codeword. Upon completion of the comparison of the required number of code words, a signal (Fig. 8b) is applied from the output of generator 9 (Fig. 1) to the input of detector 49, which is input 7 of code converter 6 to enable the readout making the generated power codeword. At the same time, this signal enters this power code word into power code register 51 (Fig. 2). After entering all N code words of spectral components of the signal-20 sample into buffer memory 50, a signal comes from the output of generator 9 (Fig. 8b) at control input 8 of code converter 6 to enable the code word of the last one to be written out. Twenty-fourth power of the sample of readings from the output of detector 49 (FIG. 2) in codeword register 51. After the last twenty-fourth power codeword is written into register 51, a positive pulse (FIG. 8c) is applied to control input 8 of code converter 6 and upon arrival at the correct input of register 52, it allows rewriting of the first power codeword from the output of register 51 in encoder 52 to which the floating-point code is applied. This code word from output 17 of code converter 6 arrives at the correct input of multiplexer 16 (Fig. 1). At the same time, the codeword of the first spectral component of the signal sample being discussed is brought to the output of buffer memory 50 and supplied to the input of encoder 52, in which the codeword is shifted by a number of bit positions set by the power code word from the output of register 51 at the input of encoder 52. Thus, tissue code words of spectral components are generated and applied from output 18 of code converter 6 to the input of multiplexer 16 40 (FIG. 1). The encoding of spectral components with a constant 87207477 21 of the power continues until the other input of encoder 52 receives a new power codeword from the output of register 51 thereby causing spectral component codewords to be shifted by a number of positions set by this new power codeword. This sequence of operations continues until all twenty-four power codewords of the subject signal sample are read from register 51. Subsequent samples of N readings are encoded in the same manner.

Multiplexer 16 (Fig. 1) performs the reclassification at the time of the 10 power and mantissa codewords to provide a regular pulse train on its output. The pulse repetition rate at the output of multiplexer 16 is described by the following equation: 15 Fuit = (24kp + Nkm) fd / N (2) where kp is the power bit capacity, km is the mantissa bit capacity and N is the number of readings is in the sample.

The operation of analog-to-digital converter 2, buffer memory 3, 20 spectral converter 4, code converter 6, control pulse generator 9, spectral component arrival memory 12 and multiplexer 16 is time-controlled by synchronization pulse generator 21. Pulses with a repetition rate Fd / N are generated at output 22 of synchronization pulse generator 21, pulses with an Fd repetition rate are generated at its output 23 and pulses with an repetition rate of Ful't appear at its output 25.

Control pulse generator 9 functions as follows. The count inputs of counters 53, 55, 63, 65 form the clock inputs of generator 9 and receive a pulse train with a repetition rate of 16 Fd from output 24 of synchronization pulse generator 21 (Fig. 1), this repetition rate corresponding to the bit rate of code words of spectral components. A train of pulses with a repetition rate Fd / N from output 23 of synchronization pulse generator 21 (Fig. 1) is supplied to the set of inputs of counters 53 and 55 and determines the start of a sample of N readings of the sound program signal used to calculate the spectrum and accordingly set the start of the sequence of spectral components of this sample of readouts. Pulses from output 23 of synchronization pulse generator 21 trigger counters 53 and 55 (FIG. 3). The 40 spectral component number code is generated at the output of 8720747: 22 counter 53 and transferred to a first group of inputs of comparator 54, the second group of inputs of which receives the code number of the last spectral component in this frequency group from the number output memory 12, in which the numbers of spectral components are stored in 5 critical audio frequency bands. When the codes on the first and second groups of inputs of comparator 54 coincide (FIG. 3), this comparator produces a signal that initiates counter 63 and sets flip-flop 64 to a logic unit. Furthermore, the output of comparator 54 is transferred to input 13 10 of number memory 12 (Fig. 1) and allows reading of the code number of the last spectral component of the next frequency group from a correct output of number memory 12. Counter 63 (Fig. 3) counts the required number of pulses arriving at its count input and produces a signal to switch flip-flop from logic unit 15 to logic zero and to set flip-flop 66 to logic unit. Furthermore, the output of counter 63 initiates counter 65, which counts the required number of pulses, as in counter 63, to produce a signal that switches flip-flop 66 from logic unit to logic zero. In this manner, flip-20 flops 64 and 66 produce pulse trains (Fig. 8b, c) at their outputs to control the operation of code converter 6 (Fig. 1).

After counting the required number of pulses, counter 55 (FIG. 3) generates a signal for initiating counter 56, the input of which receives a pulse train at a repetition rate 25 Ful't from input 25 of synchronization pulse generator 21 (FIG. 1).

The code number of the pulse arriving at the input of counter 56 is generated at its output and transferred to comparator 57 for comparison with that of the least significant bit in the power code of this frequency group, which is applied to the second Input of comparator 57 from the output of memory 12 (fig. 1).

The coincidence of these numbers causes comparator 57 (fig.

3) generates a signal to clear counter 58 and set flip-flop 60 to a logic unit. Furthermore, the signal from the output of comparator 57 arrives at input 14 of memory 12 (FIG. 1) 35 and clears the reading of the power code number of the next frequency group from the correct output of memory 12. Counter 58 (FIG. 3) counts down a number of pulses equal to the bit capacity, kp, in the power codeword and generates a signal to initiate flip-flop 60 and switch it from logic-zero. 40 Pulses are generated at the output of flip-flop 60 (fig. 8d) and 8720747.1 23 are transmitted to control input 19 of multiplexer 16 (fig. 1) and to the input of inverter 62 (fig. 3), the output of which is at control input 20 produces pulses supplied from multiplexer 16 (FIG. 1).

Number memory 12, in which the numbers of spectral components of critical audio frequency bands are stored, functions as follows. The count inputs of counters 67 and 69 receive pulses from correct outputs of generator 9 (Fig. 3) and their set inputs receive pulses from output 23 of synchronization pulse generator 21 (Fig. 4) and from the correct output of generator 9 (Fig. 3). 3). These 10 pulses clear counters 67 and 69 (Fig. 4). At the outputs of counter 67, code number address codes of last spectral components of frequency groups are generated to reach dead memory 68, where these code numbers are stored and from which these code numbers are read and transferred to input 10 (Fig. 15 3) from generator 9. Address codes of code numbers corresponding to the least significant bits of power code words of frequency groups are generated at the outputs of counter 69 (FIG. 4). These addresses are used to reach dead memory 70, from the output of which the code numbers are transferred to input 11 20 (fig. 3) of generator 9.

The system decoder functions as follows. The train of at-block floating-point code bits representing spectral components of a sound program signal from the output of multiplexer 16 (Fig. 1) are transferred to the input of demultiplexer 26, in which the input train is separated into a sequence of power code word bits and a sequence of mantissa code word bits. Demultiplexer 26 also senses the pulse repetition rate Fu-jt and transfers trains of this pulse repetition rate to output 45 of demultiplexer 26. Furthermore, demultiplexer 26 extracts the cycle clock signal from the input pulse sequence, applying this signal to the start defining a block of spectral components corresponding to the subsequently transferred sample of N readings of the sound program signal. Cycle clock pulses with a repetition rate of F (y / N appear at output 46 of demultiplexer 26.

Code converter 49 performs code conversion from block-floating-point to 16-bit linear fixed point code words.

Power code bits from output 27 of demultiplexer 26 are allowed in register 76 (Fig. 6) at a repeat rate Ful't reading from output 45 of demultiplexer 26. Upon arrival of a 40 control signal (Fig. 8f) from the output 37 (fig. 1) of generator 34 87 20747? 24, these code bits are transmitted in parallel code from register 76 to the first group of inputs of comparator 77 (Figure 6), the second group of inputs of which receive signals from the outputs of counter 80, whose count input receives pulses with the clock frequency 5 Fits from output 47 (Figure 1) of synchronization pulse generator 44. Comparator 77 (Figure 6) generates a signal to control register 79 and simultaneously resets counter 80.

Mantissa code bits with a clock frequency Ful't from output 28 (fig. 1) of demultiplexer 26 are transferred to the input of 10 km = bit-mantissa code register 81 (fig. 6). On arrival of a control signal (Fig. 8g) from output 36 (Fig. 1) of generator 34, the sign bit is rewritten from register 81 into 16-bit register 84 (Fig. 6) at the sign bit position in a fixed point notation, and the other km-1 bits of the mantissa are transmitted in a parallel code 15 at km positions of least significant bits in 15-bit register 79, in which they are subsequently shifted with a clock frequency Fuit coming from output 47 (Fig. 1) of synchronization pulse generator 44. A signal defining the start of the mantissa bit shift (Fig. 8h) is applied to the control input of register 79 (Fig. 6) 20 from output 35 of generator 34. This signal also brings counter 80 (Fig. 6). ) in progress to count the number of shifts. Upon completion of a preset number of shifts, counter 80 produces a codec combination that coincides with the power code word stored in register 76. This combination arrives at the second input of comparator 77 and generates a command to rewrite the contents of register 79 into bit positions of register 84. At the same time, this command resets counter 80 to zero. In this manner, a fixed-point 16-bit codeword is generated by register 84 and transferred to buffer memory 30 upon arrival of a control signal (FIG. 8i) from output 38 of generator 34 (FIG. 1). Buffer memory 30 delays the arriving sequence of codewords for two periods of Fd / N, i.e., for the duration of 2N codewords.

Buffer memory 30 serves to couple the arrival rate of spectral component codewords from the output of converter 29 35 to the rate of their processing by reverse spectral converter 31, in which the sample of N readings is again stored from its N spectral components . 16-bit codewords of sound program signal readings are transferred in parallel code from the output of reverse spectral converter 31 to digital-40 analog converter 32, in which the quantized readings of the 8720747? 25 loudspeaker signal can be stored again. Digital-to-analog converter 32 is charged by low-pass fliter 33, in which the quantized readings are smoothed, and so the initial analog sound program signal with a bandwidth up to F = 15 kHz is again stored.

Thus, the input signal is output at the output of the system encoder by a bit stream transmitted at a rate defined by equation (1) and the decoder again stores the initial analog signal from this bit stream.

Experimental studies of this system for encoding and decoding sound program signals were performed on a sample of N = 1024, power codeword bit power kp = 4, mantissa codeword bit power km = 5, and a time discrimination rate Fd = 32 kHz.

The bit rate at the encoding output V = 163 kilobits per second, i.e., 15 was twice lower than in the prototype system. Expert sound evaluations showed that the quality of sound program signals after encoding and decoding in the inventive system were not lower compared to the quality of the initial digital signal with readings encoded in a 16-bit linear code.

The encoder for stereo sound program signals includes a main low-pass filter 88 (FIG. 9) and a main analog-digital converter 89 for the left series-connected stereo channel, and a supplemental low-pass filter 90 and an ana lye-digital converter 91 for the right stereo-25 channel connected in series. The outputs of low-pass flashes 88 and 90 form the encoding inputs. The outputs of the analog-to-digital converter 89 are connected at bit to inputs 92 of arithmetic unit 93, whose inputs 94 are at-bit connected to the outputs of analog-digital converter 91. The group of outputs 95 of arithmetic unit 93 is connected at bit to the first group of data inputs of buffer memory 96 and also to the inputs of digital filter unit 97. The group of outputs 98 of arithmetic unit 93 is connected at bit to corresponding inputs of digital filter unit 97 and to the inputs of signal converter 99, in which information about the stereo sound program signal carrying signals are processed. Groups of outputs 100χ, ..., 100m, 100m + i, ..., 1002m, which are connected to correct inputs of signal converter 99, of which a group of outputs 101 is connected to a second group of data inputs of buffer memory 96. The 102 102m group outputs of sig-40 sewing converter 99 is connected to the data inputs of supplemental 8720 747 26 re code converters 103i, ..., 103m, each of those converters having two groups of outputs. The first group of outputs of signal converters 103χ, ..., 103m is connected to inputs 104 ^, ..., 104m of multiplexer 105 and the second group of outputs of signal converters 103i, ..., 103m is connected to inputs 106 ^, ..., 106m from multiplexer 105.

The stereo sound program signal encoder is provided with spectral converter 107, the inputs 108 of which are connected bit by bit to the outputs of buffer memory 96 and whose outputs are connected by bit to the data inputs of main code conversion -ter 109. Control inputs 110 and 111 of master code converter 109 are connected to correct outputs of control pulse generator 112. Outputs 113 and 114 of code converter 109 are connected to correct inputs of multiplexer 105.

The encoder is further provided with number memory 115, in which the numbers of spectral components of critical audio frequency bands are stored and of which inputs 116, 117, 118 and outputs 119, 120 are connected at bit to appropriate outputs and inputs, respectively. of control pulse generator 112, whose outputs 20 121, 122 are connected to correct inputs of multiplexer 105. Furthermore, the encoder for stereo sound program signal is provided with synchronization pulse generator 123, of which output 124 is connected to correct clock inputs of buffer memory 96, of spectral converter 107 , from code converter 109 and from multiplexer 105. Output 125 of generator 123 is connected to correct clock inputs of buffer memory 96, spectral converter 107, control pulse generator 112, memory 115 and multiplexer 105. Output 126 of synchronization pulse generator 123 drives the correct clock input of control pulse generator 112. Synchronization output 127 pulse generator 123 is connected to correct clock inputs of control pulse generator 112 and of multiplexer 105. Output 128 of synchronization pulse generator 123 is connected to correct clock inputs of analog-to-digital converters 98, 91 of arithmetic unit 93, of digital filters unit 97, of signal converter 99, from code converters 103 ^, ..., 103m, from buffer memory 96 and from multiplexer 105. Output 129 of synchronization pulse generator 123 is connected to correct inputs of signal converter 99, of code converters 103 ^, ..., 103m, of buffer memory 96 and from multiplexer 105.

The stereo sound program signal decoder is provided with demultiplexer 130, one input of which is the decoder input, and 8720747 27 a series-connected main code converter 131, buffer memory 132, reverse spectral converter 133 and buffer memory 134. Outputs 135 and 136 of demultiplexer 130 are connected to correct inputs of code converter 131.

5 The decoder is also provided with m additional code converters 137χ, ..., 137m, each with two data inputs. The first data inputs of code converters 137χ, ..., 137m receive signals from outputs 138] _, ..., 138m of demultiplexer 130 and the second data inputs of code converters 137χ, ..., 137m 10 are connected to outputs 139m, ..., 139m from demultiplexer 130. The outputs of code converters 137], ... »137m are connected bit by bit to data inputs 140], ..., 140m from stereo signal regenerator 141. Furthermore, the decoder is provided with digital filter unit 142 in which the data input is connected bit by bit to output group 143 of buffer memory 134, of which output group 144 is connected to correct outputs of stereo signal regenerator 141, whose inputs are 145χ. ... 145m + i are driven from the outputs of digital filter unit 142. The output 146 of stereo signal regenerator 141 is connected to main digital analog converter 147 and series connected main low pass filter 148 and output 149 is connected to supplementai The digital-to-analog converter 150 connected in series with the outputs of the decoding outputs forming low-pass flashes 148 and 151.

The decoder further includes control pulse generator 25 152, number memory 153, in which the numbers of spectral components of critical audio frequency bands are stored, and synchronization pulse generator 154. Outputs 155, 156, 157, 158 of control pulse generator 152 drive proper inputs to from code converter 131 and outputs 155 and 156 are further connected to the inputs of demultiplexer 30 130. Outputs 159 and 160 of control pulse generator 152 are connected to appropriate inputs of number memory 153 whose outputs 161 and 162 become at-bit connected to proper data inputs of control pulse generator 152.

The output 163 of demultiplexer 130 is connected to correct inputs of generator 154, buffer memory 134 and code converters 137χ, ..., 137m. The output 164 of demultiplexer 130 is connected to correct inputs of generator 152, converter 131 and generator 154, the output 165 of which is connected to a correct input of control pulse generator 152. The output 166 of synchronization pulse generator 154 40 is connected to correct clock inputs of buffer memories 132 and 134 8720747 * · · 28 and of reverse spectral converter 133. Output 167 of generator 154 is connected to correct clock inputs of buffer memories 132 and 134 of control pulse generator 152 and of code converter 131. Output 168 of synchronization pulse generator 154 is connected to correct clock sensors of buffer memory 134, of code converters 137χ, ..., 137m, of digital filter unit 142, of stereo signal regenerator 141 and of digital-analog converters 147, 150.

Low-pass flashers 88, 90, 148, 151, analog-digital converters 89 and 91, code converters 103] _, ..., 103m, 109, 131, 137 ^, ..., 10 137m, spectral signal converter 107, control pulse generators 112 and 152, number memories 115 and 153, storing the number of spectral components of critical audio frequency bands, synchronization pulse generators 123 and 154, multiplexer 105, demultiplexer 130, reverse spectral converter 133, and digital analog converters 147 and 15 150 are implemented as corresponding units of the system for the encoding and decoding of mono sound program signals.

The schematic diagram of the arithmetic unit 93 is shown in Fig. 10. The arithmetic unit 93 is provided with adder 169 and subtractor 170, inputs 92 and 94 of arithmetic unit 93 being connected to the inputs of adder 169 and subtractor 170, respectively. wherein the output of adder 169 forms the output 95 of arithmetic unit 93, the output 98 of which is the output of subtractor 170. Adder 169 and subtractor 170 may be performed with a circuit diagram known in the art (U. Titze, K. Shenk 25 "Semiconductor circuitry", a reference book, 1982, p. 334, 335. - In Russian).

The schematic diagram of digital filter unit 97 is shown in fig. 11. This unit is equipped with two groups of digital filters: 171i, ... »171m and 171m + l» ..., 1712m · The inputs of each group of digital filters 171χ, ..., 171m and 171m + i »···» 17l2m are connected together and form the inputs of unit 97. Clock inputs of digital filters 171χ, ... »17l2m are connected to output 128 (fig 9) of generator 123 and the filter outputs form the ΙΟΟχ, ..., 100m and 100m + i »35 ..., 1002m outputs, respectively. Digital filters 171χ, ..., 17l2m can be performed using art-known switching devices (U. Titze, K. Shenk, "Semiconductor circuitry," a reference book, 1982, p. 429. - In Russian).

The principle diagram of signal converter 99 for processing 40 information about the stereo sound program signal carrying processing 8720747.

29 signals are shown in Fig. 12. Signal converter 99 is provided with m channels, each comprising a series-connected adder ter 172, a multiplier 173, an adder 174, a register 175 and a switch 176 whose output 177 is connected to the correct input of adder 174. Each of the m channels also includes register 178 with a data input connected to output 179 of switch 176, one with an input connected to output 179 of switch 176 and a divider 181 whose inputs are connected to the outputs of register 178 and adder 180 respectively. Furthermore, each channel is provided with a series-connected subtractor 182, a multiplier 183, an adder 184, register 185 and a switch 186 , the output of which is connected to the appropriate inputs of adders 180 and 184. The inputs of adder 182 and subtractor 182 of the first channel are respectively connected to output angen 100 ^, ..., 100m + i (fig. 9) of digital filter unit 97, the inputs of adders 182 and subtractors 182 (fig. 12) of all other m-1 channels are connected to outputs IOO2 and 100m + 2, IOO3 and 100m + 3, respectively. ., 100m and 1002m (fig. 9) of unit 97. The outputs of dividers 181 (fig. 12) form 20 the channel outputs and the outputs 102i, ..., 102m of unit 99, respectively. Converter 99 is further provided of a series-connected adder 187 with inputs connected to correct outputs 100m + x, ..., 1002m of digital filter unit 97 and a subtractor 188 (fig. 12) with an output forming the output 101 of converter 99 and 25 further provided with register 189, the input of which forms one of the inputs of inputs of converter 99 connected to output 98 (fig. 9) of arithmetic unit 93 and the output of which is connected to the other input of subtractor 188. The clock inputs of adders 172, 174, 184, 187, subtractors 182, 188, multipliers 173, 183, regis-30 ters 175, 185, 189 are connected to output 128 (fig. 9) from synchronization pulse generator 123. The clock inputs of switches 176, 186 (FIG. 12), register 178, adder 180 and subtractor 181 are connected to output 129 (FIG. 9) of generator 123.

Adders 172, 184, 180, 184, 187 (Fig. 12), subtractors 182 and 188, and multipliers 173, 183 can be performed with art-known circuitry (U. Titze, E. Shenk "Semiconductor circuitry," a reference book. , 1982, pp. 335, 340. - In Russian).

Divider 181 can be performed with the 40 switching device known in the art (P. Rabiner, P. Gould "Digital signal processing 8720747.

30 theory and applications ", Moscow, MIR, 1978, biz. 584. - In Russian).

Registers 175, 185, 178, 189 and switches 176, 186 can be implemented with commercially available SN7400 series integrated circuit diagrams.

The principle diagram of buffer memory 96 is shown in FIG.

13. Buffer memory 96 is provided with switches 190 and 191. The input of switch 190 forms one of the inputs of buffer memory 96 and is connected to output 95 (fig. 9) of arithmetic unit 93 and 10 the input of switch 191 (fig. 13) is connected to output 101 (Fig. 9) of signal converter 99. Outputs 197 and 198 of switch 190 are connected bit by bit to the data inputs of working memories 192, 193. Outputs 199, 200 of switch 191 are connected to data inputs from working memories 194 and 195. The control inputs from switches 190, 191 are driven from the output 125 (Fig. 9) of synchronization pulse generator 123. The clock inputs from working memories 192, 193, 194, 195 are connected to outputs 124, 128 (fig. 9) of synchronization pulse generator 123 and the outputs of working memories 192, 193, 194, 195 (fig. 13) respectively are connected to the inputs of switch 196, the control inputs of which are connected on the outputs 125, 129 (fig. 9) of synchronization pulse generator 123, the output of which (fig. 13) forms the output of buffer memory 96 and is connected to input 108 (fig. 9) of spectral signal converter 107.

Switches 190, 191, 196 (Fig. 13) can be equipped with commercially available SN7400 series integrated circuits while operating memories 192, 193, 194, 195 can be equipped with MM2141-5 type integrated circuits.

The schematic diagram of buffer memory 134 is shown in Fig. 14. Buffer memory 134 is provided with switches 201, 202, 203 and working memories 204, 205, 206, 207. The control inputs of switch 201 are respectively connected to output 167 (fig. 9) of synchronization pulse generator 154 and on output 163 of demultiplexer 130, the data input of switch 201 (FIG. 14) forms the input of buffer 35 memory 134. Outputs 208, 209, 210, 211 of switch 201 become by-bit connected to the data inputs of working memories 204, 205, 206, 207, the clock inputs of which are connected to outputs 166 and 168 (fig. 9) of synchronizing pulse generator 154. The outputs of working memories 204, 205 (fig. 14) are connected to the inputs of 40 switch 202, the outputs of working memories 206, 207 are indicated 8720747.

31 locks on the inputs of switch 203. The control inputs of switch-1 to 202, 203 are connected to output 163 (fig. 9) of demultiplexer 130. The output of switches 202, 203 (fig. 14) form outputs respectively 143 and 144 of buffer memory 134 and are connected to the inputs of digital filter unit 142 (FIG. 9) and stereo signal regenerator 141, respectively.

Switches 201, 202, 203 (Fig. 14) can be implemented with commercially available SN7400 series integrated circuits, operating memories 204, 205, 206, 207 can be implemented with MM2141-5 integrated circuits.

The schematic diagram of stereo signal regenerator 141 is shown in Fig. 15. Stereo signal regenerator 141 includes a series-connected adder 212 and register 213 and also a series-connected subtractor 214 and register 215. Correct inputs of adder 212 and subtractor 214 are connected together and form input 145 of regenerator 141 and are further connected to output 144 (fig.

9) from buffer memory 134. The output of register 213 (fig. 15) is connected to input 216 of adder I 217 and the output of register 215 is connected to input 218 of adder 219. Regenerator 141 20 is further provided with m identical channels equipped with multipliers 220i, ..., 220m, registers 221χ, ..., 221m and 222χ, ..., 222m and subtractors 223χ, ..., 223m. The first inputs of all multipliers 220 ^, ..., 220m are the data inputs 140 ^, ..., 140m of regenerator 141 and are connected to the 25 outputs of code converters 137 ^, ..., 137m ( Fig. 9). The other inputs of multipliers 220 ^, ..., 220m (fig. 15) are combined with the outputs of registers 222χ, ..., 222m and form inputs 1452, ···> 145m + i, which are connected to the outputs of digital filter unit 142 (Fig. 9). The outputs of multipliers 220χ, ..., 220m (fig. 15) are connected bit by bit to the data inputs of registers 221χ, ..., 221m and to correct inputs of subtractors 223χ ..... 223m, the other inputs of which receive signals from the outputs of registers 222i, ..., 222m.

The outputs of registers 221χ 9 ..., 221m form the channel outputs and are connected to the inputs 224 ..., 224m of the adder! er 217, the outputs of subtracters 223 ^, ..., 223m form the other channel outputs and are connected to inputs 225i, ..., 225m of adder Ier 219. The outputs of adder Iers 217 and 219 form outputs 146 and 149 of regenerator 141 and are connected to the inputs of digital analog converters 87 0747, respectively.

32 147 and 150 (Fig. 9). The clock inputs of adders 212, 217, 219 (fig.

15), subtractors 214, 223i, ..., 223m, registers 213, 215, 221i, ..., 221m, 222i, ..., 222m are connected to output 168 (Fig. 9) of synchronization pulse generator 154.

Adder Irish 212, 217, 219 and multipliers 220, ..., 220m (Fig. 15) can be performed with art-known switching devices (U. Titze, K. Shenk "Semiconductor circuitry", a reference 1982, p. 334, 335, 340. - In Russian). Registers 213, 215, 221χ, ..., 221m can be implemented with commercially available SN7400 series integrated circuits.

Fig. 16 depicts the amplitude-frequency response characteristics of digital filters 171χ, ..., 1712m (Fig. 11) in digital filter unit 97:

Fig. 16a depicts the amplitude-frequency response of filters 171i and 171m + x (FIG. 11), where fo and fi are the critical frequencies of the passband of filters 171χ and 171m + x;

Fig. 16b depicts the frequency response of filters 17I2 and 171 ^ + 2 (FIG. 11), where fi and f2 are the critical frequencies of the pass bands of filters 1712 and 171m + 2; FIG. 16c depicts the frequency response of filters 171m and 17l2m (Fig. 11), where fm_i and fm are the critical frequencies of the pass bands of filters 171m and 17l2m.

The system for encoding and decoding stereo sound program signals according to the invention functions as follows.

In the encoder of the system, analog signals from the left and right stereo channels are applied to the inputs of low-pass flashes 88, 90 (FIG. 9) and are then transferred to analog-to-digital converters 89, 91; 1 low-pass flashers 88, 90 are similar to low-pass filter 1 (Fig. 1), analog-to-digital converters 89, 91 are similar to analog-to-digital converter 2 (Fig. 1). Code words of left and right stereo channel readings produced by analog-to-digital converters 89, 91 (FIG. 9) are transferred to arithmetic unit 93 in which their half sum X + and half difference X. are calculated. The half sum X + of the 35 left and right stereo channels of code words describing output 95 are transferred to the correct input of buffer memory 96.

Stereo information is extracted and encoded by submitting the code words corresponding to the half sum X + and half difference X_ of the left 40 and right stereo channels to the pass 8720747 t 33 band filtering in digital filter unit 97 provided is of two identical combs of m filters, 171χ, 171m and 171m + i, 17l2m, for the half-sum X + and half-difference X_ signals, respectively. The frequency response characteristics of filters 5171, 1712m are shown in Fig. 16. As a result, m readings of filters half-sum signals X + (D, X + (2)} ..., x + (m) are produced at outputs ΙΟΟχ, 10Qfn of digital filter unit 97 (Fig. 11) and m readings of filtered half-difference signal and xJD, xj2), ..., 10 X>) are produced at outputs 100m + i, ..., 1002m . These trains of readings are transferred to converter 99 (FIG. 9) along with a signal corresponding to half the difference X_ of output 98 of the arithmetic unit 93.

Converter 99 performs the calculation for each pair of filtered sig-15 signals X + (i), xJ1 ") (i = 1, 2, ..., m) of the ratio

Pi = EL (1 V (EL (D + ER (D) (3) where Ε ^ 1 ') and Er (ï) are the energies of signals 20 X ^ i) and XR (i) from the left and right, respectively) stereo channels where XL (i) = X + (i) + x_ (i) (4) XRii) = X + (i) - X. (i) (5)

The energy is calculated in a time interval T = N / Fd corresponding to N readings of the input signal such that 30 Nl EL ('> = 21 [XL (1> (n)] 2 (6) n = 0 /.x Nl 35 Er (i) = Σ1 CXR (l) (n)] 2 (7) n = 0

As mentioned, the energy is calculated during a time interval corresponding to N readings, so that the ratio Pi (i = 1 »2, ..., 40 m) is also determined once during this time interval. Furthermore, 8720747.

34, converter 99 also produces readings of the difference signal filtered in a frequency bandwidth from zero to fo in accordance with the equation: ® m

Xj °) = X- - IZ X- (l) (8) i = 1

Converter 99 (Fig. 12) is provided with m identical filtered signal processing channels for the X + (i) and xji) signals, so that the examination of a channel is sufficient. Code words from filtered signal readings X + (i), xJi) from outputs 100i and 100m + i of digital filter unit 97 (Fig. 11) arrive at the inputs of adder 172 and subtractor 182, into the outputs 15 of which code words are produced in accordance with the first filtered signals X ^ D and Xr (1> of the left and right stereo channels, respectively, which are transmitted to multipliers 173 and 183, at the outputs of which the squares of filtered signals [X ^ 1) ] 2, [Xr (D] 2) corresponding code words are generated The values of energies E | _ (1) and of the filtered signals are calculated using adders 174 and 184, registers 175 and 185 and switches 176 and 186. The start of the addition cycle is set by a clock signal from output 129 (Fig. 9) of synchronization pulse generator 25 123 that arrives at the input of converter 99 and ensures that switch 176 (Fig. 12) correctly inputs the outputs of register 175. add up Irish 174. The second group of inputs of adder Ier 174 receives corresponding squares from the left channel with the squares of filtered signal readings [XL (1)]. The result of addition is entered into register 175. Thus, at the end of the addition cycle, register 175 accumulates the total sum of squared readings of filtered signals of the left channel according to equation (6) with this sum of energy E | _ d ) displays the filtered signal. The energy of the filtered right channel signal is calculated in a similar manner using adder 184, register 185 and switch 186.

Upon completion of the addition cycle, register 175 upon arrival of a clock signal from output 129 of switch 176 of 40 synchronization pulse generator 123 (Fig. 9) couples outputs of register 175 to 87 20747.1 35, inputs of register 178 and switch 186 couples outputs of register 185 at inputs of adder 180. Register 178 delays the code word, which corresponds to the energy of the filtered signal from the left stereo channel, by the duration of the adder in adder 180, at the output of which a code word is generated corresponding to the sum E | _ ^) + Er (D of energies of filtered signals from the left and right stereo channels that are transferred to proper inputs of divider 181. The other inputs of divider 181 receive one with the value of E | _ (D corresponding code word, ie the energy of the left channel signal. Divider 181 generates a code word corresponding to the value of ratio Pi according to king (3).

Processing channels, in which the P2, ... »Pm ratios are calculated, function in a similar manner. The operation of counters 172, 174, 184, multipliers 173, 183, registers 175, 185 and subtractors is time-controlled by clock pulses at which the signal-readings repetition rate arrives at the input of converter 99 (Fig. 9) output 128 of synchronization pulse generator 123. The operation of register 178, adder 180 and divider 181 (Fig. 12) is synchronized by a key pulse, which arrives from output 129 of synchronization pulse generator 123 to the input of converter 99 and sets the duration of the addition cycle during the calculation of the energy of the filtered signals.

The difference signal, X_ (°), which is filtered in a frequency band from zero to fo, is calculated using adder 187, subtractor 188 and register 189 (Fig. 12). Inputs 100m + i, ..., 1002m from converter 99, i.e. the inputs of adder 187, receive filtered signals X _. (D, Χ_ ^), ...

X>). Code words corresponding to sums of the filtered signals from the output of adder 187 are transferred to the first group of inputs of subtractor 188, the second group of inputs of which receives the difference signal X- delayed in register 189 for the duration of operation of adder 187. As a result, subtractor 188 at its output with signal readings X_ (°) produces matching code words in accordance with equation (8).

Trains of code words corresponding to ratios Pj_, ..., Pm with a repetition rate Fd / N from outputs 102] _, ..., 102m from converter 99 pass to the inputs of code converters 103χ, ... »103m (fig. 9). Sequences of code words from signal-40 readings X_ (0) with a repetition rate Fd are transmitted 8720747; 36 from output 101 of converter 99 to a proper input of buffer memory 96 (FIG. 9).

Buffer memory 96 delays the input signals, ie trains code words of the half-sum of signal readings in the left and right stereo channels, X + and the filtered half-difference signal, to match their rates to that of the current at the input of spectral converter 107. For this purpose, signals X + and X_ (0) are applied to the inputs of switches 190, 191 (Fig.

13) which are controlled by the addition cycle setting key pulse.

10 This key pulse sets the duration of processing in converter 99 (fig.

9) so that the time interval during which a spectral analysis is performed is equal to the time interval of averaging the squares of signal readings for the calculation of energies E [_ (i) and Ep (i). Thus, switches 190, 191 during the first N clock periods allow signal readings X + and XJ0) to be inserted into working memories 192 and 194, respectively, and during the following N clock periods - into working memories 193 and 195, respectively, while the contents of working memories 192 and 194 are read. Data is input into working memories 192, 20 193, 194, 195 at a clock speed of Fd and reading takes place at a speed of 2Fd · Switch 196 alternatively connects the input of buffer memory 96 to the outputs of working memories 192, 193, 194, 195 this resulting in a train of code words with signal readings X + and X_ (0) with a 2Fd repetition rate, wherein a group N code words of X + signal readings are first generated and followed by a group of N code words of xJ °) signal readings, etc. .

The train code words of X + and X_ (0) signal readings arrive at the spectral converter 107 (Fig. 9) and are then transferred to code converter 109 which is controlled by signals from control pulse generator 112 and number memory 115, in which numbers of spectral components of critical audio frequency bands are stored. Control pulse generator 112 and number memory 115 function as previously described for mono signal encoding.

Code converters 103j_, ..., 103m recode the codewords corresponding to ratios P1, ..., Pm into a floating-point notation as known in the prior art system.

Power and mantissa codewords from the outputs of code converters 103i, ..., 103m are transferred to multiplexer 105 in 40 inputs 104i, ... »104m and 106 ^, ..., 106m for the combination in 8720747 Γ * 37 a single digital stream with a repetition rate Fs defined as:

Fs = Fmi + FM2 + Fp (9) 5 where Fj / ιχ is the pulse repetition rate in the X + code word,

Fji / | 2 is the pulse repetition rate in the codeword and Fp is the pulse repetition rate of ratios Ρχ, Pm codewords.

During stereo signal encoding and decoding, the decoder demultiplexer 130 (FIG. 9) receives a sequence of binary symbols from the encoded sound program digital signal, from which it extracts binary symbols from the Fs repetition rate and also extracts the key signal. at a repetition rate of 15 Fjj / N from the received cycle timing symbols. Demultiplexer 130 also separates the received data stream into power and mantissa codeword sequences from encoded filtered signals and into half sum signals from the left and right stereo channel signals. The sequences of power and mantissa codewords are transferred from -20 from the output of demultiplexer 130 to the inputs of code converters 131, 137χ, ..., 137m for conversion of the codewords in accordance with ratios Ρχ ..... Pm from the floating point notation in the fixed point notation. Signals generated by code converters 137χ, ..., 137m are transmitted to inputs 140χ, ..., 140m of stereo signal regenerator 141.

Code converter 131 recodes spectral components of the X + and X_ (0) signals of the subblock floating point notation into a fixed point notation in the same manner as in the mono signal decoder. Code converter 131 is controlled by signals arriving from outputs 155, 156, 157, 158 of control pulse generator 152 and from number memory 153, in which numbers of spectral components of critical audio frequency bands are stored. Spectral component codewords from code converter 131 are transferred to buffer memory 132 and then to reverse spectral converter 133.

The operation of code converter 131, buffer memory 132, reverse spectral converter 133, number memory 153 and control pulse generator 152 is the same as that of respective comparable units in the mono signal decoder.

Code words of signal X + and X_ (°) readings from the output of reverse spectral converter 133 are transferred 57207477 38 to buffer memory 134 for their delay and their separation in X + and xJ0) signal-reading code words. Thus, buffer memory 134 performs reverse processing compared to that of buffer memory 96 (Fig. 9) in the stereo signal encoder.

5 The train of X + signal reading code words with an F (j | repetition rate is applied to the input of digital filter unit 142 (Fig. 9), which differs from digital filter unit 97 by the presence of a more supplemental (m + 1) digital filter with a passage from DC to fo · Filtered signals X + ^) s 10 X + (D ..... X + (m) from the outputs of digital filter unit 142 are transferred to inputs 145i , 145ΐ] ΐ + ι of stereo sound regenerator 141. Code words of X_ (0) signal readings are further applied to the input of regenerator 141 from output 144 of buffer memory 134.

Stereo signal regenerator 141 stores the signals of the left and right stereo channels again from the filtered X + (0) s X + (1), .... x + (») half-sum signals of the left and right stereo channels. channels and from the low-pass filtered difference X_ (°) signal and using the values of ratios Pi, ..., Pm of the left channel signal energy to the sum of energies of filtered signals of the left and right channels. The left stereo channel signal filtered in a frequency band from DC to FG forms: 25 XL (0) = χ + (0) + χ_ (0) (10) and that of the right stereo channel will be: XR (°) = X + (0) - X_ (0) (11) 30

The rest of the filtered signals are stored again according to the following equations: XL (i) = X + (i) pi (i = 1, 2, ..., m) (12) 35 XR (i) = X + (i) (1-Pj) = Χ + Π) -XL (1) (13)

The total left channel signal saved again is: 87207477 5 39 m,.

Χ | _ = ΣΙ XL {1) (14) 1 = 0 and that of the right stereo channel is: m, t

Xr = 2_ Xr () (15) 10.0

In stereo signal regenerator 141, code words of signals x + «» and X_ (°) are applied to the inputs of adder 212 (Fig. 15) in the output of which code words of X [_ (0) sig-15 sewing readings are provided and transferred to register 213. The signals X_ (°) also arrive at the input of subtractor 214, at the output of which code words of Xr (0) signal readings are supplied and transferred to register 215. Code words of filtered X + (D signal readings are supplied) applied to the first 20 input of multiplier 220 \ and to the input of register 221i The second input of multiplier 220χ forms input 140χ of regenerator 141, receives code words from Pi ratios from the output of code converter 137χ (Fig. 9). again stored filtered signal X | _ (D readings from the left stereo channel appear at the output of multiplier 220 and are transferred to register 221χ and to the first input of subtracter 223i, where from the second input, delayed in register 222χ for a clock period, receives multiplication codewords from the filtered Xr (D signal from the right stereo-30 channel. In a similar manner, the filtered X | _ (2), ... XL (m) and Xr (2), xR (m) signals are stored. Registers 213, 215, 222χ9 ..., 222m serve for the delay of code words of Xi_ (°! Xr (° I Xl ^ I ··· »X [_ (m) signals with the period of operation of subtractors 223χ, 35 ..., 223m Adders Irish 217, 219 add up the stored again filtered X | _ (i) and Xr (ï) (i = 0, 1, 2, ..., m) signals arriving at their 216, 224χ, ..., 224m, and 218, 225i, ..., 225m inputs, respectively, so that codewords from stored left and right channel signals are reproduced on their outputs and transmitted to digital-analog converters 147, 150 (Fig. 9) 8720747.

140 and then to low-pass flashes 148 and 151. The stored signals from the left and right stereo channels are generated at the outputs of low-pass filters 148 and 151.

Thus, during the stereo signal coding on the encoding output of the system, the stereo signal is reproduced by a digital stream at a rate:

Vs =% L + Vj / | 2 + Vp bits per second (16) 10 where V ^ i is the repetition rate of the encoded signal X + of the half sum of signals in the left and right stereo channels equal to the repetition rate of the digital stream at the output of the encoder for mono sound program signals and therefore 15 VMi = (24kp + Nkm) Fd / N (17)

Vm2 is the bit rate of the encoded signal X_ of half the difference of signals in the left and right stereo channels filtered in a frequency band from DC to fQ. Since at frequencies above fg the energy of xj0) signals is zero, spectral components with numbers above Ni = NfQ / (Fd / 2) are also zero and do not need to be encoded; consequently, the bit rate of the digital stream is: 25

Vm2 = (22-m) kp + Nikm Fd / N bits per second (18) where m is the number of high-frequency critical audio frequency bands in which ratios Ρχ, ..., Pm are calculated. Vp in comparison (16) is the bit rate of the digital stream of encoded signals corresponding to ratios Pl, ..., Pm and is:

Vp = m (kp '= km'lFd / N bits per second (19), where kp' and km 'are the bit capacities of the power and the mantissa of codes of ratios Pi, ..., Pm, respectively.

Experimental studies of the system according to the invention were carried out with bandwidths fo, fi, ..., fn selected equal to critical audio frequency bands, with fo = 6400, so that in a frequency band corresponding to twin-40-frequency groups, the stereo-ef # 8720747, ί # 41 feet completely preserved. Quasi-stereophony is provided in each of the other four critical audio frequency bands. Since the human ear is practically insensitive to stereo sound in the high-frequency range, such a frequency band quasi-stereophony at 5 frequencies above 6400 Hz is sufficient to ensure stereo reception. The following encoding parameters are used: kp '= 4, km' = 5, M = 4, Ni = 412. The rest of the parameters were chosen the same as those used in encoding mono sound program signals. The sound quality of the decoded stereo sound program signal was no different from that of the initial signal. The bit rate of the digital stream at the encoder output of the system according to equations (16), (17), (18) and (19) was 228 kilobits per second, ie was 1.4 times lower than in the encoder according to claim 1 for stereo signals with independent encoding of signals from the left and right stereo channels.

Industrial applicability

The system according to the invention is intended for use in digital systems for signal transmission, recording, storage and reproduction in digital broadcasting, multifunctional communication, sound program transmission systems from the earth and from a satellite and in digital systems for the replenishment of sound program transmission in television.

0720747 ^

Claims (2)

1. Sound program signal coding and decoding system comprising an encoder having a series-connected low-pass fliter (1), the input of which forms the encoder input, an analog-to-digital converter (2), a code converter (6) connected to the analog-to-digital converter (2), a synchronization pulse generator (21) connected to the clock inputs of the analog-to-digital converter and the code converter (6) and a decoder with a code converter (29) and a series-connected digital-to-analog converter (32 ) which is electrically connected to code converter (29) and low-pass filter (33), the output of which constitutes the decoding output and also comprises a synchronization pulse generator (44), of which an output (48) is connected to the clock input of digital analog converter (32), characterized in that during the coding and decoding of mono sound program signals the co-coding device is provided with a buffer memory (3) with the correct inputs at bit are connected to the outputs of analog-to-digital converter (2) and the clock and time inputs are respectively connected to outputs (22, 23) of synchronization pulse generator (21), a sound program signal spectral converter (4) with the output 20 data inputs connected to the buffer memory (3), cycle and clock inputs connected to outputs (22, 23) of synchronization pulse generator (21) and outputs connected to the data converter of code converter (6) at bit, respectively control pulse generator (9) with clock inputs connected to correct outputs (23, 24, 25) of synchronization pulse generator (21) and outputs connected to control inputs (7, 8) of code converter (6), a number memory (12) for storing the number of spectral components of critical audio frequency bands with control inputs (13, 14, 15) connected to the correct outputs of the control pulse generator (9) and to data inputs (10, 11) of control pulse-30 generator (9) connected output and where the clock input is connected to the output (23) of synchronization pulse generator (21), a multiplexer (16) with data inputs connected to outputs (17, 18) of code converter (6), with correct outputs of control pulse generator (9) connected control inputs (19, 20), with clock inputs connected to correct (23, 25) outputs of synchronization pulse generator (21) and outputs forming the encoding output, and the decoding device comprising a demultiplexer (26) whose input the decode! input and is connected to the outputs of multiplexer (16), the data outputs of which are connected to correct inputs of 40 code converter (29) and of which a clock input is connected to correct 8720 74 7. inputs of synchronization pulse generator (44) and of code converter (29), buffer memory (30) with bit inputs connected to correct outputs of code converter (29) and with clock inputs of the multiplexer (26) connected to correct outputs (48, 46) of synchronization pulse generator (44) reverse spectral converter (31) for sound program signals with data inputs connected to correct outputs of buffer memory (30) at bit, with clock inputs connected to correct outputs (48, 46) of synchronization pulse generator (44) and demultiplexer (26) and with outputs connected to correct inputs of digital-analog converter (22) at-10 bit, a control pulse generator (34) with appropriate outputs (45, 46, 47) of demultiplexer (26) and of synchronization pulse nerator (44) and clock inputs connected to an output (47) connected to the clock converter code converter (29), the outputs (35, 36, 37, 38) of control pulse generator (34) being connected to the 15 control inputs of code converter (29), buffer memory (30) and demultiplexer (26), number memory (41), respectively, for storing spectral component numbers of critical audio frequency bands with appropriate outputs (42, 43) of control pulse generator (34 ) connected control inputs, with a clock input connected to output (46) of the multiplexer (26) and with outputs (39, 40) connected to the data inputs of control pulse generator (34). System for the encoding and decoding of sound program signals, comprising an encoder and a decoder, the encoder comprising a series-connected main layer 25 pass filter (88), the input of which forms the encoder input and a master-analog-digital converter (89), a master code converter (109) electrically connected to the master-analog-digital converter (89), one to the clock inputs of master-analog-digital converter (89) and main code converter (109) connected synchronization pulse generator (123) and 30, wherein the decoder is provided with a master code converter (131) and an electrically master-code converter (131) connected in series-connected master digital-analog converter (147) and a master low-pass filter (148), the output of which constitutes the decoding output, further comprising a synchronization pulse generator (154), connected to an output connected to the clock input of main digital-analog converter (147), with the characteristic k, that during the encoding and decoding of stereo sound program signals the encoder is provided with a series-connected supplementary low-pass filter (90), the input of which forms the supplementary input of the encoder and a supplementary analog-digital converter (91) with an the correct output 8720747. $ • 44 gang (128) of synchronization pulse generator (123) connected clock input, an arithmetic unit (93) with analog-to-digital converters at the outputs of main (89) and auxiliary (91) respectively. bit-connected data inputs (92, 94) and with a clock input connected to the correct output 5 (128) of synchronization pulse generator (123), a digital filter unit (97) with bit-connected to correct outputs of the arithmetic unit (93) data inputs and with a clock input connected to the correct output (128) of synchronization pulse generator (123), a signal converter (99) for transmitting signal information over the stereo sound program signals with 2m groups of data inputs (m = 1, ... »24) connected at bit to outputs (100i, ..., 100m, 100m + i, ..., 1002m) respectively of digi language filter unit (97) and a group of data inputs connected to the correct outputs of the arithmetic unit (93) with an at-bit and with clock inputs connected to the correct outputs (128, 129) of the synchronization pulse generator (123), m supplementary code converters 103 ^, ..., 103m) with bit inputs connected to outputs (102χ, ..., 102m) of signal converter (99) for signals containing information about the stereo sound program signals and with appropriate outputs ( 129, 128) 20 clock inputs connected from synchronization pulse generator (123), a multiplexer (105) with bit inputs connected to outputs (113, 114) of master code converter (109) and with appropriate outputs (124, 125, 127, 128, 129) of the clock inputs connected to the synchronization pulse generator (123) and having a, the coding output forming output, 25 where each of the m additional code converters (103χ, ..., 103m) two groups on proper data inputs (104χ, ..., 104m, 106 ^ ..... 106m) of multiplexer (105) connected outputs, a buffer memory (96) with a group of data inputs connected to the output (95) of the correct arithmetic unit (93) and with a second group of at-bit on the correct output (101) of signal converter (99) connected data inputs for signals containing information about stereo sound program signals and with clock inputs connected to appropriate outputs (124, 125) of synchronization pulse generator (123), a sound program signal spectral converter (107) having data inputs (108) connected to the out-of-outputs of buffer memory (96) at bit and with cycle and clock inputs connected to correct outputs (124, 125) of synchronization pulse generator (123) and to data inputs of main code converter (109) at bit-connected outputs, a control pulse generator (112) with clock inputs connected to the correct outputs (125, 126, 127) of the synchronization pulse generator (123) and with the control input 0720747. '* V gen (110, 111) of master code converter (109) connected outputs and with outputs (121, 122) connected to outputs of multiplexer (105), a number memory (115) for the storage of component numbers of critical audio frequency bands with the outputs of the 5 correct control pulse generator (112) connected control inputs (116, 117, 118) and with outputs (119, 120) connected to data inputs of control pulse generator (112) and one connected to the correct output (125) of synchronization pulse generator (123) clock input and wherein the decoding direction is provided with a demultiplexer (130) whose input forms the decoding input and is connected to the output of multiplexer (105) of the encoder and of which the correct outputs (135, 136) are connected on the data inputs of decode-ho ofd-code converter (131) and of which a clock output (164) is connected to correct inputs of synchronization pulse generator (154) and of decoder-master-decoder (131), buffer memory (132) with correct outputs of decoder-master code converter (131) connected data inputs and with clock inputs connected to correct outputs (166, 167) of synchronization pulse generator (154), a reverse spectral converter (133) for sound program signals with at-bit on correct outputs of buffer 20 memory (132) connected data inputs and with clock inputs connected to correct outputs (167, 166) of synchronization pulse generator (154), a control pulse generator (152) with correct outputs (164, 165) of demultiplexer (130) and of synchronization pulse generator (154) connected clock inputs and with a proper input (167) connected to the clock input of decoder-master-code converter (131), the outputs (155, 156, 157, 158) of control pulse generator (152) being respectively and connected to the control inputs of decoder master code converter (131) of buffer memory (132) and of the multiplexer (130) number memory (153) for the storage of spectral component number1 and of critical audio frequency bands with correct outputs ( 159, 160) from control pulse generator (152) connected to control inputs with a clock input connected to the appropriate output (167) of synchronization pulse generator (154) and with outputs (161, 162) connected to data inputs from control pulse generator (152), m additional code converters (137 ^, ..., 137m) 35 each having two data inputs connected to proper outputs (138χ, ..., 138m, 139i, ..., 139m) of the multiplexer (130) and with clock inputs connected to outputs (168, 163) of synchronization pulse generator (154) and of the multiplexer (130), a stereo signal regenerator (141) with a clock input connected to the appropriate output (168) of synchronization pulse generator (154) 872074 7. ψ * corridor, a d digital filter unit (142) with a clock input connected to the correct output (168) of synchronization pulse generator (154) and to correct inputs (145χ, ..., 145m + i) of stereo signal regenerator (141) connected by bit (m +1) outputs, whose inputs 5 (140i, ··· »140m) are bit-connected to a proper output of each of the m supplementary code converters (137 ^, ..., 137m), a buffer memory (134) with data inputs connected to the bit of reverse spectral converter (133) at bit and to clock inputs (166, 167, 168, 163) of synchronization pulse generator (154) and demultiplexer (130) respectively, wherein a group (143) of buffer memory (134) at-bit outputs is connected to appropriate inputs of digital filter unit (142) and another group (144) of buffer memory (134) at-bit outputs is connected to appropriate inputs of stereo signal regenerator (141) and an auxiliary connected in series 15 digital-to-analog converter (150) and an auxiliary low-pass filter (151), the output of which constitutes the auxiliary output of the decoder, in which a group (146) of the outputs of stereo signal regenerator (141) is connected at-bit to the data inputs of the main digital-analog converter 20 (147) and another group (149) of the outputs of stereo signal regenerator (141) at bit is connected to the data inputs of auxiliary digital-analog converter (150), whose clock output is connected to the appropriate output (168) of synchronization pulse generator (154). +++++++ 8720747.