JPS6273737A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6273737A JPS6273737A JP21532185A JP21532185A JPS6273737A JP S6273737 A JPS6273737 A JP S6273737A JP 21532185 A JP21532185 A JP 21532185A JP 21532185 A JP21532185 A JP 21532185A JP S6273737 A JPS6273737 A JP S6273737A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- silicon
- polycrystalline silicon
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に溝絶縁分離を有する半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having trench isolation.
従来、多結晶シリコンで埋設された溝によって素子分離
を行ガう場合、溝内部に多結晶シリコンが埋設された溝
の上部に埋設多結晶シリコンを酸化してシリコン酸化膜
全形成するが、この際このシリコン酸化膜が素子領域に
喰い込む事を防ぐ為、溝内壁にシリコン酸化膜とシリコ
ン窒化膜の二層膜を有する構造が用いられていた。第3
図は従来の二層膜構造の絶縁分離領域を有する半導体装
置の断面図であり、図において101はシリコン基板、
105及び104は二層膜を構成するシリコン酸化膜及
びシリコン窒化膜である。また102は二層膜の内側の
溝を埋めt多結晶シリコンであり、203は多結晶シリ
コンを酸化して形成した溝上部のシリコン酸化膜である
。Conventionally, when element isolation is performed using a trench filled with polycrystalline silicon, the buried polycrystalline silicon is oxidized to form a full silicon oxide film on the top of the trench with polycrystalline silicon buried inside the trench. In order to prevent this silicon oxide film from digging into the element region, a structure in which the inner wall of the trench has a two-layer film of a silicon oxide film and a silicon nitride film has been used. Third
The figure is a cross-sectional view of a conventional semiconductor device having an insulating isolation region with a two-layer film structure. In the figure, 101 is a silicon substrate;
105 and 104 are a silicon oxide film and a silicon nitride film forming a two-layer film. Further, 102 is polycrystalline silicon that fills the groove inside the two-layer film, and 203 is a silicon oxide film above the groove formed by oxidizing polycrystalline silicon.
上述した従来方法では、埋設多結晶シリコンを酸化して
溝上部に酸化膜を形成する際、この酸化膜が溝内壁のシ
リコン窒化膜と接する部分で酸化膜が薄くなる為に後工
程で、溝上部の酸化膜が部分的に無くなり多結晶シリコ
ンが露出して配線系の短絡、しきい値電圧VT2 の
低下をもたらすと云っ之問題がある。In the conventional method described above, when the buried polycrystalline silicon is oxidized to form an oxide film on the top of the trench, the oxide film becomes thinner at the part where it contacts the silicon nitride film on the inner wall of the trench. There is a problem in that the oxide film on the surface is partially removed and the polycrystalline silicon is exposed, resulting in a short circuit in the wiring system and a decrease in the threshold voltage VT2.
本発明は、従来技術の問題点を除き、構造的に安定し次
素子分離溝を有する半導体装置を提供する事を目的とす
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the problems of the prior art and provide a structurally stable semiconductor device having a sub-element isolation groove.
本発明の半導体装置は、半導体基板上に誘電体膜と多結
晶シリコンによって埋設された溝を有し、該溝で素子間
の絶縁分離を行なっている半導体装置に於いて、前記溝
の内壁に沿って第1のシリコン酸化膜とシリコン窒化膜
と第2のシリコン酸化膜からなる三層膜が形成され、該
三層膜の内部に多結晶シリコンが埋設され、該多結晶シ
リコン上には第3のシリコン酸化膜が形成され、該第3
のシリコン酸化膜は前記第2のシリコン酸化膜と接続部
分でくびれる事なく接続されて構成される。The semiconductor device of the present invention has a groove buried in a dielectric film and polycrystalline silicon on a semiconductor substrate, and in the semiconductor device in which insulation isolation between elements is performed by the groove, the inner wall of the groove is A three-layer film consisting of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film is formed along the line, polycrystalline silicon is buried inside the three-layer film, and a third layer is formed on the polycrystalline silicon. A silicon oxide film of No. 3 is formed, and the third silicon oxide film is formed.
The silicon oxide film is connected to the second silicon oxide film without being constricted at the connecting portion.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の断面図であり、また第2図
ta+〜fflは第1図に示し九−実施例の製造方法全
説明するために工程順に示した断面図である。FIG. 1 is a cross-sectional view of one embodiment of the present invention, and FIG. 2 ta+ to ffl are cross-sectional views shown in the order of steps to fully explain the manufacturing method of the ninth embodiment shown in FIG.
まず第2図(a)〜+f)にもとすき製造方法につき説
明する。First, the manufacturing method for the plow will be explained with reference to FIGS. 2(a) to +f).
まず、第2図(alに示すように、シリコン基板101
上にシリコン酸化膜106、それに重ねてシリコン窒化
膜107 fc影形成、第1の二層膜を形成する。First, as shown in FIG.
A silicon oxide film 106 is formed thereon, and a silicon nitride film 107 (fc) is formed over the silicon oxide film 106 to form a first two-layer film.
次に写真蝕刻技術によりホトレジストマスクを形放し、
このホトレジストマスクとして溝形成領域の第1の二層
膜をエツチングし、更にシリコン基板をエツチングして
溝を形成する。Next, the photoresist mask is released using photolithographic technology.
Using this photoresist mask, the first two-layer film in the groove forming region is etched, and the silicon substrate is further etched to form a groove.
次に、第2図(b)に示すように、第1の二層膜全マス
クとして溝の内壁のみにシリコン酸化膜105を形成し
、次いでシリコン窒化膜107ヲ除去し、新たにシリコ
ン窒化膜104ヲ成長させる。次すで気相成長法或いは
スパッタ法等でシリコン酸化膜ツチパックすることによ
シ溝の内部のみに多結晶シリコンを残す。Next, as shown in FIG. 2(b), a silicon oxide film 105 is formed only on the inner wall of the trench as a first two-layer mask, and then the silicon nitride film 107 is removed and a new silicon nitride film is formed. Grow 104. Next, polycrystalline silicon is left only inside the trench by sputtering a silicon oxide film using a vapor phase growth method or a sputtering method.
次に、第2図(dlに示すように1バツフアート弗酸液
でシリコン酸化膜103 ftエツチングする。この際
シリコン酸化膜103の上端を埋設多結晶シリコンの上
面よシ低くなるように、エツチング時間を調節する。Next, as shown in FIG. 2 (dl), the silicon oxide film 103 ft is etched with a 1 buffer hydrofluoric acid solution. At this time, the etching time is set so that the upper end of the silicon oxide film 103 is lower than the upper surface of the buried polycrystalline silicon. Adjust.
次に、第2図(elに示すように埋設多結晶シリコン1
02t−酸化し表面にシリコン酸化膜103a f形成
する。Next, as shown in Figure 2 (el), the buried polycrystalline silicon 1
02t - Oxidize to form silicon oxide films 103a to 103f on the surface.
次に第2図げ)に示すように、素子領域のシリコン窒化
膜104とシリコン酸化膜106を除去し、後工程を経
て素子を形成する。Next, as shown in Figure 2), the silicon nitride film 104 and silicon oxide film 106 in the element region are removed, and the element is formed through a post-process.
以上の実施例で実現された半導体装置は、第1図に示し
たように、溝の内壁に沿って、第1のシリコン酸化膜1
05 、シリコン窒化膜104.第2のシリコン酸化膜
103の三層膜が形成され、その三層膜の内部に多結晶
シリコン102が埋設され、その多結晶シリコン上には
第3のシリコン酸化膜1oaaが形成され、その第3の
シリコン酸化膜103aは第2のシリコン酸化膜103
と接続部分でくびれる事なく接続されている構造を有し
ている。As shown in FIG. 1, the semiconductor device realized in the above embodiment has a first silicon oxide film 1 along the inner wall of the trench.
05, silicon nitride film 104. A three-layer film of a second silicon oxide film 103 is formed, polycrystalline silicon 102 is buried inside the three-layer film, a third silicon oxide film 1oaa is formed on the polycrystalline silicon, and the third silicon oxide film 103 is formed. The silicon oxide film 103a of No. 3 is the second silicon oxide film 103
It has a structure in which it is connected without constricting at the connecting part.
従って、第3図に示したシリコン酸化膜105とシリコ
ン窒化膜104の二層膜しかな−従来例に比べ溝上部の
酸化膜が溝壁部分でくびれない構造とすることができる
。Therefore, it is possible to create a structure in which the oxide film on the upper part of the trench is not constricted by the trench wall portion, compared to the conventional example, which is only a two-layer film consisting of the silicon oxide film 105 and the silicon nitride film 104 shown in FIG.
以上説明しtように1本発明は、溝壁に形成されている
シリコン窒化膜上にシリコン酸化膜が形成されている為
埋設多結晶シリコン上に形成された酸化膜が、溝の壁近
辺でくびれる事がなく、従来構造での問題を解決でき、
更に、従来構造に比べ溝壁の誘電体膜の膜厚が厚い事に
より、素子間の結合容量が減少する効果も有しており、
本構造の溝を用いる事により、高信頼性、高性能の半導
体装置が得られる。As explained above, in the present invention, since the silicon oxide film is formed on the silicon nitride film formed on the trench wall, the oxide film formed on the buried polycrystalline silicon is There is no constriction, and the problems with conventional structures can be solved.
Furthermore, the thicker dielectric film on the trench wall compared to the conventional structure has the effect of reducing the coupling capacitance between elements.
By using the groove of this structure, a highly reliable and high performance semiconductor device can be obtained.
第1図は本発明の一実施例の断面図、第2図tar〜(
f)は第1図に示す一実施例の製造方法を説明するため
に工程順に示した断面図、第3図は従来の半導体装置の
一例の断面図である。
101・・・・・・シリコン基板、102・・・・・・
多結晶シリコン、103・・・・・・シリコン11化1
1L 103 a・・・・・・シリコン酸化膜、104
・・・・・・シリコン窒化膜、105・・・・・・シリ
コン酸化膜、106・・・・・・シリコン酸化膜、10
7・・・・・・シリコン窒化膜、203・・・・・・シ
リコン酸化膜。
代理人 弁理士 内 原 晋
マ21回
子づ躬
半21
茅Z劃FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment of the present invention.
f) is a cross-sectional view shown in order of steps to explain the manufacturing method of the embodiment shown in FIG. 1, and FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device. 101...Silicon substrate, 102...
Polycrystalline silicon, 103...Silicon 11 oxide 1
1L 103 a...Silicon oxide film, 104
...Silicon nitride film, 105...Silicon oxide film, 106...Silicon oxide film, 10
7...Silicon nitride film, 203...Silicon oxide film. Agent Patent Attorney Shinma Uchihara 21st Kozuman Han 21 Kaya Zaku
Claims (1)
された溝を有し、該溝で素子間の絶縁分離を行なってい
る半導体装置に於いて、前記溝の内壁に沿って第1のシ
リコン酸化膜とシリコン窒化膜と第2のシリコン酸化膜
からなる三層膜が形成され、該三層膜の内部に多結晶シ
リコンが埋設され、該多結晶シリコン上には第3のシリ
コン酸化膜が形成され、該第3のシリコン酸化膜は前記
第2のシリコン酸化膜と接続部分でくびれる事なく接続
されている事を特徴とする半導体装置。In a semiconductor device having a trench buried in a dielectric film and polycrystalline silicon on a semiconductor substrate, and insulating and isolating between elements in the trench, a first silicon oxide layer is formed along the inner wall of the trench. A three-layer film consisting of a silicon nitride film and a second silicon oxide film is formed, polycrystalline silicon is buried inside the three-layer film, and a third silicon oxide film is formed on the polycrystalline silicon. A semiconductor device characterized in that the third silicon oxide film is connected to the second silicon oxide film without being constricted at the connection portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21532185A JPS6273737A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21532185A JPS6273737A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6273737A true JPS6273737A (en) | 1987-04-04 |
Family
ID=16670370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21532185A Pending JPS6273737A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6273737A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114654A (en) * | 1988-10-25 | 1990-04-26 | Sharp Corp | Manufacture of semiconductor device |
US5358891A (en) * | 1993-06-29 | 1994-10-25 | Intel Corporation | Trench isolation with planar topography and method of fabrication |
US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
US6396113B1 (en) | 1999-11-19 | 2002-05-28 | Mitsubishi Denki Kabushiki Kaisha | Active trench isolation structure to prevent punch-through and junction leakage |
US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
-
1985
- 1985-09-27 JP JP21532185A patent/JPS6273737A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114654A (en) * | 1988-10-25 | 1990-04-26 | Sharp Corp | Manufacture of semiconductor device |
US5358891A (en) * | 1993-06-29 | 1994-10-25 | Intel Corporation | Trench isolation with planar topography and method of fabrication |
US5536675A (en) * | 1993-12-30 | 1996-07-16 | Intel Corporation | Isolation structure formation for semiconductor circuit fabrication |
US6396113B1 (en) | 1999-11-19 | 2002-05-28 | Mitsubishi Denki Kabushiki Kaisha | Active trench isolation structure to prevent punch-through and junction leakage |
US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
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