JPS6272041A - キヤツシユメモリ制御装置 - Google Patents

キヤツシユメモリ制御装置

Info

Publication number
JPS6272041A
JPS6272041A JP60212821A JP21282185A JPS6272041A JP S6272041 A JPS6272041 A JP S6272041A JP 60212821 A JP60212821 A JP 60212821A JP 21282185 A JP21282185 A JP 21282185A JP S6272041 A JPS6272041 A JP S6272041A
Authority
JP
Japan
Prior art keywords
address
memory
block
data
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60212821A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0556543B2 (en:Method
Inventor
Izuyuki Uehara
上原　出之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60212821A priority Critical patent/JPS6272041A/ja
Publication of JPS6272041A publication Critical patent/JPS6272041A/ja
Publication of JPH0556543B2 publication Critical patent/JPH0556543B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP60212821A 1985-09-25 1985-09-25 キヤツシユメモリ制御装置 Granted JPS6272041A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60212821A JPS6272041A (ja) 1985-09-25 1985-09-25 キヤツシユメモリ制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60212821A JPS6272041A (ja) 1985-09-25 1985-09-25 キヤツシユメモリ制御装置

Publications (2)

Publication Number Publication Date
JPS6272041A true JPS6272041A (ja) 1987-04-02
JPH0556543B2 JPH0556543B2 (en:Method) 1993-08-19

Family

ID=16628911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60212821A Granted JPS6272041A (ja) 1985-09-25 1985-09-25 キヤツシユメモリ制御装置

Country Status (1)

Country Link
JP (1) JPS6272041A (en:Method)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6479843A (en) * 1987-09-22 1989-03-24 Nec Corp Information processor
EP0628912A4 (en) * 1992-02-28 1995-10-11 Oki Electric Ind Co Ltd CACHE STORAGE DEVICE.
WO2001037098A1 (fr) * 1999-11-16 2001-05-25 Hitachi, Ltd Dispositif et systeme informatique
JP2009288977A (ja) * 2008-05-28 2009-12-10 Fujitsu Ltd キャッシュメモリ制御装置、半導体集積回路、およびキャッシュメモリ制御方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0659614B1 (en) 1993-12-22 1998-08-19 Nihon Plast Co., Ltd. Reel device for cable

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177782A (ja) * 1983-03-25 1984-10-08 Nec Corp バツフアメモリ制御方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177782A (ja) * 1983-03-25 1984-10-08 Nec Corp バツフアメモリ制御方式

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6479843A (en) * 1987-09-22 1989-03-24 Nec Corp Information processor
EP0628912A4 (en) * 1992-02-28 1995-10-11 Oki Electric Ind Co Ltd CACHE STORAGE DEVICE.
US5634104A (en) * 1992-02-28 1997-05-27 Oki Electric Industry Co. Ltd. Cache memory apparatus for reading data corresponding to input address information
US5754814A (en) * 1992-02-28 1998-05-19 Oki Electric Industry Co., Ltd. Cache memory apparatus for reading data corresponding to input address information
WO2001037098A1 (fr) * 1999-11-16 2001-05-25 Hitachi, Ltd Dispositif et systeme informatique
JP2009288977A (ja) * 2008-05-28 2009-12-10 Fujitsu Ltd キャッシュメモリ制御装置、半導体集積回路、およびキャッシュメモリ制御方法

Also Published As

Publication number Publication date
JPH0556543B2 (en:Method) 1993-08-19

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Legal Events

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