JPS6271334A - Parallel type analog-digital converter - Google Patents

Abstract

PURPOSE:To realize low power consumption without sacrificing the converting speed of a parallel type A/D converter by providing a current control circuit increasing the operating current of a comparator requiring high speed operation and decreasing the operating current of the comparator not requested. CONSTITUTION:Comparators C1-C2N-1 are divided into plural numbers, e.g., M-set of comparator blocks. The current control circuit A introduces an analog input voltage VIN and also controls the current values of the comparator blocks 1-M. The value of the analog input voltage VIN is discriminated in the current control circuit A, the operating current of the comparator block (i) including the comparator (j) is increased and the operating current of the other comparator blocks is decreased by the control. The comparator whose output logic level Voutk changes, that is, the comparator requiring high speed operation is only the comparator (j). Thus, the converting speed as the A/D converter is reduced by providing the current control circuit A.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Object of the Invention (Field of Industrial Application) The present invention relates to reducing the power consumption of a parallel AD converter.

(Prior Art) FIG. 6 is a diagram showing the configuration of a conventional parallel AD converter. The figure shows an N-bit AD converter, in which the reference voltage ■T and 1-VTL are divided by a resistor R.
A reference voltage (2-1) is created, and this is simultaneously compared with the analog input voltage using (2-1> comparators).

The result is latched and encoded according to the clock input. Then, the output of encoder E is latched again, and a digital conversion output is performed.

(Problem to be solved by the invention) However, the above-mentioned means have the following problems.

A differential amplifier type comparator, which is often used as the comparators C1 to C2N-1 in FIG. 6, becomes faster as its operating current increases. Therefore, there is a trade-off relationship between the maximum sampling frequency and power consumption of the AD converter. Therefore, it is desirable to have an AD converter that reduces power consumption without reducing conversion speed.

An object of the present invention is to provide such a parallel AD converter.

``Structure of the Invention'' [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention increases the operating current of only the comparators that require speed among the many comparators, and The operating current of the comparator is reduced. In other words, the comparator is divided into multiple comparator blocks, and depending on the analog input voltage, the operating current of the comparator block to which the same reference voltage as that voltage is input is increased (i.e., the operating current of the other comparator blocks is increased). It is equipped with a current control circuit that reduces the R current.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention.

In the figure, VrH and vrt- are reference voltages, and these voltages are resistance-divided by a resistor string P1 in which a plurality of resistors R are connected in series as shown in the figure, to obtain reference voltages of a plurality of levels. Reference voltages of each level are introduced into one end of the comparators C+ to C2'-1, respectively. On the other hand, each comparator CI "'
An analog input voltage V1N'Ifi, which is a signal to be converted, is introduced to the other end of C2'-1. Each comparator C! The output terminals of ~C2'-+ are latched and connected to 1~LM. The output of this latch L+"-LM is then introduced into the encoder E. The cono encoder E converts the output of each of the comparators C+ to C2'J-1 into N-bit digital data. The signal is output to the outside by the latch and buffer B.

Here, in the device shown in FIG. 1, comparators C1 to C
2'-1 is divided into a plurality of comparator blocks, for example M1. A is a current control circuit which introduces an analog input voltage VIN and controls the current values of the comparator blocks 1 to M.

FIG. 2 is a diagram showing only the features of the present invention, that is, the comparator blocks 1 to M and the current control circuit A portion of FIG. 1.

The present invention will be described in detail as follows using FIGS. 1 and 2.

The analog input voltage V is the sofa voltage of the comparator Vr(j-+) * Vru) * Vru+
+), V r(iu) < VIN < V
r<i> (1) (a Kara V, c Shi) < v,
Suppose that the value has changed to N < V r < NeI).

At this time, the output logic level of the comparator is V. , 4(k
-1 to 2-1) is expressed as follows.

(1) V r(J”) <VIN <V rCk)
"Time V6Ut1 - Vout2""' -vaU
tC & −1) = voR(j) −”H”VoK(
j+l) ”' VHt(J+2) ---Vou
t(2N-Q = "L" where +1811
and "°L" are the output logic levels of the comparators.

(2) V r(j) <Vt, J<V r(/-1
Vovtl −Vout2 −”
'-VoutC! −〇 −“H′vO+zt(
j) ”vfllllltCj+1)”
”'-vout(Z'-1) ”” ”L
”, and the only comparator whose output logic level changes is comparator j, and the output levels of the other comparators do not change.

Here, in current control circuit A, analog input voltage V
The value of IN is determined by, for example, a means described later, and the operating current of the comparator block 1 including the comparator j is increased, and the operating current of the other comparator blocks is controlled to be decreased.

Output logic level V. A comparator whose l1tK changes,
The only comparator required to operate at high speed is comparator j. Therefore, by providing the current control circuit A, the conversion speed as an AD converter does not change, and the AD
The operating 'F1 flow of the converter as a whole is reduced. That is, according to the present invention, power consumption can be reduced without sacrificing conversion speed.

In reality, the range of change in the analog input voltage is large and the output logic level may change across a plurality of comparators, so the number of comparators included in a comparator block is set to be plural as shown in the figure.

Furthermore, since the analog input voltage may change across comparator blocks, the current control circuit A is designed to be able to change the operating current of a plurality of comparator blocks. It's practical.

FIG. 3 is a diagram showing a specific configuration example of the current II m circuit A and a connection example with the comparator block in FIGS. 1 and 2. The configuration of the current control circuit A shown in FIG. 3 utilizes a parallel AD converter with a small number of bits. That is, its configuration is based on the reference voltage ■T? I,
The resistor string P2 (series resistor R+"RKya1") connected between vrL, the divided reference voltage obtained by this resistor string P2, and the analog input VIN
It consists of comparators C3, ~COK in which the comparator C0f=coK is introduced, an encoding circuit F for encoding the signal from the comparator C0f=coK, and a level shift G for level-shifting the signal from the encoding circuit F. .

Control signals S1 to sk, which are output signals of the current control circuit A, are applied to each companion node block shown in FIGS. 1 and 2.

By encoding in the same way as the parallel △D converter described above,
Depending on the analog human power VuJ, one of the outputs can be set to a high potential, and the remaining outputs are set to a low potential.

On the other hand, the comparator of a commonly used parallel AD converter has a circuit configuration as shown in Figure 4.
Operating current ■bids by changing the potential of vbias
can be changed. Therefore, by appropriately performing a level shift, it is possible to increase the operating current of a specific comparator block and reduce the operating current of other blocks in accordance with the analog human input VIN.

Since the current control circuit A is required to operate at high speed, the comparators C81 to COK used therein require a large operating current, but since the number of comparators is small, even if the operating current is increased, AD! There is little effect on the grinder as a whole.

To explain specifically, for example, assume that the operating current of one comparator is Io (for high-speed operation) and U-Io (for low-Q speed operation). Then, a 10-bit parallel type A
Assuming that 11 D converters are made, the current control circuit A at this time
The operating current of the comparators C6, ~Co in the section is set to 1
Assuming 0Io, the currents of all comparator sections flowing to the parallel AD converter are as follows.

(1) In the case of a conventional parallel AD converter This is a case where the current control circuit A is not provided and a high-speed operating current 1o is supplied to all comparators.

In this case, the total current of the comparator section is 1024
A current of Io flows.

(11) In the case of the parallel AD converter of the present invention, the third
If the number of comparators in current control circuit A in the figure is 8, the comparator block can be divided into 8 pieces, so 128Io +696-upper・I0+8・10・■.

雛297.610 As described above, if the number k of comparators in the current control circuit A is appropriately selected, the overall operating current can be lowered.

FIG. 5 is a diagram showing another specific example of the configuration of the current control circuit A and an example of connection with the comparator blocks in FIGS. 1 and 2. In the current control circuit A shown in FIG.
When Vr(j++)<VIIV-<Vr(j), only comparator block j operates with current 1o, and the other comparator blocks operate with 'Io. If the reference voltages of the comparators included in one comparator and Vr(i), Vr(A+l), etc. are selected appropriately, the ratio of the operating current of the comparator that requires high-speed operation and that of the comparator that does not need to be 2:1. It can be done. At this time, in the case of the conventional example, the sum of the currents of the comparator block is: (k-1>·I.

In the case of Figure 5, 2k, top, and I.

Therefore, by increasing k appropriately, it is possible to operate with approximately half the operating current.

In FIG. 1, the comparator blocks 1 to M are illustrated so that in addition to each comparator, the comparator blocks 1 to LM are also included in this block. However, moving the latches out of this comparator block has no effect on the operation of the present invention. Specification I
In R, the term "comparator block" refers to the concept of a block that includes a plurality of comparators, and the presence or absence of a latch does not matter.

C. Effects of the Present Invention As stated above, the present invention allows high-speed operation! Since the current control circuit controls the operating current of the required comparator to be large and the operating current of the unrequired comparator to be small, power consumption can be reduced without sacrificing the conversion speed of the parallel AD converter. It can be realized.

[Brief explanation of drawings]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention.
Figure 3 shows a specific configuration example of current control circuit A and a connection example with the comparator blocks in Figures 1 and 2. Figure 4 is a diagram showing the circuit configuration of a comparator of a commonly used parallel type △D converter.
FIG. 5 shows another specific configuration example of the current control circuit Δ, and FIG.
FIG. 6 is a diagram showing an example of connection with the comparator block in FIG. 2, and FIG. 6 is a diagram showing the configuration of a conventional parallel AD converter. PI, P2...Resistance string, R...Resistance, C1
~C2'-1, CQI = COY, - comparator,
1~M... Comparator block, 11~1M...
Latch, E...encoder, A...current control circuit,
F... Encoding circuit, G... Level shift. Figure 2 Figure 4 Vrt 7j lock input V/N

Claims (1)

[Claims] In a parallel AD converter using a plurality of differential amplifier type comparators that compare a reference voltage and an analog input voltage, the comparators are divided into a plurality of comparator blocks, and the analog input voltage is A parallel AD conversion characterized by comprising a current control circuit that increases the operating current of a comparator block to which a reference voltage of the same level as that voltage is inputted, and reduces the operating current of other comparator blocks. vessel.