JPS6268370A - Pseudo synchronizing signal generating circuit - Google Patents
Pseudo synchronizing signal generating circuitInfo
- Publication number
- JPS6268370A JPS6268370A JP60208514A JP20851485A JPS6268370A JP S6268370 A JPS6268370 A JP S6268370A JP 60208514 A JP60208514 A JP 60208514A JP 20851485 A JP20851485 A JP 20851485A JP S6268370 A JPS6268370 A JP S6268370A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- video signal
- synchronization
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
Description
【発明の詳細な説明】
3、ブを明の詳1111な説明
産業上の利用分野
本発明は、例えばビデオディスクプレー17のように、
記録媒体に記録された映e4I(tj号を再生して、テ
レビジョン受像機に適した信号に処i!I!−Jる回路
に用いられる、疑似同期信号発生回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION 3. Detailed explanation of the invention Field of industrial application The present invention is applicable to, for example, a video disc player 17,
This invention relates to a pseudo synchronization signal generation circuit used in a circuit that reproduces a video recorded on a recording medium and processes it into a signal suitable for a television receiver.
従来の技術
従来は、再生した映像信号に疑似同期信号を挿入するこ
となく、再生した映BI信号の同明信号を用いて映像信
号の処理を行なっていた。第3図は従来の映像信号処理
回路において再生した映像信号をクランプした波形であ
り、1す土中生ずるゴミ付きやビット欠落ヤRF回路の
特性により、映像信号にヒゲが発生している。再生した
映像信号を処理して画質の向上を図るとき、このヒゲに
より充分な画質の向上が図れないという問題や、同期信
号の先端に発生づるヒゲにより受vQ橢で誤動作すると
いう問題があった。2. Description of the Related Art Conventionally, a video signal has been processed using a synchronization signal of a reproduced video BI signal without inserting a pseudo synchronization signal into the reproduced video signal. FIG. 3 shows a waveform obtained by clamping a video signal reproduced by a conventional video signal processing circuit, and the video signal has whiskers due to dirt in the ground, missing bits, and characteristics of the RF circuit. When trying to improve the image quality by processing the reproduced video signal, there was a problem that the image quality could not be improved sufficiently due to this hair, and a problem that the hair that appeared at the tip of the synchronization signal caused a malfunction due to unreliable VQ error. .
発明が解決しようとする問題点
このように従来は、記録媒体から再生した映像信号の同
期の先端でヒゲが発生したり、同期のレベルが変化して
テレビジョン受像機や再生はに悪影響を与えたり、また
、映像信号を記録媒体から再生するとき生ずるゴミ付き
等の異常状態により同期区間以外の映i信号の輝度信号
にペデスタルレベルよりも小さいヒゲが発生し、再生機
の誤動作の原因となったり、画質面上の妨げとなる問題
がある。Problems to be Solved by the Invention As described above, in the past, hair loss occurred at the synchronization end of the video signal reproduced from the recording medium, and the synchronization level changed, which adversely affected the television receiver and playback. In addition, abnormal conditions such as dust that occur when playing back video signals from a recording medium may cause whiskers smaller than the pedestal level to appear in the brightness signal of the video i signal outside the synchronized period, which may cause malfunction of the playback device. There are also problems that may impede the image quality.
本発明は上記従来の問題点を解消するもので、簡q1な
構成で再生同期信号の代りに疑似同期信号を映像信号に
発生させ、また、同期区間以外の輝度信号のペデスタル
レベル以下に生ずるヒゲも取り除くことができ、かつ、
IC化に適する疑似同期信号発生回路を提供づることを
目的とする。The present invention solves the above-mentioned conventional problems, and uses a simple Q1 configuration to generate a pseudo synchronization signal in the video signal instead of the reproduction synchronization signal. can also be removed, and
The object of the present invention is to provide a pseudo synchronous signal generation circuit suitable for IC implementation.
問題点を解決するための手段
上記問題点を解決するため、本発明の疑似同期信号発生
回路は、映像11号をクランプするクランプ回路1段と
、このクランプ回路手段でクランプした映像信号のペデ
スタルレベル以下の信号をペデスタルレベルにクリップ
するクリップ回路手段と、前記クランプ回路手段でクラ
ンプされた映憬FJ月の同期信号区間を検出する同期検
出手段と、この同期検出手段により検出された同期信号
区間において前記クリップ回路手段でクリップした映像
信号に疑似同期信号を加算づる疑似同期信号加算回路手
段とを尚えた構成どしたものである。Means for Solving the Problems In order to solve the above problems, the pseudo synchronization signal generation circuit of the present invention includes one stage of clamp circuit for clamping video No. 11, and a pedestal level control of the video signal clamped by this clamp circuit means. clipping circuit means for clipping the following signals to the pedestal level; synchronization detection means for detecting a synchronization signal section of the video FJ month clamped by the clamp circuit means; and a synchronization signal section detected by the synchronization detection means. The present invention further includes a pseudo synchronization signal adding circuit means for adding a pseudo synchronization signal to the video signal clipped by the clipping circuit means.
作用
上記構成によれば、再生した映像信号の同期信号の代り
に、疑似同期信号を映像信号に発生させ、また、同期信
号区間以外の輝度信号のべfスタルレベル以下をクラン
プすることにより、同期の先端のヒゲを取り除き、同期
のレベルを一定にすることができ、かつ、再生した信号
のペデスタルレベル以下に生ずるヒゲも取り除くことが
できるため、画質の向トを図ることができる。Effects According to the above configuration, a pseudo synchronization signal is generated in the video signal instead of the synchronization signal of the reproduced video signal, and the synchronization is performed by clamping the luminance signal below the best level outside the synchronization signal section. The synchronization level can be kept constant by removing whiskers at the tip of the signal, and it is also possible to remove whiskers that occur below the pedestal level of the reproduced signal, so it is possible to improve the image quality.
実施例
以下、本発明の一実施例を第1図〜第2図にIJづいて
説明する。EXAMPLE Hereinafter, an example of the present invention will be explained with reference to IJ with reference to FIGS. 1 and 2.
第1図は本発明の一実施例におGJる疑似同期信号発生
回路の回路ブロック図で、1はへ力端了、2はクランプ
回路、3はクリップ回路、4はペデスタルレベル用の基
準電圧源、5は同期検出回路、6は同期検出レベル用の
基準電圧源、7は疑似同期18号加算回路、8は疑似同
期信号レベル用の基準電圧源、9は出力端子である。FIG. 1 is a circuit block diagram of a pseudo synchronous signal generation circuit according to an embodiment of the present invention, in which 1 is a power terminal, 2 is a clamp circuit, 3 is a clip circuit, and 4 is a reference voltage for pedestal level. 5 is a synchronization detection circuit, 6 is a reference voltage source for the synchronization detection level, 7 is a pseudo synchronization No. 18 addition circuit, 8 is a reference voltage source for the pseudo synchronization signal level, and 9 is an output terminal.
次に動作について第2図を参照しながら説明する。第2
図(a)に示す波形は、記録媒体から再生した映像信号
を示している。この再生した映像信号は、直流成分が復
元されていないため、クランプ回路2を通して、直流成
分を復元する。第2図(b)に直流成分を復元した映像
信号を示している。Next, the operation will be explained with reference to FIG. Second
The waveform shown in Figure (a) shows a video signal reproduced from a recording medium. Since the DC component of this reproduced video signal has not been restored, the DC component is restored through the clamp circuit 2. FIG. 2(b) shows a video signal with the DC component restored.
このクランプされた映像信号は、クリップ回路3と同期
検出回路5とに入力される。クリップ回路3は、映像信
号と基準電圧源4からのペデスタルレベルとを比較して
、映像信号のペデスタルレベル以下の信号をクリップす
る回路である。第2図(C)はクリップした映ゆ信号を
示している。一方、同期検出回路5は、基準電圧源6か
らの同期検出レベルと映像信号とを比較して、映像信号
の同期信号を検出し、同期信号区間だけ疑似同期信号側
枠回路7に制御信号を出力する。第2図(b)に映像(
H号と同期検出レベルとの関係を、第2図(d)に同期
検出回路5の出力を各々示している。疑似同期信号側枠
回路7は、映像信号をペデスタルレベルでクリップする
クリップ回路3の出力に、同期検出回路5で検出した同
期区間において、一定振幅の疑似同期イエ号レベルの疑
似同期信号を側御する。第2図(e)に疑似同期45号
を加粋した映像信号を示している。かくしで、再生した
映像信号の同期信号の代りに同明信す区間に一定振幅の
疑似回期信号を側御した映像信号が出力される。This clamped video signal is input to a clip circuit 3 and a synchronization detection circuit 5. The clipping circuit 3 is a circuit that compares the video signal with a pedestal level from the reference voltage source 4 and clips a signal that is lower than the pedestal level of the video signal. FIG. 2(C) shows the clipped video signal. On the other hand, the synchronization detection circuit 5 compares the synchronization detection level from the reference voltage source 6 with the video signal, detects the synchronization signal of the video signal, and sends a control signal to the pseudo synchronization signal side frame circuit 7 only during the synchronization signal period. Output. Figure 2(b) shows the image (
The relationship between the H number and the synchronization detection level is shown in FIG. 2(d) for the output of the synchronization detection circuit 5. The pseudo synchronization signal side frame circuit 7 side controls a pseudo synchronization signal at a pseudo synchronization signal level with a constant amplitude in the synchronization period detected by the synchronization detection circuit 5 to the output of the clipping circuit 3 that clips the video signal at the pedestal level. do. FIG. 2(e) shows a video signal with pseudo synchronization No. 45 added. In this way, instead of the synchronizing signal of the reproduced video signal, a video signal in which a pseudo-periodic signal of constant amplitude is controlled in the same period is output.
このように、再生した映@信号を用いて映像信号のペデ
スタルレベル以下の信号レベルをクリップするとともに
、同期信号区間には一定振幅の疑似同期信号を加えて出
力している。その結果、同期の先端に発生するヒゲや同
l!ll信号の振幅の不ぞろいがなくなり、また、ペデ
スタルレベル以下のヒゲも取り除けるため、画質の向−
Lが図れる利点を有するとともに、容易な回路構成で実
現て゛さる疑似同期信号発生回路となっている。In this way, the reproduced video @ signal is used to clip the signal level below the pedestal level of the video signal, and a pseudo synchronization signal of constant amplitude is added to the synchronization signal section and output. As a result, the whiskers that occur at the tip of the synchronization and the same l! This eliminates unevenness in the amplitude of the ll signal and removes whiskers below the pedestal level, improving image quality.
This pseudo synchronous signal generating circuit has the advantage of being able to reduce the number of L and can be realized with a simple circuit configuration.
発明の効果
以上述べた如く本発明によれば、簡単な回路構成により
、再生した映像185]の同期の先端に発生するヒゲや
同期信号の振幅の不ぞろいをなくづことができ、また、
再生した映像信号のベデスクルレベル以下に生ずるヒゲ
も取り除くことができるため、画質の向上を図ることが
できる。Effects of the Invention As described above, according to the present invention, with a simple circuit configuration, it is possible to eliminate whiskers that occur at the synchronization end of the reproduced video 185] and unevenness in the amplitude of the synchronization signal.
Since it is also possible to remove whiskers that occur below the Bedesque level of the reproduced video signal, it is possible to improve the image quality.
第1図は本発明の一実施例に53ける疑似開明イ3号発
生回路の回路ブロック図、第2図は第1図に示す回路の
各部信号波形図、第3図は従来の映像伝号処理回路にJ
31ブる再生映像悟りをクランプした状態の波形図であ
る。Fig. 1 is a circuit block diagram of a pseudo-Kaimei No. 3 generation circuit in 53 according to an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part of the circuit shown in Fig. 1, and Fig. 3 is a conventional video transmission signal. J to the processing circuit
31 is a waveform diagram of a state in which the reproduced video image enlightenment is clamped; FIG.
Claims (1)
クランプ回路手段でクランプした映像信号のペデスタル
レベル以下の信号をペデスタルレベルにクリップするク
リップ回路手段と、前記クランプ回路手段でクランプさ
れた映像信号の同期信号区間を検出する周期検出手段と
、この同期検出手段により検出された同期信号区間にお
いて前記クリップ回路手段でクリップした映像信号に疑
似同期信号を加算する疑似同期信号加算回路手段とを備
えた疑似同期信号発生回路。1. Synchronization of a clamp circuit means for clamping a video signal, a clip circuit means for clipping a signal below the pedestal level of the video signal clamped by the clamp circuit means to the pedestal level, and a video signal clamped by the clamp circuit means. Pseudo synchronization comprising period detection means for detecting a signal section, and pseudo synchronization signal addition circuit means for adding a pseudo synchronization signal to the video signal clipped by the clipping circuit means in the synchronization signal section detected by the synchronization detection means. Signal generation circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60208514A JPH0666937B2 (en) | 1985-09-19 | 1985-09-19 | Pseudo sync signal generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60208514A JPH0666937B2 (en) | 1985-09-19 | 1985-09-19 | Pseudo sync signal generator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6268370A true JPS6268370A (en) | 1987-03-28 |
JPH0666937B2 JPH0666937B2 (en) | 1994-08-24 |
Family
ID=16557424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60208514A Expired - Lifetime JPH0666937B2 (en) | 1985-09-19 | 1985-09-19 | Pseudo sync signal generator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0666937B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023305A (en) * | 1996-06-10 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Primary color video signal output circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54100220A (en) * | 1978-01-25 | 1979-08-07 | Hitachi Ltd | Synchronous signal isolator circuit |
JPS55120274A (en) * | 1979-03-09 | 1980-09-16 | Toshiba Corp | Video recording and reproducing system |
JPS6037983U (en) * | 1983-08-22 | 1985-03-15 | ソニー株式会社 | Synchronous signal waveform shaping circuit |
-
1985
- 1985-09-19 JP JP60208514A patent/JPH0666937B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54100220A (en) * | 1978-01-25 | 1979-08-07 | Hitachi Ltd | Synchronous signal isolator circuit |
JPS55120274A (en) * | 1979-03-09 | 1980-09-16 | Toshiba Corp | Video recording and reproducing system |
JPS6037983U (en) * | 1983-08-22 | 1985-03-15 | ソニー株式会社 | Synchronous signal waveform shaping circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023305A (en) * | 1996-06-10 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Primary color video signal output circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0666937B2 (en) | 1994-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6268370A (en) | Pseudo synchronizing signal generating circuit | |
JPH04361493A (en) | Video signal reproduction device | |
KR0146498B1 (en) | Multi-color signal group delay circuit | |
EP0479135B1 (en) | Image signal processing device | |
JP2550734B2 (en) | Video signal clamp device | |
JPH0453066A (en) | Reproducing device | |
JPH0213514B2 (en) | ||
JP2775801B2 (en) | Video signal processing circuit | |
JP2979556B2 (en) | No signal detection device | |
JPH09121323A (en) | Video signal processor | |
KR900009753Y1 (en) | Noise signal reduction circuit in case of variable speed reproduction for video cassette recorder | |
EP0492462B1 (en) | Waveform detecting circuit | |
JP2539582B2 (en) | Video / audio signal recording apparatus, reproducing apparatus, and recording / reproducing apparatus | |
JP2508819B2 (en) | Video signal circuit | |
JPS6397074A (en) | Video signal reproducing device | |
JPS59167801A (en) | Device for recording or recording and reproducing video signal | |
JPH04311881A (en) | Magnetic recording/reproducing device | |
JPH0472978A (en) | Video incorporated type camera | |
JPH07264540A (en) | Magnetic recording and reproducing device | |
JPS6083472A (en) | Regenerating method of direct current potential of video signal | |
JPH0319578A (en) | Video signal processing unit | |
JPH0342557B2 (en) | ||
JPH04372771A (en) | Emphasis correcting circuit | |
JPS63182983A (en) | Dropout compensator | |
JPS6267991A (en) | Magnetic recording and reproducing device |