JPS6267836A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the bonding property of high melting point metallic film or metallic silicide film and other conductive film or insulating film while preventing them from being peeled off by a method wherein the impurity concentration of high melting point metallic film or metallic silicide film is lowered. CONSTITUTION:An insulating film 9B with thickness of around 400Angstrom is formed on the upper part of a high melting point metallic silicide film 6B so that only around 10% of impurity with high concentration around 10<16>atoms/cm<2> may be led into said metallic silicide film 6B. Moreover when the insulating film 9B with higher thickness of around 1,000Angstrom is formed on the upper part of high melting point metallic silicide film 6B, almost no impurity with high concentration around 10<16>atoms/cm<2> is led into said metallic silicide film 6B. Through these procedures, the impurity concentration in a high melting point metallic silicide film 6B can be lowered so that the bonding property of high melting point metallic silicide film 6B and other conductive film or insulating film may be improved while preventing them from being peeled off.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device having a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film containing the same. It is related to effective technology.

[Background Art] A semiconductor integrated circuit device having a MISFET uses a composite film (
Polycide film) is used as the gate electrode material. This is because the specific resistance value is smaller than that of a polycrystalline silicon film, so the signal transmission speed can be increased.

This type of MISFET can be formed in a first manufacturing process.

First, a gate electrode of a polycide film is formed on the main surface of a semiconductor substrate via a gate insulating film. Thereafter, using the gate electrode as a mask for impurity introduction, a high concentration impurity of the opposite conductivity type is introduced into the main surface of the semiconductor substrate on the side thereof. A MIS FET is completed by stretching and diffusing the introduced impurities to form a source region or a drain region.

However, as a result of experiments and studies on this technology, the present inventor found that the following problems occurred.

When impurities are introduced at a high concentration into the high melting point metal silicide film of the polycide film, peeling occurs at the interface with the insulating film (eg, silicon oxide film) covering the polycide film. In addition, static random access memory (hereinafter referred to as SR)
A similar phenomenon occurs with AM. That is, peeling occurs at the interface between the gate electrode (polycide film) of the MISFET for driving the memory cell and the polycrystalline silicon film or insulating film constituting the high resistance load element. For this reason, the dielectric breakdown voltage deteriorates due to peeling between the polycide film and the insulating film, and conduction failure occurs due to peeling between the polycide film and the polycrystalline silicon film, resulting in a decrease in electrical reliability.

The present inventor has discovered that 101' in the high melting point metal silicide film.
It has been found that when impurities are contained at a high concentration of about [al=oms/Cm2] or higher, the above-mentioned phenomenon occurs.

Further, the present inventor predicts that in a MISFET in which a single layer of a high melting point metal film or a high melting point metal silicide film is used as a gate electrode, there is a possibility that the gate electrode and the gate insulating film may separate.

Regarding polycide films, for example, see Nikkei McGraw-Hill Special Issue R Micro Devices, August 2, 1983.
Published on the 2nd, described on pages 118 to 120.

[Object of the Invention] An object of the present invention is to provide a technology capable of improving electrical reliability in a semiconductor integrated circuit device having a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film containing the same. Our goal is to provide the following.

Another object of the present invention is to provide a technique capable of preventing peeling between a high melting point metal film or a high melting point metal silicide film and other conductive films or insulating films.

Another object of the present invention is to provide a technique that can achieve the above object without increasing the number of manufacturing steps.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

That is, in a semiconductor integrated circuit device having a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film containing the same, the impurity concentration of the high melting point metal film or high melting point metal silicide film is made low.

This improves the adhesion between the high melting point metal film or the high melting point metal silicide film and other conductive films or insulating films, and prevents peeling, thereby improving electrical reliability.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to an SRAM.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example] A memory cell of an SRAM which is an example of the present invention is shown in a plan view in FIG. In order to make the configuration of this embodiment easier to understand, the figure does not show any insulating films other than the field insulating film provided between each conductive layer.

In FIGS. 1 and 2, reference numeral 1 indicates a diagonal type semiconductor substrate made of single crystal silicon, and reference numeral 2 indicates a p-type well region.

3 is a field insulating film, and 4 is a p-type channel stopper region. Field insulating film 3 and channel stopper region 4 are provided on the main surface of well region 2 and are configured to electrically isolate semiconductor elements.

The memory cell of the SRAM includes a flip-flop circuit composed of a high resistance load element RrpR2 and driving MI5FETs Qdr and Qd2, and a transfer MI connected between the pair of input/output terminals and the data lines DL, DL. SF
It is composed of E T Q s t and Q 32.

The MISFETQd+, Qdz, QSI, Qs
2 is mainly a well region 2. Gate insulating film 5, gate electrode 6. A pair of n-type semiconductor regions 7 and a pair of rl”
It is made up of a semiconductor region 10 of a type.

The gate electrode 6 is made of polycrystalline silicon [6A and refractory metal silicide (MoSi2.T) provided thereon.
aSi2. It is composed of a composite WA (polycide film) consisting of a Ti5iz, WSiz) film 6B. Polycrystalline siliconllll5A contains an impurity (A) that reduces the resistance value.
s, P or B) have been introduced. The gate electrode 6 is composed of a single layer of a high melting point metal (Mo, Ta, Ti, W) film, a high melting point metal silicide film, or a composite film in which a high melting point metal film is provided on a polycrystalline silicon film. It's okay.

In addition, a word line (W) is made of the same conductive material as the gate electrode 6.
L) 6 and reference voltage (e.g. circuit ground voltage 0 [Vl)
A wiring (Vss) 6 is configured.

The extended part of the gate electrode 6 and the reference voltage wiring 6 are
Through the connection hole 5A provided in the gate insulating film 5, it is electrically connected to a predetermined semiconductor region 10, so-called direct contact.

The semiconductor region 7 is M I S F E T Q 9
r+Q! + 2 +Qdt is provided between the channel forming region of Qd2 and the semiconductor region 10, and constitutes a part of the source region or the drain region.

The semiconductor region 7 is so-called LDD (Light,
MISFETQs with 1ydn opcd drain) structure
+, QS2, Qd+.

Q　d　2.

Semiconductor region 10 is adapted to constitute a substantial source or drain region.

Reference numeral 8 denotes an impurity introduction mask provided on the side of the gate electrode 6, and is used to form the semiconductor region 10.

9A is an insulating film provided on the upper part of the semiconductor region 10, 9B
is at least the high melting point metal silicide film 6 of the gate electrode 6
This is an insulating film provided on top of B.

The insulating film 9A is used as a mask for introducing impurities to form the semiconductor region 10! It is configured to prevent contamination of metals and the like and to alleviate damage to the main surface of the semiconductor region 10. The insulating film 9A has a thickness that allows impurities to actively pass through.

The insulating film 9B is used as a mask for introducing impurities forming the semiconductor region 10, and is used as a mask for introducing impurities forming the semiconductor region 10, and is used as a high-melting point metal silicide film 6B for the gate electrode, word line (WL), base voltage wiring, and line (Vss) Q. It is configured to suppress introduction of impurities into the material.

According to the inventor's experiments and studies, it has been found that impurities (As, P or B) introduced into the high melting point metal silicide film 6B.
) is desirably less than about 10"[aL;ou+s/e+n'.

13A is a high resistance load element R8, R2, 13B is ffi!
Wiring for voltage (e.g. circuit operating voltage 5 [V]) V C
It is c. The high resistance load element 13A connects the MISFETQs+ + (
112 semiconductor regions 10 and MISFETQdL,Q
It is configured to be electrically connected to the gate electrode 6 of dz and to extend over the insulating film 11 . Power supply voltage wiring 1
3B is configured integrally with the high resistance load element 13A and is configured to extend above the insulating film 11.

The high resistance load element 13A is made of, for example, a polycrystalline silicon film (in the region surrounded by the dotted line marked 13A in FIG. 1) into which impurities (As or P) that reduce the resistance value are not introduced. ing. The power supply voltage wiring 13B is made of, for example, a polycrystalline silicon film into which the impurity is introduced.

16 is data lines DL, DL and an insulating film 9A.

MIS F through the connection hole 15 provided in 11.14.
Semiconductor region 10 of E T Q s 1 + Q S 2
It is configured to be electrically connected to and extend over the insulating film 14. The data X1Ax6 is composed of an aluminum film, an aluminum film containing a predetermined additive, or the like.

In this way, by forming the high melting point metal silicide film 6B such as the gate electrode 6 made of a polycide film with a low impurity concentration, the high melting point metal silicide film 6B in the connection hole 12 portion and the high resistance load element 13A (multiple Since the adhesive force with the crystalline silicon film can be increased, peeling thereof can be prevented and conduction defects can be eliminated.

In addition, by providing the insulating film 9B made of the high melting point metal silicide film 6B with a low impurity concentration or covering it, the insulating film (for example, a silicon oxide film formed by high temperature and low pressure CVD technology) 11 and Since it is possible to increase the adhesive strength of the materials, it is possible to prevent their peeling and suppress deterioration of dielectric strength voltage.

Next, the manufacturing method of the fifth embodiment will be briefly explained.

A method for manufacturing an SRAM memory cell according to an embodiment of the present invention is shown in cross-sectional views at each manufacturing step in FIGS. 3 to 7.

First, a P-type well region 2 is formed in an n-type semiconductor substrate 1 made of single crystal silicon.

Thereafter, a field insulating film 3 and a P-type channel stopper region 4 are formed on the main surface of the well region 2.

Then, as shown in FIG. 3, a gate insulating film 5 is formed on the main surface of the well region 2 in the semiconductor element formation region. As the gate insulating film 5, a silicon oxide film formed by thermal oxidation technology is used.

After the step of forming the gate insulating film S shown in FIG. 3, the gate insulating film 5 in the direct contact portion is removed to form a connection hole 5A.

Thereafter, a gate electrode 6 and a word line (WL ) 6 and reference voltage wiring (Vss) 6 are formed. These gate electrodes 6 etc.
It is formed of a polycrystalline silicon film 6A formed by CVD technology and doped with impurities to reduce the resistance value, and a polycide film of high melting point metal silicide 116B formed by sputtering technology. In addition, in the directly contacted portion, that is, the main surface of the well region 2 connected to the polycrystalline silicon film 6A through the connection hole 5A, the impurity introduced into the polycrystalline silicon film 6A is diffused, and the n0 type is formed. A semiconductor region 10 is formed.

Then, as shown in FIG. 4, an n-type semiconductor region 7 is formed on the main surface of the well region 2 under the gate insulating film S. The semiconductor region 7 mainly consists of a field insulating film 3. The gate electrode 6 and the reference voltage wiring 6 are used as a mask for impurity introduction, and are formed in self-alignment with them. The semiconductor region 7 is, for example, ~10'' [a-s/c
It can be formed by introducing P with an impurity concentration of about m''1 by ion implantation technology and performing stretching and diffusion.

In the step of forming this semiconductor region 7, impurities are introduced into the high melting point metal silicide film 6B.
Since the concentration is not high and is not high, the adhesion between the high melting point metal silicide film 6B and other conductive films or insulating films will not deteriorate and they will not peel off.

Further, the high melting point metal silicide film 6B is well bonded to the polycrystalline silicon film 6A below it. This is because, in a state where no impurity is introduced into the high melting point metal silicide film 6B, their interfaces are mixed to some extent during or after the formation process.

After the step of forming the semiconductor region 7 shown in FIG.
As shown in the figure, an impurity introduction mask 8 is mainly formed on the side of the gate electrode 6. The impurity introduction mask 8 is formed by, for example, performing anisotropic etching such as single-reactive ion etching on a silicon oxide film formed by CVD technology.

In the step of forming this impurity introduction mask 8, the exposed gate insulating film 5 is removed.

After the step of forming the impurity introduction mask 8 shown in FIG. 5, as shown in FIG. An insulating film 9A is formed on the main surface.

This insulating film 9A.

It is used as a mask for introducing impurities to form the source region or the drain region, and is designed to prevent heavy metal contamination and to alleviate damage to the main surface of the semiconductor region 7. The insulating film 9A is, for example, a silicon oxide film formed by performing oxidation treatment for about 60 [min] in an oxygen gas atmosphere at a temperature of about 900 ['C]. The insulating film 9A is 2
It is formed with a film thickness of about 00 [λ]. When the insulating film 9A is formed under such oxidation conditions, the insulating film 9B made of a silicon oxide film is also formed on the high melting point metal silicide film 6B in the same manufacturing process. The insulating film 9B has a thickness of 400 [λ]
The thickness of the insulating film 9A can be greater than that of the insulating film 9A. The insulating film 9B is configured to actively suppress introduction of impurities into the high melting point metal silicide film 6B.

Further, the insulating film 9A may be formed by performing an oxidation treatment of about 20 [n+in1] in a steam atmosphere at a temperature of about 800 [° C.]. In this case, the insulating film 9A is 10
The insulating film 9B is formed with a film thickness of about 0 [λ], and the insulating film 9B is 1000
It can be formed with a film thickness of about [ON].

In this way, by forming the insulating film 9B with a thicker thickness in the process of forming the insulating film 9A, the insulating film 9B
Since the step of forming is no longer necessary, the number of manufacturing steps can be reduced.

After the step of forming the insulating films 9A and 9B shown in FIG.
As shown in FIG. 7, an n-type semiconductor region 10 is formed on the main surface of the well region 2 under the insulating film 9A. The semiconductor region 10 can be formed by introducing an impurity (for example, AS) at a high concentration of about 10"[atoms/ra"] or higher using an ion implantation technique and performing stretching diffusion. The semiconductor region 10 is for forming a source region or a drain region.

In order to form the semiconductor region 10 in self-alignment with the gate electrode 6 and the like, a polycide film such as the gate electrode 6 is used as a mask for impurity introduction. Therefore, impurities forming the semiconductor region 10 are also introduced into the high melting point metal silicide film 6B.

However, on the top of the high melting point metal silicide film 6B,
Since the insulating film 9B is formed with a thickness of about 400 [λ]], among the impurities at a high concentration of about 10" [at, oms/am"], 10% of the impurity is contained in the high melting point metal silicide film 6B. It will be stopped by introducing about [%]]. Further, on the top of the high melting point metal silicide film 6B, 1000
When the insulating film 9B is formed as thick as [ON], 1
Of the impurities at a high concentration of about 0'' [a+ss/c12], almost no impurities are introduced into the high melting point metal silicide film 6B.

In this way, by lowering the impurity concentration of the high melting point metal silicide film 6B, as described above, the adhesion between the high melting point metal silicide v6B and other conductive films or insulating films is improved, and their peeling is improved. can be prevented.

In the step of forming the semiconductor region 10, the transfer M
ISFETQs+, Qs2 and driving MI SFE
TQd r and Qd2 are almost completed.

After the step of forming the semiconductor region 10 shown in FIG. 7, the insulating film 11, the connection hole 12. A high resistance load element 13A, a power supply voltage wiring (Vcc) 13B, an insulating film 14, a connection hole 15, and a data line (DL) 16 are formed. By performing these series of manufacturing steps, the S shown in FIG. 1 and FIG.
The RAM memory cell is completed.

In the above embodiments, the present invention was applied to an SRAM in which memory cells were configured with MISFETs having an LDD structure, but the present invention is also applicable to SRAMs in which memory cells were configured by MISFETs in a so-called single-drain structure or double-drain structure. You may. In this case, the semiconductor region 10 may be formed using an etching mask for patterning the gate electrode 6 and the like instead of the insulating film 9B. For example, a photoresist film is used as the etching mask.

Further, in the embodiments described above, the present invention is applied to an SRAM as a semiconductor integrated circuit device having a MISFET, but the present invention may be applied to a semiconductor integrated circuit device having other MISFETs. Specifically, the present invention can be applied to a dynamic random access memory, a mask ROM, and an ultraviolet erasable or electrically erasable rewritable ROM.

Furthermore, the present invention can also be applied to a semiconductor integrated circuit device having a bipolar transistor. In this case, the impurity concentration in the high melting point metal film or the high melting point metal silicide film may be lower than that in the emitter region.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) In a semiconductor integrated circuit device having a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film containing the same, lowering the impurity concentration of the high melting point metal film or high melting point metal silicide film. This makes it possible to improve the adhesion between the high melting point metal film or the high melting point metal silicide film and other conductive films or insulating films, thereby preventing their peeling.

(2) According to the above (1), it is possible to suppress poor conduction and deterioration of dielectric strength voltage, and improve the electrical reliability of the semiconductor integrated circuit device.

(3) In a semiconductor integrated circuit device equipped with a MISFET having a single layer of a high-melting point metal film or a high-melting point metal silicide film, or a composite film containing the same, introducing a first impurity to form a source region or a drain region of the MISFET. In the process of forming masks for use.

A step of forming the second impurity introduction mask by forming a second impurity introduction mask to lower the impurity concentration on the high melting point metal film or the high melting point metal silicide film is required. Therefore, the number of manufacturing steps can be reduced.

The invention made by the present inventor has been specifically explained in the above embodiments, but the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a plan view of an SRAM memory cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. FIG. 3 to FIG. 7 show an SRAM which is an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the memory cell in each manufacturing process. In the figure, 2... Well region, 5... Gate insulating film, 6
...Gate electrode, word! (WL), reference voltage wiring (Vss), 6A...polycrystalline silicon film, 6B...
- High melting point metal silicide film, 7.10... semiconductor region. 9A, 9B... Insulating film, 12... Connection hole, 13A,
R... High resistance load element, 13 B * V c c...
- Wiring for power supply voltage, Q...MISFET. 2, 2,

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film containing the same, wherein the high melting point metal film or high melting point metal silicide film comprises:
A semiconductor integrated circuit device comprising a low impurity concentration. 2. In a semiconductor integrated circuit device having a MISFET, the impurity concentration of the high melting point metal film or the high melting point metal silicide film is lower than that of the source region or the drain region. Claim 1
2. The semiconductor integrated circuit device described in 2. 3. A patent claim characterized in that, in a semiconductor integrated circuit device having a bipolar transistor, the impurity concentration of the high melting point metal film or the high melting point metal silicide film is lower than that of the emitter region. The semiconductor integrated circuit device according to scope 1. 4. The high melting point metal film or high melting point metal silicide film is
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured to have an impurity concentration of approximately 10^1^6 [atoms/cm^2] or less. 5. A method for manufacturing a semiconductor integrated circuit device having a MISFET, which comprises: on the main surface of the first semiconductor region of the first conductivity type;
A step of forming a gate electrode of a single layer of a high melting point metal film or a high melting point metal silicide film or a composite film containing the same through a gate insulating film, and at least a high melting point metal film or a high melting point metal silicide film of the gate electrode. forming a thick first insulating film on the top of the first insulating film, and forming a thin second insulating film on the main surface of the first semiconductor region on the side of the gate electrode; using the insulating film as a mask for impurity introduction, and introducing an impurity of the second conductivity type into the main surface of the first semiconductor region through the first insulating film to form a source region or a drain region. A method for manufacturing a semiconductor integrated circuit device, characterized in that: 6. According to claim 5, the step of forming the first insulating film and the second insulating film is a step of forming a silicon oxide film formed by thermal oxidation technology. A method for manufacturing a semiconductor integrated circuit device.