JPS6266367A - Main memory control system - Google Patents

Abstract

PURPOSE:To prevent a processor which has a large access throughput from decreasing in access throughput by attaining access having continuous addresses in the decreasing order of the addresses by either a processor which has a smaller throughput than any other device or that which has a larger throughput than any other device. CONSTITUTION:For example, the access throughput of a load store pipeline that an extended storage device (EMU) has is 4 elements/1tau (tau: cycle time) and access is attained at 4 elements/4tau so as to improve the access efficiency. Then, when logical storage numbers of a main memory device having continuous addresses are accessed, the access order of the processor which has the smaller throughput than any other device or larger throughput than any other device is reversed. For example, vector access is attained in the increasing order of addresses and EMU access is in the decreasing order in a figure 1.

Description

[Detailed Description of the Invention] [Summary] In an information processing system in which a plurality of processing devices with different access throughputs to a main storage device are connected, one of the processing devices has a smaller access throughput than the other devices,
The system is configured so that successive addresses are accessed by one of the processing devices with a larger access throughput than the other device in descending order of address, so that the access of the processing device with the larger access throughput is It is possible to prevent throughput from decreasing.

[Industrial Application Field] The present invention relates to controlling access to a main storage device by a plurality of processing devices, and particularly relates to controlling access to a main storage device by a plurality of processing devices having different throughputs.

[Prior Art] In a computer system in which multiple processing units with different throughputs to the main memory are connected, when the multiple processing units simultaneously access the main memory for consecutive addresses, the throughput is large. There is a problem in that the throughput of the processing device becomes the same as that of a processing device with a lower throughput.

FIG. 3 is a diagram showing an example of a system configuration for explaining this problem.

In Figure 3, MSU is the main memory, MCU is the main storage
A TV control device, VU vector unit, SU a scalar unit, CHP a channel processor, ESU an extended storage device, and EMU an extended storage control device.

Hector Unisoto (VU) has 4 elements /
1τ (τ is the cycle time).

It is assumed that the access throughput of the rotor store pipeline of the extended storage controller (EMU) is 1 element/1τ. However, in order to improve the access efficiency, access is performed at 4 times 1 to /4τ.

Therefore, the Vector Uniso I-(VU) has four times the throughput compared to the Extended Storage Unit (EMU).

4 and 5, the vertical axis represents time and the horizontal axis represents the logical storage number (hereinafter abbreviated as LS) of the main storage device, and the access from VU (hereinafter referred to as LS) , ■U access) and extended storage controller (EMU).
) (hereinafter referred to as EMtJ access).

In the figure, the line that extends vertically when the LS is accessed is due to the LS busy time, during which the L
Other access to S is prohibited.

Figure 4 shows the synchronization between VU access and EMU access.
A case is shown in which the access throughput of the VU does not decrease because there is no contention for the LS.

In FIG. 5, due to the LS busy time due to EMU access, VU access is forced to wait until LS busy is turned off. For this reason, the access throughput of the VU decreases and becomes the same as the throughput of the EMU.

[Problems to be Solved by the Invention] As explained above, according to the conventional method, the throughput of the processing device with higher throughput decreases and becomes the same as the throughput of the processing device with smaller throughput. There were some problems when it came to this.

The present invention aims to provide a new main memory control method that solves these problems.

[Means for Solving the Problems] FIG. 1 is an access state diagram showing the principle of the main memory control method of the present invention.

In order to access LSs of consecutive addresses, it is normal to access them in order from the youngest address to the largest address, that is, in ascending order of addresses, or in the present invention, processing with a smaller throughput than others This conversion is performed so that the access order of either the processing device or the processing device whose throughput is larger than the other is reversed, that is, it is in descending order.

In FIG. 1, VU access is accessed in ascending order of addresses, whereas EMU access is accessed in descending order of addresses.

As a result, even if VU access and EMU access temporarily cause LS busy contention, it is within the LS busy time, and throughput is guaranteed.

[Effects] By adopting the above configuration, when multiple processing devices simultaneously access consecutive addresses, the throughput of the processing device with higher throughput decreases, and the throughput of the processing device with lower throughput decreases. This solves the problem that the throughput becomes the same as the throughput.

This makes it possible to improve the overall processing performance of the system.

[Example] The present invention will be explained in more detail with reference to an example shown in FIG.

The effect is the same whether the present invention is applied to EMU access with a small throughput or to ■U access with a large throughput.
The case where it is applied to access will be explained.

FIG. 2 shows an EMU access request address generation circuit according to an embodiment of the present invention, and is a circuit that generates descending addresses for EMU access.

When the extended storage control unit (EMU) issues a main memory access, the load
An operation code (Opc) indicating a store, a start address (SA), the number of elements (EL), etc. are given.

These are controlled by control signals inside the EMU such as OPC register (OPC-12EG) 1, SA register (SA
-REG) 2 and EL register (EL-REG) 3.

An example of operation when the start address (SA) of the EMU is 10000, the number of elements (EL) is 256 elements, and the operation code (OPC) is "5TORE" is as follows. In this embodiment, addresses are assigned in byte units, one element is 8 bytes, and four elements (that is, 32 bytes) are read/written in one access.

(1) OPCL/Jister (OPC-1'1EG) 1
d “5TORE” code, SA-REG 7, evening (SA-REG) 2 d “1000”
0” (hexadecimal), EL register (EL-REG) 3 d “100”
(hexadecimal), is set.

(2) SAlzji, Z, Yu (SA-REG) The first address (SA) of the two characters and the EL register (EL-R
EG) In the end address calculation circuit 4, the end address "SA0EL" is calculated based on the number of elements (EL).
*8” is calculated, and from this the subtractor 6 calculates “20”.
The result of subtracting (hexadecimal) is the RA register (RA-RE
G) is set to 7.

(3) EL subtraction register (EL-DEC-REG) 9
"10" from EL register (EL-REG) 3
0'' (hexadecimal) is set and the request control circuit (REQ
-CTL) 11 sends out a REQ valid signal and also sends out the request address placed in the request address register (RA-RUG) 7.

(4) When the REQ valid signal is output, the selector (SE
L) 5 switches, RA-REG 7→SEL
5 - The path of subtractor 6 is selected and subtracted by 20'' (hex).

(5) Similarly, selector (S'EL) 8 switches, EL-DEC-REG 9 → (-4) register 10
→ SEL 8 → EL-DEC-REG The route 9 is selected and subtracted by 4.

(6) Repeat this operation until EL-DEC-REG 9 becomes "0".

[Effects of the Invention] As explained above, according to the present invention, even when multiple processing devices with different access throughputs access consecutive addresses in the main memory simultaneously, the throughput of the processing device with the higher throughput can be prevented from decreasing. This can be avoided, and the effect of contributing to improving data processing efficiency is extremely large.

[Brief explanation of drawings]

Fig. 1 is an access state diagram showing the principle of the present invention, Fig. 2 is a block diagram of an access request address generation circuit in an embodiment of the present invention, Fig. 3 is a system configuration diagram, and Fig. 4 is an access state of a conventional example. (Part 1) and FIG. 5 are access state diagrams (Part 2) of the conventional example. In the drawing, 1 is the OP code register (OPC-REG), 2 is the start address register (SA-REG), 3 is the element number register (EL-REG), and 4 is the final address calculation circuit (SA+, EL*8). ), 5.8 is a selector (SEL), 6 is a subtracter (-20 (HEX)), 7 is a request address register (RA-1 Company G), and 9 is an EL subtraction register (EL DEC- REG), 0 is 14 registers, 11 is request control circuit (REQ-CTL), M S LJ
is the main memory, MCt is the main memory control unit, VU is the hector unit, SU is the scalar unit, C14fI is the channel processor, ESU is the expansion unit, RMUB;l: extension i, i! if] control device,
are shown respectively.

Claims (1)

[Claims] In a data processing system in which a plurality of processing units access consecutive addresses of a main storage device, the access throughput of the processing unit is smaller than that of other processing units, or the access throughput is larger than that of other processing units. A main memory control system characterized in that the order in which successive addresses are accessed by one of the processing devices is in descending order of addresses.