JPS6266359A - Communication system between processor - Google Patents

Abstract

PURPOSE:To effectively utilize a limited number of subchannels by providing a mode in which a bus is not set previously when a system is started up and set in data transfer. CONSTITUTION:Subchannels in opposite-processor fixed mode are set previously by a transmission-side and a reception-side interprocessor connecting device 14, but a couple of subchannels in opposite-processor floating mode are not set previously on the transmission and reception sides when the system is started up, but set in a path setting state storage area by the transmission-side connecting device 14 with a command every time data is transferred to transmit data immediately. The data reception side connecting device 14 checks channels in use from a received frame, a path check is not made in the opposite processor floating mode, and a path is set on the basis of the address information of the received frame, so that processors 10, 11, and 12 reads in bus information with a sense command after reading data.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a communication method between multiple processors, and particularly to a communication method that enables direct data transfer between tasks between multiple processors. be.

[Conventional technology]

FIG. 4 shows a configuration example of a conventional inter-processor communication system. In FIG. 4, each task 17 in processors 0, 11.12 has a one-to-one correspondence with a subchannel 16 of channel 20.21.22, respectively. on the other hand,
Inter-processor connection device 14 is channel interface 1
channel 20 of processor 10.11.12 by 5;
2].

22. In the inter-processor connection device 14, a destination processor address, a destination processor address, and a
A function is provided to store destination subchannel addresses and path setting states.

A plurality of processors are interconnected via the inter-processor connection device 14 by a transmission path I3 having an arbitrary topology. Note that each subchannel is connected on a one-to-one basis.

Data transfer between subchannels is performed in the following steps.

The inter-processor connection device 14 on the sending side receives a command specifying the destination address, sets the destination processor address and the destination subchannel address in the storage area corresponding to the I10 address (the subchannel address),
Put the subchannel into address setting state. A similar address setting is performed in the inter-processor connection device 14 on the receiving side.

When a data transfer request is generated, the inter-processor connection device 14 on the sending side receives a data transfer request from the channel, reads the destination processor address and the destination subchannel address from the storage area corresponding to the specified subchannel address, and frames the transmission frame. and sends the data to the transmission path. If the address is not set in the storage area, an error is reported to the channel. When the inter-processor connection device 14 on the receiving side receives a frame from the transmission path,
It checks the status information of the storage area corresponding to the destination subchannel address specified in the frame, and if it is receivable, requests the corresponding subchannel of the channel to receive data. If reception is not possible, report this to the sender.

[Problem that the invention seeks to solve]

In this way, in the conventional method, when the system is restarted before data transfer, the other party's processor address and the other party's subchannel address are stored in one of the storage areas that stores the path setting status of both the sending side and the receiving side in advance. It needs to be set. That is, 1:1 subchannel pairs are set in advance.

Therefore, subchannel pairs must be set in advance for infrequent communications such as broadcast communications and datagram communications for data circulation, resulting in inefficient use of subchannel pairs and a shortage of subchannel pairs. There are drawbacks that pose problems.

An object of the present invention is to effectively utilize a limited number of subchannels in a communication system between multiple processors.

[Means and operations for solving the problem] In addition to the conventional data transfer mode (partner fixed mode) in which fixed sub-channel pairs (one pair) are set in advance, the present invention provides four sub-channels for each data transfer. = Provide a mode (partner floating mode) in which data is transferred by setting and releasing a Janel pair. Each subchannel consists of these two
It is assumed that one of the various modes is set in advance, and communication is performed by selecting the mode.

For subchannels in fixed partner mode, subchannel pairs are set in advance on the interprocessor connection device on the sending and receiving sides, but for subchannels in floating partner mode, pairs are set in advance on the sending and receiving sides at the time of system startup. Instead of setting a subchannel pair (path), each time data is transferred, it is set in the path setting state storage area by a command in the interprocessor connection device on the sending side, and then data is immediately transmitted. The inter-processor connection device on the data receiving side checks the used subchannel from the received frame and, if the other party is in floating mode, performs a path check based on the contents of the path setting status storage area when receiving data. (rejecting addresses other than subchannel addresses), a path is set based on the address information of the received frame, and after the processor reads the data (by the READ command), the path information is read by the sense command. Note that the next request from the other subchannel will not be accepted until the path information has been read.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention. The basic configuration is the same as that in FIG. 4, but for example, subchannel 16
-5 is not fixedly coupled to another subchannel 16-1 on a one-to-one basis, but can be coupled to another subchannel 16-10 when data transfer is completed.

For this reason, the inter-processor coupling device 14 is provided with the following functions.

■ When starting up the system, assign each subchannel to fixed partner mode and floating partner mode.

(2) For the storage area of a subchannel in fixed partner mode, write to the partner subchannel and set a subchannel pair in advance. This setting is not performed for subchannels in partner floating mode.

■ Data transfer operation function in fixed destination mode remains the same as before.

■ Data transfer operation functions in partner floating mode are as follows.

B. When a data transfer request occurs, first accept a command to set the destination address, set the destination processor address and destination subchannel in the storage area corresponding to the I10 address (subchannel address), and then select the corresponding subchannel. Enter the address setting state.

When a data transfer request is received from a channel, the destination address and destination subchannel address are read from the storage area corresponding to the specified subchannel address, and the WRI
It assembles an RE request transmission frame and sends the data to the transmission path.

C. Upon receiving a WRITE request frame from the transmission path,
The status information of the storage area corresponding to the destination subchannel address specified in the frame is checked, and the status is RE.
If it is an AD display and the subchannel is not in use and can be received -7, then write the source processor address and the source subchannel address in the storage area, and send the frame that notifies the source of synchronization to the transmission path. Send to. If the subchannel is in use, this fact is reported to the transmission source.

2. When receiving a synchronization frame from the transmission path, it requests the channel to send data, frames the data, and sends it to the transmission path.

E. When a data frame is received from the transmission path, a request is made to the corresponding subchannel of the channel to receive data.

After all data has been received, the source address and source subchannel address are read into the processor from the path setting storage area using a sense command.

FIG. 2 shows an embodiment of an inter-processor connection device to which the present invention is applied, which includes an I10 interface control unit 201, an input/output data (IOD) register 202, and a command (CM
D) Register 203, device status (DSB) register 204, device control unit 205, subchannel table 20
6. Data link=8= It is composed of a data link controller 20B, an instruction (IR) register 209, a data buffer 210, a report (SR) register 211, and the like. The subchannel table 206 includes a destination processor address (DPCI) and a destination subchannel address (D S
B C) and an area for storing the path setting status (STA).

Hereinafter, based on the communication example shown in FIG. 3, the transfer operation will be explained with reference to FIG. 2. An example of data transfer operation in fixed destination mode is
Since it is the same as the conventional method, only the case of opponent floating mode will be explained here. In addition, in Fig. 3, HO8 at the left end
T is the processor 10 in FIG. 1, and R and CI#A are the inter-processor connection device 1 connected to the processor 10.
4, HO8T at the right end corresponds to the processor 11 in FIG. 1, and RCT#B corresponds to the inter-processor connection device 14 connected to the processor 11.

Inter-processor connection device PCT #A that received a path setting command (for example, SET command) for I10 address #1 (subchannel address #i) from HO8T
When the I10 interface control unit 201 learns that the T10 address and operation command have been sent from the channel, the T10 address ttj is stored in the TOD register 20.
2, the operation command SET is set in the CMD register 223, the activation result is set in the DSB register 204, and reported to the channel. When the device control unit 205 continues to receive the destination processor address (DP(1) #B and subchannel address (DSBC) #j from the channel,
The destination address #R, # is specified in the subchannel #i of the subchannel table 206 specified by the OD register 202.
j and path setting display, and when the setting is completed normally, sets the channel end (CE) and device end (DE) in the DSB register 204, and reports to the channel that the path setting operation has completed normally. do.

Next, the process moves to the transfer operation command. It is assumed that data is transferred from PCI#A to PCI#B. H on PCIaB side
The task on the OS T processor issues a pre-read command of the READ command to all subchannels, and
The task of the HOST processor on the aA side issues a write request for a WRTTE command to the corresponding subchannel when a transfer request occurs. Preliminary reading is performed for all subchannels by multiple processing as follows. When a certain R E A D command is issued, PCT #
A READ command is entered in the CMD register 203 of B,
The specified subchannel address is l0r) register 2
Set to 02. FIG. 3 shows a case where subchannel address #j is specified. Device control unit 205
is the state area (STA) of the corresponding subchannel #j in the subchannel table 206 specified by the IOD register
) 207 to indicate that there was a RE A D request, and
A command retry request (RET) is sent to the SB register 204.
> display (SM, GE, UC) and instructs the I10 interface control unit 201 to perform a reporting operation.

On the other hand, when the WR1TE command is issued to PCr #A, WRT is written to the CMD register 203 in the same way as above.
TE is set to #i in the TOr' register 202. When the device control unit 205 registers that a WRI'I'E request has been made in the corresponding subchannel #i of the subchannel table 206 specified by the TOD register 202, the device control unit 205 sends an instruction register 209 to the data link control unit 208. Set the WRITE request to . Data link control unit 208
Assembles the transmission request frame 301 shown in FIG. 3 based on the information in the instruction register 209, TOD register 202, and subchannel table 206, and sends it to the loop-shaped transmission path 13. At the same time, it sends the command retry frame to the DSB register 204. A request (RET) is displayed (SM, CE, 1., JC) to instruct the I10 interface control unit 201 to perform a reporting operation.

The data link control unit 208 of PCI #B, which received the transmission request frame 301, buffers the frame in the data buffer 210 and writes the transmission destination subchannel address #j in the frame to the 0D register 202 as WR.
Place the ITE request into the report register 211. The device control unit 205 confirms that the subchannel address specified in the OD register 202 is in floating mode, and performs a pass check (checks whether it has been written to the subchannel in the subchannel table 206). The status information registered in the status area (STA) of the corresponding subchannel #j in the subchannel table 206 is read
When the display confirms that data reception is possible, the sender processor address #A and subchannel address #i are written to subchannel #j of the subchannel table 206, and instructions are sent to notify the other processor of a data transmission request. A synchronization indication (M) is made in the register 209, and the data link control unit 208 is instructed to send the synchronization report frame 302 shown in FIG. 3 to PCI#A. The data link control unit 208 requests data necessary for frame configuration from the transfer control unit 212, and sends the frame to the loop-shaped transmission path I3 while assembling the frame.

The data link control unit 208 of the PCI SA that received the synchronization frame buffers the frame in the data buffer 210, sends the destination subchannel address #i in the frame to the TOD register 202, and sends the synchronization indication (M) to the report register. Set to 211. The device control unit 205
In order to report to the own processor that the synchronization report has been received,
Device termination (DE) is set in the DSB register 204 to instruct the I10 interface control unit 201 to perform a reporting operation. Due to device termination (DE), a command retry instruction is issued from the channel to PCT#A, and WRI
A TE command is sent.

The I10 interface control unit 201 of the PCT SA,
The WRITE command and TOD address #i sent by command retry are set in the CMD register 203 and TOD register 202. The device control unit 205 checks the 5TA 207 of the corresponding subchannel #i in the subchannel table 206 specified by the TOD register 202, and if the path is set and the synchronization is completed in the WRITE system, the startup is started. In order to indicate that the process has been carried out normally, all "0"' are set in the DSB register 204, the I10 interface control unit 201 is instructed to perform a reporting operation, and the process proceeds to the transfer of WRITE data.

The transfer control unit 212 buffers the data sent from the channel to the data buffer 210. Also,
The data ring control unit 208 has an instruction register 209, an IO
The data frame 303 shown in FIG.

The data link control unit 208 of PCI #B, which received the data frame 303 from the loop transmission path 16, stores the transmission destination subchannel address #j of the frame in the IOD register 2.
02, the report register 211 is set to indicate that it is a data transfer, and the received frame is buffered in the data buffer 210.

The device control unit 205 checks the corresponding subchannel #j in the subchannel table 206 specified by the IOD register 202, and finds that the path setting display, READ system, and synchronization completion display are displayed in the status area (STA) 207. Original processor address #A, subchannel address #i
matches that specified in the received frame, then R
In order to prompt EAD command restart (retry), DSB
Displays device end (DE) in the register 204, and
10 instructs the interface control unit 201 to perform a reporting operation. Upon device termination (DE), a command retry instruction is issued from the channel to PCI#B, and a READ command is sent. The I10 interface control unit 201 of PCI#H sets the command and OD address # j ti'c MD register 203 and IOD register 202 that were sent in the command retry. The device control unit 205 selects 5T of the corresponding subchannel #j in the subchannel table 206 specified by the IOD register 202.
Check A207, path is set and RE
When synchronization is completed in the AD system, all 110 is set in the DSB register 204 to indicate that startup was performed normally.
1y is set to instruct the I10 interface control unit 201 to perform an activation report operation, and the process proceeds to a received data READ operation. After the data reception operation is completed, in order to report normal completion, channel end (CE) and device end (DE) are displayed in the DSB register 204, and the I10 interface control unit 201 is instructed to perform a reporting operation. At the same time, the device control unit 205 displays an ACK in the instruction register 209 in order to report to the other processor that the data has been received normally, and the data link control unit 208
Instructs to send a CK frame to the other processor.

A sense device command (for example, 5ENSE PCI) is sent from the PCI #B channel that has received CE and DE in accordance with a command chain instruction. When the sense device command enters PCI#B, PCI#
This command enters the CMD register 203 of B, and the IO
Specified subchannel address #j is set in D register 202.

In order to indicate that the startup has been performed normally, the device control unit 205 sets all II OII in the DSB register 204 and instructs the I10 interface control unit 201 to perform a startup reporting operation, and then sets it in the 10D register 202. The destination address #A and the destination subchannel address #i in the corresponding subchannel of the subchannel data 206 are transferred. After the transfer operation is completed, the DS
CE and DE are displayed in the B register 204, and the T10 interface control unit 201 is instructed to perform a reporting operation. At the same time, the device control unit 205 returns the contents of the corresponding address section of the subchannel 206 to its initial state.

When the PCI SA also receives an ACK frame 304 from PC1#B after transmitting data, the device control unit 205 sends the IOD
Contents of register 202 and received A-G K frame 304
Check whether the destination addresses match. If the addresses match and the contents of the report register 211 set from the ACK frame indicate normal completion, set CE and DE in the DSB register 204 to report normal completion to the own processor. Instructs the interface control unit 201 to perform a reporting operation. Further, the state of the corresponding address #i in the subchannel table 206 is returned to the initial state.

Although this method has been described using a loop-shaped transmission path as an example, it is also applicable to transmission paths of any topology, such as path type or star type.

[Effects of the Invention] As explained above, according to the present invention, in addition to the mode in which a path is set in advance at system startup and data transfer is performed, there is also a mode in which data is transferred without setting a path in advance at system startup. The provision of a path setting mode has the advantage that a limited number of subchannels can be used effectively, and subchannels can be used effectively for temporary communications such as broadcast communications and datagram communications.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the inter-processor communication method according to the present invention, FIG. 2 is a detailed diagram of the inter-processor connection device in FIG. 1, and FIG. FIG. 4 is a diagram showing an example of a conventional inter-processor communication system. =19- 10.11.12...Processor, 20.21.22...Channel, ]3...Transmission line, 14...Inter-processor connection device, 16...Subchannel, 17... ·task.

Claims (1)

[Claims] (1) In an information processing system in which a plurality of processors are interconnected by a transmission path, an inter-processor connection device is installed between the processors and the transmission path, and the input/output operations of the processors are connected to the inter-processor connection device. Storage means for storing a destination processor address, a destination subchannel address, and the path setting state for setting a communication path corresponding to a subchannel of a channel to be controlled, and a mode for communicating in a one-to-one fixed subchannel pair. (hereinafter referred to as partner fixed mode) and a mode for communicating with any partner subchannel at any time (hereinafter referred to as partner floating mode); and a means for specifying a mode for communicating with any partner subchannel at any time (hereinafter referred to as partner floating mode), and accepting a transfer request from the channel to a certain subchannel in partner floating mode. , means for setting a destination processor address and a destination subchannel address in the corresponding subchannel of the storage means, means for assembling a transmission frame based on the information in the storage means and sending it to the transmission path, means for receiving a frame, setting a source processor address and a source subchannel address specified in the frame in a storage means, and transmitting a frame to a transmission path for notifying the transmission source of synchronization; means for receiving a synchronization frame, requesting data transmission from a channel based on the synchronization frame, and sending a transmission data frame to a transmission path; means for transmitting a received frame to a subchannel; and after transmitting the received frame to a subchannel, a source processor address in the subchannel and a source subchannel address in the storage means are specified in the frame; An inter-processor communication method characterized by providing means for transmitting to a subchannel within a channel.