JPS6222168A - Communication system for inter-processor - Google Patents

Abstract

PURPOSE:To effectively utilize a sub-channel by providing an opposite selection possible mode that performs a bus setting in a data transmission time other than an opposite fixed mode that sets a fixed sub-channel with one to one. CONSTITUTION:An inter-processor connecting device 24, when a system is started up, allocates each of sub-channels 26-1-26-12 in each of processors 20-22 to sub-channels with the opposite fixed mode and to those with the opposite selection possible mode. And at a transmission side connecting device, a communication destination processor address and a communication sub-channel address in forefront two bytes are set at a storing area within a table corresponded to the sub-channel that received a write command. At the next stage, the communication destination address and the communication sub-channel address are read out from the forefront two bytes of data, assembling a write requesting transmission frame and it is sent out to a transmission line 23. Thereby, it is possible to effectively utilize the sub-channel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication system between multiple processors, and particularly to a communication system that enables direct data transfer between tasks between multiple processors.

Generally, processing programs and many control programs are executed within a system using units called tasks, and there are many tasks within a computer system, and these tasks are executed by the central processing unit (CPU). ) and other system resources are used alternately to execute each program, thereby achieving parallel processing of multiple programs as a whole. The present invention provides that between such tasks in a processor and tasks in other processors,
This relates to an inter-processor communication system that directly transfers required data.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional example of such an inter-processor communication system. In the figure, /O゜11.12 respectively indicate processors, 17 is a task, 16 is a subchannel, 14 is an inter-processor connection device, 13 is a loop-shaped transmission line in this case, 15 is a channel interface,
It is.

Now, in FIG. 4, the processor/O. Each task 17 within 11° 12 is associated with a subchannel 16 on a one-to-one basis. On the other hand, each inter-processor connection device 14 connects the processor/O. 1
112, and each inter-processor connection device 14 is provided with a table that stores destination processor addresses, destination subchannel addresses, and communication path setting states for each subchannel 16.

A plurality of processors are interconnected by a transmission line (hereinafter simply referred to as a transmission line) 13 of an arbitrary topology via this inter-processor connection bag W14. Note that even though the transmission path 13 is used, subchannels are connected one-to-one between processors in the conventional inter-processor communication system. The dotted line connecting subchannels 16 and 16 is
This is to show this.

Next, in FIG. 4, data transfer between subchannels is performed in the following procedure.

■) Now, let processor/O be the sending side, and processor 11
When the receiving side is the receiving side, when the connecting device 14 belonging to the transmitting side processor/O receives a command specifying the communication destination address from the processor side, it corresponds to the I/O address (subchannel address) where the command was received. The destination processor address and the destination subchannel address are set in the storage area in the table created, and the subchannel is placed in an address setting state. Similar address settings are made on the receiving side in preparation for data reception.

(2) When a data transfer request is generated, the sending side connection device 14 receives a data transfer request from the channel, reads out the communication destination processor address and communication destination subchannel address from the storage area on the table corresponding to the specified subchannel address, It assembles a transmission frame and sends the data to the transmission path 13. If the address is not set in the storage area, an error is reported to the channel.

■) When receiving a frame from the loop transmission path 13, the receiving side connection device 14 checks the status information of the storage area in the table corresponding to the communication destination subchannel address specified in the frame, and if it is possible to receive the frame, For example, the subchannel address of the channel is requested to receive data. If reception is not possible, report this to the sender.

As can be seen from the above explanation, in the conventional method, when starting up the system before data transfer, one of the storage areas that stores the path setting status is stored in the table in the connected device on both the sending and receiving sides. to the other processor address,
It is necessary to set the partner subchannel address.

That is, it is necessary to set in advance a 1:1 subchannel pair between the transmitting processor and the receiving processor.

Therefore, even when performing infrequent communication such as broadcast communication or data duram communication for data circulation, it is necessary to set subchannel pairs between the sending and receiving processors in advance. The use of subchannels becomes inefficient, and the shortage of subchannel pairs becomes a problem.

Conventional inter-processor communication systems have the above-mentioned drawbacks. Note that the conventional inter-processor communication method is
One example is the one proposed in Japanese Patent Application No. 57-41579.

[Problem that the invention seeks to solve]

Therefore, in the present invention, in addition to the conventional data transfer mode in which subchannel pairs of 1 to 1 are set in advance, subchannel pairs can be set and released each time data transfer is performed, and any partner subchannel pair can be set and released at any time. To also realize data transfer by a mode capable of communicating with a channel, and by that? The problem to be solved is to make effective use of the specified number of subchannels. Therefore, it is an object of the present invention to provide an inter-processor communication method that makes the above possible.

[Means and operations for solving the problem] In order to achieve the above object, the present invention provides a data transfer mode in which a conventional one-to-one fixed subchannel pair is set (more specifically, the above-mentioned Japanese Patent Application No. 41579), subchannel pairs can be set up and released each time data is transferred, enabling a mode in which communication can be performed with any partner subchannel at any time, and the former can be used as a fixed partner. mode, the latter is called the partner selectable mode. Each subchannel is preset to one of the above two types of modes, and communication can be performed by selecting the mode.

In fixed party mode, the subchannels are
Subchannel pairs are set in advance, but subchannels in partner selectable mode are
Subchannel pairs (paths) are not set in advance on the receiving side, but each time data is transferred, the transmitting side makes the necessary settings using a command in the path setting state storage area in the table, and then immediately assembles a frame and transmits the data.

In the partner selectable mode, the data transmitting side does not issue a path setting command when transmitting data, but directly issues a WRITE command. The path information required during transmission (the destination processor address and the arbitrarily selected destination subchannel address) is written at the beginning of the WRITE data, and by looking at this, the frame address information is known and the frame is assembled and transmitted. be able to.

In the case of fixed partner mode, the same procedure as before is performed.

Briefly, the differences between the present invention and the conventional technology are as follows:
It has a mode in which the path is set at the time of data transfer instead of setting the path in advance at system startup, there is no need to issue a path setting command when transmitting data, and the path information is included at the beginning of the transmitted data. , etc.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the concept of an embodiment of the present invention. In the figure, 20, 21, and 22 are processors, 27 are tasks, (26-1) to (26-12) are subchannels, 25 is a channel interface, 24 is an inter-processor connection device, 23 is a transmission path, It is.

The basic configuration shown in FIG. 1 is the same as that shown in FIG. 4, but for example, one subchannel (26-5) is paired with another subchannel (26-1). They are not fixedly connected in a relationship of Various subchannels are connected by dotted lines.

In this embodiment, the inter-processor connection device 24 has the following functions.

- At the time of system start-up, each subchannel in each processor is assigned to a subchannel in a fixed partner mode and a subchannel in a partner selectable mode.

- For subchannels that use fixed partner mode, write the partner subchannel and set subchannel pairs in advance.

(2) Fixed settings as described above are not made for sub-channels in partner selection mode.

(2) The data transfer operation function in the partner fixed mode is the same as the conventional one (as described in the above-mentioned Japanese Patent Application No. 57-41579).

(2) The data transfer operation function in the partner selectable mode is as follows according to the present invention.

When a data transfer request is generated from a transmitting processor, the transmitting side connection device belonging to the processor first accepts a WRITE command via the channel, and then sends a WRITE command to the channel.
Return SB=O and transfer the data.

Then, upon receiving the first 2-byte data containing the communication destination processor address and the communication destination subchannel address, which is not fixed but arbitrarily selected and determined, a retry request is returned, and the I/O address that accepted the WRITE command is sent. (Specifically, the subchannel address), set the communication destination processor address and communication destination subchannel address in the storage area in the table corresponding to the subchannel address, put the corresponding subchannel in the address setting state, Reads the communication destination address and communication destination subchannel address from , assembles a WRITE request transmission frame,
Send to the transmission path.

When the receiving side connection device receives a WRITE request frame from the transmission path, it checks the status information of the storage area in the table corresponding to the communication destination subchannel address specified in the frame, and if the status is READ indication, the corresponding subchannel If the channel is not in use and can receive data, the communication destination processor address and communication destination subchannel address are written in the storage area, and a frame for notifying the transmission source of synchronization is sent to the transmission path. If the subchannel is in use, this fact is reported to the transmission source.

When the transmission side connection device receives the synchronization frame from the transmission path, it requests the channel to transmit data, frames the obtained data, and sends it to the transmission path.

When the receiving side connection device receives a data frame from the transmission path, it requests the corresponding subchannel to receive data. After all data has been received, the source address and source subchannel address are read from the path setting storage area in the table into the processor using a sense command.

FIG. 2 is a block diagram showing a specific example of the connection device 24 in FIG. 1. As shown in the figure, the connection device 2
4 is an I/O interface control unit 201, an input/output data (/OD) register 202, a command (CMD) register 203, a device status g (DSB) register 204,
device control unit 205, subchannel table 206, data link control unit 208, instruction (IR) register 209,
Data buffer 2/O, report (SR) register 211
, etc.

FIG. 3 is an explanatory diagram of an example of communication according to the method of the present invention.

The data transfer operation will be explained below with reference to FIGS. 2 and 3. Since the data transfer operation in fixed partner mode is the same as the conventional method, the transfer operation in partner selectable mode will be explained here.

In FIG. 3, the leftmost HO5T is connected to the processor 20 in FIG. 1, the PCI#A is connected to the interprocessor connection device 24 connected to the processor 20, and the rightmost HO
3T is the processor 21 in FIG. 1, and PCI#B is the inter-processor connection device 24 connected to the processor 21.
, and data is transferred from the processor 20 to the processor 21.

First, the task on the receiving side HO3T processor on the PCIaB side issues a pre-read command of the READ command to all subchannels, and the task on the sending side HO3T processor on the PCIaA side
The third-superior task issues a write request for a WRITE command to the corresponding subchannel at the time a transfer request occurs. Pre-reading on the receiving side is performed for all subchannels as follows.

When a READ command is issued, PCI#B CMD
A READ command is entered into the register 203, and the designated subchannel address #j is set in the OD register 202. The device control unit 205 selects the state a area (STA) of the subchannel table 206 specified by the IOD register 202.
) 207 to indicate that there was a READ request, and
A command retry request (RET) is displayed in the register 204 (
SM, CE, UC) and instructs the I/O interface control unit 201 to perform a reporting operation.

In the interprocessor connection device PCI#A, which accepts the WRITE command for the subchannel with address #i from the sending side HO3T, the I/O interface control unit 201 sends the /O address and operation command from the subchannel. When it learns that it has arrived, it sets the I/O address in the IOD register 202, the operation command in the CMD register 203, and the activation result in the DSB register 204, and reports them to the channel.

When the device control unit 205 decodes the contents of the CMD register 203 and learns that it is a WRITE command, it decodes the communication destination processor address (DP
CI), a subchannel address (DSBC), and the address of the subchannel table 206 in which state information is set, and prepares to receive communication destination addresses #B and #j sent from the channel.

Note that the first two bytes of data transferred from the channel include the destination processor address #B and the destination subchannel address #j, and only the first two bytes are received at this stage.

Communication destination processor address (DPCi), subchannel address (DSBC), path setting, WRIT
When the E request display is successfully set in the subchannel table 206, a WRITE request is set in the instruction register 209 to the data link control unit 208. Based on the information in the instruction register 209, IOD register 202, and subchannel table 206, the data link control unit 208
The transmission request frame 301 shown in FIG.
Command retry request (RET) display (SM, CE,
UC) and instructs the I/O interface control unit 201 to perform a reporting operation.

The data link control unit 208 of the receiving PC #B that received the transmission request frame 301 buffers the frame in the data buffer 2/O, and stores the communication destination subchannel address #j in the frame in the /OD register 202. To,
Place the WRITE request into the report register 211.

The device control unit 205 confirms that the subchannel address specified by the /OD register 202 is selected and determined by the partner selectable mode, and performs a pass check (for the subchannel in the subchannel table 206). The state area of the subchannel table 206 (checking whether it is from the address being written)
When the state information registered in the STA (STA) confirms that data reception is possible in the READ display, the communication destination processor address and subchannel address are written in the subchannel table 206 in order to notify the other processor of a data transmission request. , synchronous display in instruction register 209 (M)
The data link control unit 208 performs the following and sends a synchronization report frame shown at 302 in FIG. 3 to PCI#A.
instruct.

The data link control unit 208 requests the transfer control unit 212 for data necessary for frame configuration, and sends the frame to the loop-shaped transmission path 16 while assembling the frame.

The data link control unit 208 of the receiving side PCI#A that received the synchronization frame transfers the frame to the data buffer 2/O.
The communication destination address is set in the IOD register 202 and the synchronization indication (M) is set in the report register 211.

In order to report to its own processor that it has received the synchronization report, the device control unit 205 sets the device end (DB) in the DSB register 204 and sends the I/O interface control unit 2
Instructs 01 to perform a reporting operation.

When the device ends (DE), a command retry instruction is issued from the channel to PCI#A, and a WRITE command is sent. The 1/O interface control unit '201 of PCI#A stores the command and IOD address sent by command retry in the CMD register 2.
03 and IOD register 202. The device control unit 205 checks the 5TA 207 of the subchannel table 206 specified by the OD register 202, and if the path is set and the synchronization is completed in the WRITE system, the startup has been performed normally. In order to indicate this, all 60'' is set in the DSB register 204, the I/O interface control unit 201 is instructed to perform a reporting operation, and the WRITE
Move to data transfer.

The transfer control unit 212 buffers the data sent from the channel to the data buffer 2/O. Also,
The data link control unit 208 has an instruction register 209, an IO
The data frame 303 shown in FIG.

The data link control unit 208 of the side PCI #B that received the data frame 303 from the loop transmission path 16 sends the communication destination subchannel address of the frame to the IOD register 202 and a report register 211 indicating that it is a data transfer.
, and buffer the received frame in data buffer 2/O. The device control unit 205 controls the IOD register 2
Check the subchannel table 206 specified by 02, display the path setting in the state a area (STA) 207, and set the RE
If the AD system synchronization completion is displayed and the communication destination processor address and subchannel address match those specified in the received frame, the device is written in the DSB register 204 to prompt the READ command restart (retry). An end (D E) display is displayed and the I/O interface control unit 201 is instructed to perform a reporting operation. Device termination (
DE), a command retry instruction is issued from the channel to the receiving side PCI #H, and a READ command is sent.

The PCI#B I/O interface control unit 201 stores the command and /O0 address sent in the command retry in the CMD register 203 and IOD register 202.
Set to .

The device control unit 205 checks 5TA 207 of the subchannel table 206 specified by the IOD register 202, and if the path is set and the synchronization is completed in the READ system, it indicates that the startup was performed normally. To show, D
Setting all "O" in the SB register 204 instructs the I/O interface control unit 201 to perform a startup report operation, and moves to the received data READ operation.After the data reception operation is completed, in order to report normal completion, the DSB register 204
Channel end (CE) and device end (DB) are displayed, and the I/O interface control unit 201 is instructed to perform a reporting operation. At the same time, the device control unit 205 reports to the other processor that the data has been successfully received.
An ACK is displayed in the instruction register 209, and the data link control unit 208 instructs to send an ACK frame 304 shown in FIG. 3 to the other processor.

A sense device command (for example, 5ENSE PCI) is sent from the receiving side PCI#B channel that received CE and DE according to a command chain instruction. When the sense device command enters PCI#B, PCI#
This command enters the CMD register 203 of B, and the IO
Specified subchannel address #j is set in D register 202.

To indicate that the startup has been performed normally, the device control unit 205 sets all “0” in the DSB register 204 and instructs the I/O interface control unit 201 to perform a startup report operation, and then sets the /OD register. The destination address #A and the destination subchannel address #i in the subchannel table 206 set in step 202 are transferred. After the transfer operation is completed,
To report normal completion, write CE to the DSB register 204.
.

Displays the DE and instructs the I/O interface control unit 201 to perform a reporting operation. At the same time, the device control unit 205
returns the contents of the corresponding address section of the subchannel table 206 to its initial state.

After sending data, PCI#A on the sending side also switches from PCI#B to AC.
Upon receiving the K frame 304, the device control unit 205
Contents of O0 register 202 and received ACK frame 303
Check whether the communication destination addresses match. If the addresses match and the contents of the report register 211 set from the ACK frame indicate normal completion, set CE and DE in the DSB register 204 to report normal completion to the own processor. /O interface control unit 201 is instructed to perform a reporting operation. Additionally, the state of the corresponding address section of the subchannel table 206 is returned to its initial state.

In the explanation here, it is assumed that the data receiving side collects the HO3T path information using commands, and that the receiving side subchannel is also specified on the transmitting side. It is also possible to select an empty subchannel on the receiving side.

Here, the method according to the present invention has been explained using a loop-shaped transmission line as an example, but the method according to the present invention can be realized using any type of transmission line of any topology, such as path type or star type. .

〔Effect of the invention〕

As explained above, according to the present invention, in the partner selectable mode, path setting is performed at the time of data transfer without setting the path in advance at system startup, so that only a limited number of subchannels can be used. HO3T has the advantage that it is possible to effectively use subchannels for temporary communication such as access, broadcast communication, and data duram communication, and there is no need to issue a path setting command before data transfer when in partner selection mode. This has the advantage that there is less communication overhead on the side.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the concept of an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the connection device in FIG. FIG. 4 is a block diagram showing a conventional example of an inter-processor communication system. Explanation of symbols 20.21.22...Processor, 23...Transmission line, 24...Inter-processor connection device, 25...Channel interface, (26-1) to (26-12)...
・Subchannel, 27...Task agent Patent attorney Akio Namiki Agent Patent attorney Kiyoka Matsuzaki) Part 3

Claims (1)

[Claims] 1) In an information processing system in which a plurality of processors are interconnected by a transmission path, an inter-processor connection device is installed between each of the processors and the transmission path, and the inter-processor connection device is a subchannel table for storing a communication destination processor address, a communication destination subchannel address, and the path setting state for setting a communication path corresponding to a subchannel, which is a unit of channel that controls input/output operations of the processor. , an I/O interface control unit, a device control unit, a transfer control unit, a data link control unit, and a data buffer;
When transmitting data from a certain task in A to a certain task in the receiving processor #B via the transmission path, the inter-processor connection device belonging to the sending processor #A When a WRITE command is received from a channel (hereinafter referred to as a sending channel) via an I/O interface control unit, the device control unit calculates and prepares an address #i to be set in the subchannel table. If the transfer mode is not the fixed destination mode, then the communication destination processor address #B sent from the sending channel and the subchannel address #j arbitrarily selected and sent as the other party.
is set as the address #i of the subchannel table, and after that, a WRITE request is notified to the data link control unit.The data link control unit refers to the address #i of the subchannel table and writes the communication destination. Assembles a transmission request frame including processor address #B and subchannel address #j and transmits it to receiving processor #B via the transmission path, and the inter-processor connection device belonging to receiving processor #B: After the data link control unit receives the transmission request frame and buffers it in the data buffer, when the device control unit learns the subchannel address #j specified in the frame, the device control unit Refer to the table, confirm that the path setting status information of address #j in the table is displayed as READ and data reception is possible, and set the communication destination processor address #A and subchannel address #i to the address in the subchannel table. #j to instruct the data link control unit to send a synchronization report frame as a data transmission request notification to the other processor #A, and the data link control unit requests data necessary for frame configuration from the transfer control unit. Then, a frame including the synchronization indication M is assembled and sent to the transmitting processor via the transmission path. In the transmitting processor-to-processor connection device that receives the synchronization frame, the data link control unit buffers the frame in a data buffer. After ringing, a synchronization report is sent to the device control unit, and the device control unit reports to its own processor #A via the I/O interface control unit that there has been a synchronization report using a synchronization frame, and thereafter transmits The transfer of WRITE data is started from the task of the side processor #A to the task of the receiving side processor #B, and after the transfer is completed, the subchannel table is cleared and the communication path is disconnected every time the data transfer is completed. An inter-processor communication method characterized by making it possible.