JPS6265372A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the width of a gate electrode on the output stage of a CCD shift resistor for increased transferring efficiency, by forming one side of the gate electrode so as to surround an output diffusion layer while forming the other side of the gate electrode approximately in parallel to the direction along which gate electrodes other than the output stage are extended. CONSTITUTION:Gate electrodes 9 and 12 are formed into a rectangular shape and arranged in the direction intersecting the direction along which a pair of CCD shift resistors 3 are extended. A gate electrode 12A constitutes the output stage of a CCD. One side of the electrode 12A is formed to have a V-shaped profile, while the other side is approximately parallel to the direction along which the gate electrodes 9 and 12 other than the output stage of the CCD are extended. An N<+> type semiconductor region 3 serving as an output diffusion layer is provided in the region surrounded by the V shape of the gate electrode 12A. According to this construction, the output voltage can be increased for stabilized output signal and the charging speed of charges to be transferred to a capacitor element can be increased to enable the device to operate more rapidly.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device, and in particular, a charge coupled device (hereinafter referred to as a CCD).
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a semiconductor integrated circuit device.

[Background Art] A one-dimensional CCD photosensor employs the following output method. The charge generated in the photodiode is COD
Transfer via shift register.

This transferred charge is charged to a capacitive element constituted by an output diffusion layer through a gate electrode of an output stage. and,
The voltage change of this capacitive element is amplified by an amplifier and outputted to the outside as an output signal.

This type of COD shift register is required to stabilize the output signal and increase its speed.

Therefore, the patent application No. 1, 1983, which was previously filed by the applicant,
No. 78558 describes a technique that can meet the above requirements. In this technique, the gate electrode of the output stage of the COD shift register is configured in a U-shape, and the output diffusion layer is configured to be surrounded by this gate electrode. According to this technique, the gate electrode width can be increased and the size of the output diffusion layer can be reduced, so that the charging speed of the capacitive element can be increased and the output voltage can be increased. Therefore, it is possible to stabilize the output signal and increase its speed.

However, as a result of experiments and studies on this technology, the inventor found that the following problem occurred. In the above technique, the gate electrode of the output stage is formed in a U-shape, and in order to match that shape, the gate electrode in the previous stage of the output stage is also formed in a U-shape. In the CCD shift register configured in this manner, the channel area of the stage preceding the output stage is larger than the area of the other channels. For this reason, the CC to which a constant clock signal is applied
In the D shift register, variations occur in the charge transfer state at the stage before the output stage, resulting in a decrease in charge transfer efficiency.

[Object of the Invention] An object of the present invention is to stabilize and speed up output signals in a semiconductor integrated circuit device equipped with a CCD, and to
An object of the present invention is to provide a technology that can improve charge transfer efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, one side of the gate electrode of the output stage of the CCD shift register is configured to surround the output diffusion layer, and the other side of the gate electrode is configured so as to surround the output diffusion layer, and the other side of the gate electrode is configured so as to surround the output diffusion layer. They are configured substantially parallel.

This makes it possible to reduce the size of the output diffusion layer and increase the width of the output stage gate electrode, increasing the output voltage, stabilizing the output signal, and increasing the charging speed of the capacitive element made up of the output diffusion layer. In addition to speeding up the process,
Since the channel area of the stage before the output stage can be configured to be approximately the same area as the other channels, the transfer efficiency can be improved.

Hereinafter, the configuration of the present invention will be explained along with examples.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I] In Example I, the present invention is applied to a composite channel type semiconductor integrated circuit device in which the output diffusion layers of two CCD shift registers are configured in common.

FIG. 1 is a schematic plan view showing a semiconductor integrated circuit device equipped with a one-dimensional COD photosensor, which is an embodiment of the present invention.

In FIG. 1, 1 is a semiconductor integrated circuit device equipped with a one-dimensional COD photosensor.

A photodiode 2 is provided in the center of the semiconductor integrated circuit device 1 and is configured to convert an optical signal into an electrical signal. A pair of CCD shift registers 3 are provided on both sides of the photodiode 2, and are configured to sequentially transfer electric signals (charges) from the photodiode 2 to the output diffusion layer. 4 is an amplifier provided near the output section of the CCD shift register 3;
It is configured to amplify the voltage that is the information transferred to the output stage of the shift register 3.

The output diffusion layers of the pair of CCD shift registers 3 are integrally constructed, forming a so-called composite channel type semiconductor integrated circuit device 1.

Next, a specific configuration of this embodiment will be explained.

The output part of the CCD shift register is shown in the main part plan view in Fig. 2, and the cross section taken along the line ■-■ in Fig. 2 is shown in Fig. 3. To make the configuration of Example I easier to understand.

Insulating films other than the field insulating film provided between each conductive layer are not shown.

In FIGS. 2 and 3, 5 is a P-type semiconductor substrate made of single crystal silicon, and 6 is a field insulating film.

The CCD shift register 3 is of a two-phase drive type. That is, a CCD consisting of an n-type semiconductor region 7°, a gate insulating film 8, and a gate electrode 9, and an n-type semiconductor region 10. A CCD composed of a gate insulating film 11 and a gate electrode 12 or 12A is arranged at a predetermined interval from each other.

The semiconductor region 7 constitutes a buried channel type CCD shift register 3, so that charge transfer efficiency can be improved.

Gate electrodes 9 and 12 are configured to be controlled by a regular transfer clock signal. The gate electrode 12A is configured to be controlled by a different clock signal. The gate electrode 9 is made of a first conductive layer in the manufacturing process, for example, a polycrystalline silicon film.

The gate electrodes 12 and 12A are made of a second conductive layer in the manufacturing process, for example, a polycrystalline silicon film.

The gate electrodes 9 and 12 have a rectangular shape and are provided extending in a direction intersecting the direction in which the pair of CCD shift registers 3 extend.

The gate electrode 12A constitutes the CCD of the output stage, and its negative side part is formed in a U-shape, and the other side part is where the gate electrodes 9 and 12 of the COD other than the output stage extend. It is configured substantially parallel to the direction.

In the output stage of the pair of CCD shift registers 3, an n-type semiconductor region 13 used as an output diffusion layer is located in a region surrounded by the V-shape of the gate electrode 12A.
is provided. This semiconductor region 13 is used as a capacitive element that charges the charge transferred by the CCD shift register 3.

The semiconductor region 13 constitutes the source region or drain region of the reset MISFET QR.
It is constructed integrally with.

In this way, one side of the gate electrode 12A of the output stage of the CCD shift register 3 is covered with a semiconductor region 1 that will become an output diffusion layer.
By configuring it in a V-shape surrounding 3, the size of the output diffusion layer is reduced to reduce the capacitance value of the capacitive element, and the width of the gate electrode 12A (channel width) is increased to increase the transfer conductance. Since the output voltage can be increased, the output voltage can be increased to stabilize the output signal, and the charging speed of the charge transferred to the capacitive element can be increased to increase the speed.

Also, the gate electrode 1 of the output stage of the CCD shift register 3
By configuring the other side of 2A to be approximately parallel to the extending direction of the gate electrodes 9 and 12 of CODs other than the output stage, the gate electrodes 9 (9A) of the previous stage of the output stage can be connected to the CODs other than the output stage. Since it can be configured in the same shape as the gate electrodes 9 and 12 of the COD, the channel area of the stage before the output stage and the channel area of the CCD other than the output stage can be configured to be approximately the same. Therefore, the charge can be uniformly transferred to the gate electrode 12A, so that the charge transfer efficiency can be improved.

The reset MISFET QR is composed of a gate insulating film 11, a gate electrode 1' 2B, and a pair of n+ type semiconductor regions 13 used as a source region or a drain region. MISFET
QR is configured to be controlled by applying a reset signal Φ2 to the gate electrode 12B. And M.I.
SFETQ is the gate f′! ! It is provided so as to be located approximately at the center within the area surrounded by the poles 12A.

This is to increase the margin for mask alignment in the manufacturing process of the gate electrodes 12A and 12B and the contact holes 15, which will be described later.

Qrz and Qn2 are n-channel MISFETs, and although not shown in FIG.
It is composed of a pair of semiconductor regions 13 of a type. This M
I S F E T Q n I+ Q n 2 constitutes an amplifier 4 that amplifies the voltage change of the charge charged in the capacitive element constituted by the semiconductor region 13 of the output diffusion layer.

14 is an interlayer insulating film that covers the CCD shift register, etc., 15
1 is a connection hole, and 16 is a wiring made of aluminum or the like. This wiring 16 is a connection wiring between semiconductor elements, and a power supply voltage V c
c (for example, 12 [V]) or the reference voltage V s
s (for example, 0 [V]) supply wiring and output signal wiring Vout.

In addition, in this embodiment I, the output stage gate voltage tail2A
Although one side portion of the gate electrode 12A is formed in a U-shape, in the present invention, one side portion of the gate electrode 12A may be formed in a U-shape.

[Embodiment 2] This embodiment 2 is another embodiment of the present invention applied to a multi-channel type semiconductor integrated circuit device in which the output diffusion layers of a plurality of CCD shift registers are each configured separately.

The output part of one CCD shift register of a semiconductor integrated circuit device equipped with a one-dimensional CCD photosensor, which is the embodiment (2) of the present invention, is shown in a plan view of the main part of FIG. 4. 3 shows two CCD shift registers 3. The CCD shift register 3 of the present embodiment (2) has the same structure as that of the above-mentioned embodiment I. That is, one side of the output stage gate electrode 12A is formed in a V-shape, and the other side of the gate electrode 12A is formed approximately parallel to the direction in which the other gate electrodes 9 and 12 extend. There is.

By configuring the CCD shift register 3 in this way, substantially the same effects as in the embodiment I can be obtained.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

In a semiconductor integrated circuit device equipped with a CCD, one side of a gate electrode of an output stage of a CCD shift register is configured to surround an output diffusion layer, and the other side of the gate electrode is configured to surround an output diffusion layer.
By configuring the gate electrodes in areas other than the output stage approximately parallel to the extending direction, the size of the output diffusion layer can be reduced and the width of the gate electrodes in the output stage can be increased, increasing the output voltage and increasing the output signal. In order to stabilize the current and increase the charging speed of the capacitive element composed of the output diffusion layer, the channel area of the gate electrode in the previous stage of the output stage is different from that of other parts except the output stage. Since they can be constructed with approximately the same area, transfer efficiency can be improved.

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, the present invention is not limited to the above embodiments, and may be modified in various ways without departing from the gist thereof. Of course.

For example, in the above embodiment, the present invention is applied to a semiconductor integrated circuit device equipped with a buried channel type CCD shift register, but the present invention is applied to a semiconductor integrated circuit device other than a buried channel type CCD shift register. You may.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a semiconductor integrated circuit device equipped with a one-dimensional CCD photosensor, which is Embodiment I of the present invention. FIG. 2 is a plan view of a main part of the output part of the CCD shift register in FIG. , FIG. 3 is a cross-sectional view taken along the line ``--'' in FIG. FIG. 3 is a plan view of the main parts of the output portion. In the figure, 1... Semiconductor integrated circuit device, 2... Photodiode, 3... CCD shift register, 4... Amplifier, 5... Semiconductor substrate, 7, 10... Semiconductor region, 8゜11...Gate insulating film, 9.12.12A...
・Gate electrode, 13... semiconductor region (output diffusion layer),
Q...MISFET. ++7 Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having a charge-coupled device, wherein one side of a gate electrode of an output stage of the charge-coupled device is
1. A semiconductor integrated circuit device configured to surround an output diffusion layer, the other side portion being configured to be approximately parallel to the extending direction of a gate electrode other than the output stage. 2. The semiconductor integrated circuit device according to claim 1, wherein one side of the gate electrode of the output stage is formed in a V-shape or a U-shape.