JPS6264122A - Driver circuit - Google Patents

Abstract

PURPOSE:To attain the normal operation at a voltage level of a voltage by a dry battery by using a circuit bringing a gate potential of the 6th FET to a prescribed potential when an input signal to a prescribed node is at a low level. CONSTITUTION:When a signal inputted to a node 3 changes from H to L, a FET Q1 is turned on and a FET Q3 is turned off, the potential of the node 1 goes up to a VDD and the potential of a node 2 goes up to a VDDVTN lower by a threshold voltage VTN of the EFT Q2, the potential of the node 4 is lowered, the FET Q4 is turned on to increase the potential of the node 2 to the VPP. In this case, the FET Q2 is turned off, even when a high voltage is fed to the VPP for the write, the potential at the node 2 goes to a high potential in tracking and the level of the node 4 is kept to a GND level. Con versely, when the input signal of the node 3 changes from L to H, the FETs Q1, Q2 are turned off to decrease the potential at the node 2, the nodes 1, 2 are of equipotential, the FET Q5 is turned on and the FET Q6 is turned off, the level of the node 4 goes up to the VPP, the FET Q4 is turned off and the node 2 is kept to the GND level.

Description

[Detailed Description of the Invention] [Field of Application] The present invention relates to a CMO8 EPROM circuit, and particularly relates to a circuit for driving word lines or selectors thereof. As shown in Figure 2, V
L) P channel type MU with rC connection between D and node 11
SFET Ql 1 and n*Nf type MU8FET Ql 2 (!:
, rb*N channel type M connected between node 12 and GND
(JSFET Ql3, P-channel type h10sFET Ql4 connected between VPP and node 12,
P-channel type M connected between VPP and node 14
It consists of O8FET Ql5 and an N-channel type M (JSFET Ql6) connected between node 14 and GND, Qll and Ql 3 (2) gates are connected to node 13 f1% Q12 (2) gates are connected to VDDIC gjL
, the gates of Ql4 are connected to node 14; the gates of fi, Ql5 and Ql6 are connected to node 12, and the gates of fi, Ql5 and Ql6 are connected to node 12;
An address selection signal is input to 3Ic, and the node 14 is normally connected to a word line or the like.

In the read state, VPP = VDD, and when loading, determine the address in the state of ld VP)' = VDD, and after the address is fixed, set the VP such that VPP > VDD.
Since it is normal to apply a voltage (IOV~25V) of P, let us consider the case of VPP2VDD.

An address selection signal is input to node 13. When W, Qll becomes conductive and Ql3 becomes non-conductive, so the potential at node 11 rises to Vl)D, and node 1
2 is the threshold voltage of Ql2, +7) [lower than VDD-VTNl, the upper iED, qizh becomes non-conductive, and by setting it appropriately, the node 14 can be lowered. W
When the voltage level is set to Q14i exclusive state, the potential at node 12 rises to VPP, and Ql5 becomes completely non-conductive. In order to write in this state, if VPP such as VPP) VDD is applied, Ql2. Ql3 and Ql
5H is in a non-conducting state and Ql4 is in a conducting state, so the potential at node 12 rises following VPP, but the value at node 14 remains the same. 2"L kept at W.

Conversely, the selection signal 2 of the address to be input is input to node 1311C.
EH'i gh(=VDD) tri%Q 1 at O
1 Ire becomes non-conducting, Ql3 becomes conductive, and the potential at node 12 drops to the potential determined by the ratio of Ql4 and Ql3. By lowering this potential sufficiently to maintain an appropriate ratio of Q15 and Ql6, the potential at node 14 rises to VPP, Ql4 becomes non-conductive, and the potential at node 12 falls to the GND level. V to put in the rose in this state
When VPP gold is applied such that PP)VDD is applied, the potential of the #-1 node 14 follows VPi'FC and rises, and the potential of the node 12 is maintained at the GND level.

[Problem that the invention seeks to solve]

As mentioned above, IC% EPROM is VP in the continuous state.
Operates with P=VDD, and in write state VPP>VDD
Make it work.

In conventional circuits, the input is low. When W, first the potential of node 12 becomes 1'tQ11! , is VDD-VTN'! Then, Q141/(j rises to vPP, but the circuit operates normally only when VDD-VTN o[ is sufficiently large compared to the V,, O value. For example, when one dry battery is used) Power supply voltage of about 1.0 V to 1.7 V
In order to read out the %VTN value (%VTN), it is necessary to make the VT'NO value extremely small, but there is a drawback that making the value of %VTN too small is not preferable in terms of process and circuit operation stability.

However, it is not necessary to operate with dry batteries only in the % read mode, and when performing writing, a power supply tube is used and there is no need to operate at low voltage, so there is no problem.

[Means for solving problems]

The driver circuit for EPRCJM according to the present invention has VDD
P channel MO8FE'l' Ql between and node 1
is connected, and Nf layer MO8F is connected between node 1 and node 2.
ETQ2 is connected15, N channel hMU8FETQ3 is connected between node 2 and GND11, KP channel M (J8FET Q4 is connected n5) between VPP and node 2.
VPP and node 4 VcP f 'r 7 channel M (JSF
ETQ5 is connected n% KNf-y channel between node 4 and GND M08 FETQ6 is connected n% Q2 gate is VDD
The gate of Qla and Q3 is connected to node 3 n.

The gate of Q4 is connected to node 4 fL, the gate of Q5 Fs
The gate of n%Q6 connected to node 2 is connected to node 1 71
An address selection signal is input to node 3,
Node 4 is connected to a word line or the like.

C′j1! Example] Next, non-invention will be explained with reference to the drawings.

1st! ! ! 3 is a circuit diagram of an embodiment of the present invention. Ql.

Q4, Q5FiP channel type MO8FET, Q 2 = Q 3 t Q 6 n N + 4
/ne/'g There is a MOS FET. Ql is VDD
and between node 1, Q2 is between node 1 and node 2, Q3 [
tT point 2 and GNDIjJII/c, Q, 4 are connected between VPP and node 2, Q5 is connected between VPP and node 4, and Q6 is connected between node 4 and GND. The gate of n%Q2 is connected to node 3, the gate of Q2 is connected to tVDD, the gate of Q4 is connected to node 4, fi,
The gate of Q5 is connected to node 2FC, and the gate of Q6 is connected to node IK. An address selection signal is input to node 3, and the VPP terminal is normally given a potential equal to VDD, but only when omitting, a high voltage is applied after the address is determined and V P P > V D D . υ, node 4 is connected to a word line or the like. The signal input to node 3 is High. When it changes to W, Ql becomes conductive.

Since Q3 becomes non-conductive, the potential at node 1 rises to VDD, and the potential at node 2 rises to vDDVTN, which is lower than VDD by the threshold voltage VTN of Q2. Since the potential of node 1 rises to VDDt, Q6 becomes conductive, lowering the potential of node 1 40, and Q4 becomes conductive, increasing the potential of node 1 20 to 2 vpp. At this time, Q2 is in a non-conductive state, so even if a high voltage of VPPK is applied here for writing, the potential of node 2 [VPPK is followed by a high potential IC, and node 4 is at GND level. is maintained.

Conversely, the input signal entering node 3vc is strong. W to High
, Ql becomes non-conductive and Q3 becomes conductive, which lowers the potential at node 1, but Q3
By setting a sufficiently large ratio between Q4 and Q4, the potential at node 2 becomes sufficiently low, and the potential at node l also becomes the same potential as node 2, so Q5 becomes conductive.

Q6- becomes non-conductive and the potential at node 4 rises to VPP at 9. Q4 is in non-conducting state and frniji, node 2°11!
The position becomes GND level. When the VPPK high voltage is applied in this state, the node 412)11: rises following VPP, and the potential of the node 2 is maintained at the GND level.

〔Effect of the invention〕

As explained above, the driver circuit of the present invention has an input signal to node 3. By configuring the circuit so that the Q6O gate potential becomes VDD when the voltage is W, it is no longer necessary for the VDD-V and NO values to be sufficiently larger than the VTN value, and the dry battery 1
It is possible to perform normal operation even at extremely high voltage levels.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional circuit. Q 11 Q 41 Q s −Q 11 t Q l
4 e Q 1 s is a P channel/channel type MO8FgT, Q z * Q 3eQ6. Ql2. Ql3. Q
l6 is an N-channel type MO8FET. Agent Patent Attorney Susumu Uchihara, r ”:'”:'
′(,

Claims (1)

[Claims] a first FET connected between the first voltage source and the first node;
a second FET connected between the first node and the second node; a third FET connected between the second node and the ground terminal; a second voltage source; a fourth FET connected between the second node and the fourth node; a fifth FET connected between the second voltage source and the fourth node; and a fifth FET connected between the fourth node and the ground terminal. 6 FETs, the gate terminal of the second FET is connected to the first voltage source, the gate terminal of the fourth FET is connected to the fourth node, and the gate terminal of the fifth FET is connected to the fourth node. A driver circuit characterized in that a gate terminal is connected to the second node, and a gate terminal of the sixth FET is connected to the first node.