JPS62231500A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To monitor the shift quantity of a threshold voltage of a memory cell accurately and to a sufficiently large value by connecting a control gate of a memory cell and a gate of a MOS transistor (TR) selecting a memory cell and a dummy cell to a high potential terminal in using an internal test circuit. CONSTITUTION:A high potential Vpp is applied to a work line WL and a Y selection BL at write, a power voltage Vcc is applied at read and gates of a memory cell 22 and MOS TRs 23, 31 are connected to a high potential Vpp in using the internal test circuit. In this case, a potential rising gradually is given to the high potential Vpp terminal externally to read the Vpp when the data is changed from the write state into the non-write state, the shift quantity(write quantity) DELTAVTH is recognized withstanding a high potential, the value of the shift quantity DELTAVTH for evaluation is improved remarkably.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and in particular to an EP
It is used to monitor the threshold pressure change m of a memory cell in a non-volatile memory such as a ROM that can be aged.

(Prior Art) Generally, an EPROM sense amplifier circuit using a differential amplifier has a configuration as shown in FIG. In FIG. 4, reference numeral 11 denotes a floating gate type transistor as a memory cell, and a word IWL is connected to the control gate of this transistor 11. 12 is a transistor Ill<Mo3 as a transfer gate, and Y selection 1 is connected to the gate of this MOS transistor 12.
1BL is connected. 13 is a load, and a sense line 14 is connected to the connection point between the load 13 and the MOS transistor 12.
One input terminal of the differential amplifier 15 is connected through the terminal.

The output terminal of a reference potential generation circuit 16 is connected to the other input terminal of the differential amplifier 15. The reference potential generation circuit 16 includes a dummy cell 17 having the same size as the floating gate transistor (memory cell) 11 and to which a power supply voltage VCC is applied to the gate, and a dummy cell 17 having the same size as the MOS transistor 12 and having a voltage lfA voltage y applied to the gate 1-.
It is composed of a MOS transistor (transfer gate) 18 to which cc is applied, and a load 19 for obtaining an intermediate level VR between the high (“H”) level and the low (°L”) level of the sense 114.

In the above configuration, a high potential vpp is applied to the gate of the MoS transistor 12 during leakage, and a power supply voltage VCC is applied during readout. The high potential vpp is applied from the outside at a terminal different from VCC.

The sensitivity of the sense amplifier circuit shown in FIG. 4 above (shift amount ΔVTH of the threshold voltage VTH of the memory cell required to determine that it is in the write state) (7) The dependence of the electric WAWM voltage vCC heno is as follows: The result is as shown in FIG. As can be seen from Fig. 5, in the sense amplifier circuit configured as shown in Fig. 4 above, even if the voltage is raised to V CC - 8 V, the threshold necessary to determine that the connection state is The shift amount ΔVTH of the value voltage VTH is 3■, Vcc-10V
However, it is about ΔVTH-4V. Considering the breakdown voltage of the transistors used in the peripheral circuit, it is difficult to set Vcc>IOV, and if the shift mΔVTH is 4■ or more, this shift amount cannot be monitored.

Therefore, conventionally, an internal test flow path as shown in FIG. 6 is used to monitor the shift amount of the pressure of the threshold value 1. 6th
The circuit configuration shown in the figure is basically the same as the sense amplifier circuit shown in FIG. 4, and differs only in the following two points. That is, first of all, the load 13 and the load 19 are made to have the same load characteristics. Second Nitami cell 17 (7) Gate L1tilt constant potential Vc independent of pressure VCC
is giving. This constant potential Vc is generated from a constant potential generation circuit 20 formed on the same chip.

The internal test circuit shown in FIG. 11t, I lt (CVCC - VT Hll - VCC - (VT Ha + ΔVTH). However, VTHII is the threshold voltage of the memory cell ()O-ting gate type transistor) 11, VT
HO is the threshold iN of the memory cell 11 in the non-writing state
It is voltage.

On the other hand, the current 117 flowing through the dummy cell 11 is il,
ccyc-VTHII. The point where the data changes is 1+t = 117, so Vcc - (
V HO + ΔVv H) = VC - V HO.

becomes.

In this way, by changing the level of the power supply voltage VCC while applying a constant potential Vc to the gate of the dummy cell 17, and monitoring the vCC level when the "HII level" or "Lpa level" of the data changes, the memory The shift amount ΔV1□ of the threshold voltage VTH of the cell 11 can be known.

FIG. 7 shows a combination of the sense amplifier circuit shown in FIG. 4 and the internal test circuit shown in FIG. 6, and one of the circuits is selected by external control signals A and A. It is. The control signal A is at the "H" level (Vcc level) during normal reading, and at the °°L° level when the internal test circuit is used.Therefore, during normal reading, the MOS transistors 21, 18, and 21 are in the on state and M
The OS transistor 182 is turned off, and the data read from the dummy cell 171 and the data read from the memory cell 11 are compared by the differential amplifier 15. At this time, the loads 191 and 192 operate to generate the intermediate potential VR. On the other hand, when the internal test circuit is used, the control signal A becomes "L" level, the MOS transistor 182 is in the on state, and the MOS transistor 21. ial
is in the off state. Therefore, the data read from the dummy cell 172 and the data read from the memory cell 11 are compared by the differential amplifier 15. At this time, only the load 192 operates, so both input terminals of the differential amplifier 15 have the same load.

By the way, in a device such as an EPROM that applies a high potential to a memory cell when writing data, there is a difference between a writing system (Vpp system) MoS transistor to which a high potential Vpp is applied during writing and a normal Vcc system MOS transistor. changing the structure. The write-in MOS transistor has a device structure that can withstand the electric potential by increasing the channel length and increasing the surface junction breakdown voltage by using an LDD structure. On the other hand, the voltage applied to CC-based MOS transistors is up to Vcc (5V), and a particularly high voltage is not applied during normal operation. It has an advantageous device structure.

However, as devices become more highly integrated in recent years, short channel effects and junction breakdown voltages of VCC MOS transistors in peripheral circuits are significantly reduced. For this reason, as miniaturization progresses, the electric WA voltage Vcc that can be applied to devices
levels are also declining. For example, conventionally Vcc-10
Although it was possible to apply up to Vcc, due to miniaturization of elements, it is now possible to apply only up to Vcc=8V. In the circuit of FIG. 6, as described above, ΔVT H - Vcc - Vc, so if the applicable power supply voltage Vcc decreases, the value of ΔVTH that can be evaluated also decreases. Furthermore, the circuit shown in FIG. 6 uses the output potential VC of the constant potential generation circuit 20, and since this constant potential VC is generated inside the chip, it is possible to monitor the voltage from the outside. Moreover, this constant potential VCG has a large dependence on the threshold 111g voltage of the tMOS transistor. Therefore, there is a drawback that the exact value of the threshold voltage shift +-mΔV-H of the selected memory cell cannot be known from the outside.

(Problems to be Solved by the Invention) As described above, in a semiconductor memory device equipped with a conventional internal test circuit, there is a shift in threshold voltage that can be evaluated due to a decrease in power supply voltage due to miniaturization of elements. There is a drawback that the value of -ffi decreases and that the exact value of this shift amount cannot be known from the outside.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device equipped with an internal test circuit that can accurately monitor the shift amount of the threshold voltage of a memory cell to a sufficiently large value.

[Structure of the Invention] (Means for Solving Problems and Their Effects) In this invention, when using an internal test circuit, the control gate of a selected floating gate transistor (memory cell) selects this memory cell. The gate of the i-transistor (lit<Mo8) as a transfer gate for selecting the dummy cell, and the gate of the transistor (111<Mo8) as a transformer 77 gate for selecting a dummy cell are each connected to a terminal for high potential Vpp.

Then, a test is performed by applying an arbitrary voltage to the terminal for this high potential Vl)D from the outside.

(Embodiment') Hereinafter, an example M of the present invention will be described with reference to the drawings. A word line WL is connected to the control gate of the floating gate transistor 22 as a memory cell in FIG. A ground point VSS is connected to one end of the memory cell 22, and one end of a MoS transistor 23 that operates as a transfer gate is connected to the other end. A Y selection line BL is connected to the gate of this MOS transistor 23. A load 24 is connected to the other end of the MOS transistor 23, and one input end of a differential amplifier 26 is connected to the connection point between the load 24 and the MOS transistor 23 via a sense ring 25. A reference potential generation circuit 27 is connected to the other input terminal of the differential amplifier 26.
The output end of is connected. This reference potential generation circuit 21 is
Load 2 connected to the other input terminal of the differential amplifier 26
8.29 and ~IQs transistor 30 to which control signal A is supplied for determining whether to select the load 29 or not.
Then, an electric voltage Vcc (during normal readout) or Vl) D (during internal test circuit use and wear-in) is applied to the gate, and III<M is applied as a transfer gate.
o8 Transistor 31 and gate with power supply voltage VC
A floating gate type transistor 32 to which C is applied acts as a dummy cell.

In the above configuration, the Y selection line BL and the word line WL are supplied with Vcc-based signals during normal reading, and Vpp-based signals when using the internal test circuit and during fortune-telling. Further, the load 24 and the load 28 have the same load characteristics.

Next, the operation will be explained. When using the internal test circuit,
The control signal A becomes "H" level, and the MO3I-Rungis 30 is turned off. Therefore, the load characteristics of the loads 24 and 28 connected to both input terminals of the differential amplifier 26 are the same. A current 12 flows through the memory cell (O-type transistor) 22 when the internal test circuit is used.
2 is +22 (X:Vllll) Vv H22-vpp-
(VT 1.IO+ΔVTH). However, VT11
22 is the threshold voltage of the transistor 22 as a memory cell.

On the other hand, the current 132 flowing through the gummy cell 32 is 132
o::Vcc-VT H32 =VCC-VTHQ. As described above, the potential of sense [25 with the differential amplifier 2G in between and the reference potential VR match when the voltage is 122-132. At this time, Vpp
(VTHO+ΔVdH) =VCc-Vr Hav p
p −v cc−ΔVTH. Therefore, by gradually increasing the potential applied to the high potential Van input terminal and reading Vpp when the data changes from the write state to the non-write state, the shift f
It is possible to accurately know f1 (fil input m)ΔVTH.

FIGS. 2(a) and 2(b) show the memory cell 22 and MOS transistors 23 and 31G in the circuit shown in FIG.
, :, shows an example of the configuration of a circuit for selectively applying the electric fi'l voltage Vcc 1% 1st place vpp. (a) The figure is
This is a circuit for selecting the power supply voltage VOC and the high potential vpp, and the control signal PGM which becomes the "L" level in write (program) mode and the control signal @A which becomes the "LIT level" when the internal test circuit is used. are respectively supplied to the AND gate 33. The output of this AND gate 33 is supplied to an inverter circuit 34 that converts a VCC-based input signal into an inverted Vpp-based signal and outputs the inverted signal. The output of this inverter circuit 34 is supplied to the gate of a MOS transistor 35 to which a high potential vpp is applied to one end.

Further, the output of the AND gate 33 is supplied to the gate of a MOS transistor 36 to which the power supply voltage Vcc is applied to one end. Then, the MoS transistors 35 and 3
The above control signal PGM and control signal @
A power supply voltage Vcc or high potential Vpp corresponding to A is obtained. This selection output is supplied to terminals 37 and 38 of a row decoder (column decoder) shown in FIG. This row decoder includes a Nant gate 39 to which an address signal Add is supplied, a MOS transistor 40 to which the output of the Nant gate 39 is supplied to one end and is set to be conductive by a power supply voltage CC, and the other end of the MOS transistor 40. It consists of a depletion type MOS transistor 41 connected between the terminal 37 and MOS transistors 42 and 43 connected in series between the terminal 38 and the ground point VSS, the input end of which is connected to the other end of the MOS transistor 40. It consists of a CMOS inverter. Then, the output of the CMOS inverter is supplied to the word line WL.

According to such a configuration, at the time of cleaning, the word line W
To L and Y selection line BL? X potential vpp is applied, power supply voltage Vcc is applied during reading, and memory cell 22 and MOS transistor 2 are applied when the internal test circuit is used.
The gate of 3.31 can be connected to the high potential Vpp terminal. At this time, by applying a gradually increasing potential to the high potential Vpp terminal from the outside and reading Vpp when the data changes from the write state to the non-write state, the shift amount (the amount of old data) ΔV can be accurately determined. be able to. In addition, since a high potential Vpp is applied to the word line and Y selection line BL during the distress, the MOS transistors forming the row decoder and column decoder have a device configuration that can withstand high potential, so the internal test circuit It is possible to apply a high potential even when using the 3D converter, and the shift (to) ΔVTH that can be evaluated can be significantly improved.

Note that in the row decoder (column decoder) shown in FIG. 2(b) above, a depletion type MOS transistor 41 is used, but as shown in FIG.
An enhancement type MOS transistor 45 may be connected between the curved end of the MoS transistor 7 and the MoS transistor 40, and conduction of this MoS transistor 45 may be controlled by the output of a CMOS inverter.

[Effects of the Invention] As explained above, according to the present invention, a semiconductor memory device equipped with an internal test circuit that can accurately monitor the shift amount of the threshold Ii pressure of a memory cell up to a sufficiently large value is provided. can get.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is an example of the configuration of a circuit for selectively applying a power supply voltage and a high potential to the circuit shown in FIG. 1. FIG. 3 is a diagram for explaining another configuration example of the circuit shown in FIG. 2, and FIGS. 4 to 7 are diagrams for explaining a conventional semiconductor memory device, respectively. 22, 32... 1st. 2nd) O-ting gate type transistor (22: memory cell, 32: dummy cell)
, 23.31... 1st. Second MOS transistor (transfer gate), 24...first load, 28
゜29...Second load, 26...Differential amplifier, WL
...word line, B[...Y selection line, VCC...first power supply, vpp...second power supply. 1lX1 diagram Figure 2 (a) Vcc (V) - Figure 5 Figure 6 Figure 7

Claims (2)

[Claims] (1) A first floating transistor whose control gate is connected to a word line and functions as a memory cell, and a first floating transistor whose gate is connected to a Y selection line and which functions as a transfer gate for selecting the first floating gate transistor. MOS transistor and this first
a first load connected to the MOS transistor; a second floating transistor having a control gate connected to the first power supply terminal and functioning as a dummy cell; and a gate having a gate connected to the first power supply terminal or a second power supply terminal having a high potential. a second MOS transistor that is selectively connected and serves as a transfer gate for selecting the second floating gate transistor; a second load connected to the second MOS transistor; the first load and the first MOS transistor; a differential amplifier having one input terminal connected to a connection point with the transistor and the other input terminal connected to a connection point between the second load and the second MOS transistor; A signal corresponding to the potential of the first power supply terminal is supplied to the word line and the Y selection line, and the gate of the second MOS transistor is connected to the first power supply terminal. A signal corresponding to the potential of the second power supply terminal is supplied, and the gate of the second MOS transistor is connected to the second power supply terminal, and during testing, the word line, the Y selection line, and the gate of the second MOS transistor are connected to the second power supply terminal. A semiconductor memory device, characterized in that the amount of change in the threshold voltage of the first floating gate transistor is monitored by connecting the first floating gate transistor to the second power supply terminal and applying a voltage from the outside to the second power supply terminal. (2) The second load is configured such that the potential at the other input terminal of the differential amplifier becomes 1/2 of the potential at one input terminal when reading data, and remains the same during testing. A semiconductor memory device according to claim 1, characterized in that: (3) The first floating gate transistor and the second floating gate transistor have the same size, and the first MOS
2. The semiconductor memory device according to claim 1, wherein the transistor and the second MOS transistor have the same size.