JP3534815B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a function of detecting a voltage of an arbitrary node inside the device.

[0002]

2. Description of the Related Art Generally, in order to evaluate the operation of a semiconductor integrated circuit device (hereinafter, also abbreviated as "LSI") manufactured as a sample product or a finished product, a main or operationally important node inside the LSI is selected. A probe (probe) is applied and the voltage of the node is detected.

[0003]

However, in the voltage detection method by contacting the probe, there is a possibility that the contact portion may be damaged, and the impedance of the node is subtly changed by applying the probe, Since the detection voltage becomes inaccurate, there is a problem to be improved in terms of preventing damage to the LSI and improving the reliability of voltage detection. [Purpose] Therefore, an object of the present invention is to provide a technique capable of detecting a voltage of an arbitrary node inside the device without using a probe contact method, which is effective for preventing damage and improving reliability of voltage detection.

[0004]

In order to achieve the above object, the present invention has a principle diagram thereof as shown in FIG. 1. As shown in FIG. A first current portion 3 for flowing Ia, and the first current portion 3
And a second current section 4 having the same voltage / current characteristic as the current Ia flowing through the first current section 3 when the same current Ib flows through the second current section 4. It is characterized in that the input voltage Eb of the current unit 4 of No. 2 is detected as corresponding to the voltage Ea of the arbitrary node 2.

Alternatively, the first current portion and the second current portion each include an enhancement-type N-channel MOS transistor, and the drain current of each N-channel MOS transistor is set to the currents Ia and Ib. Or, the first current portion and the second current portion,
An enhancement type N-channel MOS transistor having a high threshold voltage and a high breakdown voltage, respectively, is provided, and the drain current of each N-channel MOS transistor is set to the currents Ia and Ib, or the first current portion And the second current section is a depletion type N-channel MOS having a negative threshold value and a high breakdown voltage, respectively.
The present invention is characterized in that a drain current of each N-channel MOS transistor is provided with the currents Ia and Ib.

[0006]

In the present invention, each of the first current section 3 and the second current section 3, 4 has an individual external power source having the same potential (in FIG. 1, for convenience, represented by V _CC1 and V _CC2. ) Is connected, the input voltage Eb of the second current section 4 is adjusted so that the current Ib supplied from the external power supply V _CC2 to the second current section 4 and the first current section from the external power supply V _CC1 . 3 and the current Ia supplied to the third node 3 are made equal to each other, the input voltage Eb of the second current section 4 to the voltage E of the arbitrary node 2 at the time of the match.
a is indirectly detected.

Therefore, it is possible to detect the voltage of an arbitrary node inside the device without using the probe contact method, and to provide a technique effective for preventing damage and improving the reliability of voltage detection.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.
To do. First embodiment 2 to 4 show a first semiconductor integrated circuit device according to the present invention.
It is a figure which shows an Example.

In FIG. 2, reference numeral 10 denotes a chip (hereinafter, simply referred to as "LSI chip") of the semiconductor integrated circuit device which is schematically shown. Inside the LSI chip 10, a semiconductor integrated circuit (not shown) (example As "flash memory")
Are formed, the first current portion 11 and the second current portion 11 are formed.
Current portion 12 is formed. The first current section 11 is
A P-channel MOS transistor (hereinafter “PMOS”) 14 and an N-channel MOS transistor (hereinafter “NMOS”) 15 are connected in series between the first external power supply terminal 13 of the LSI chip 10 and the low potential power supply VSS, and , PM
The gate of the OS 14 is connected to the external control terminal 1 of the LSI chip 10.
6, the gate of the NMOS 15 is connected to an arbitrary node 17 of the semiconductor integrated circuit.

Further, the second current section 12 connects the PMOS 19 and the NMOS 20 in series between the second external power supply terminal 18 of the LSI chip 10 and the low potential power supply V _SS , and
The gate of the PMOS 19 is connected to the external control terminal 16 of the LSI chip 10, and the gate of the NMOS 20 is connected to L
It is configured by being connected to the external input terminal 21 of the SI chip 10.

Here, the PMOS 14, 19 and NMOS
Both 15 and 20 have a general threshold value and withstand voltage.
Using enhancement type MOS transistor
There is. For example, the threshold value of the NMOS 15 and 20 is about +
0.6V, breakdown voltage is about + 8V. In such a configuration
The first external power supply terminal 13 and the second external control terminal 1
8, individual power supplies with the same potential (eg + 5V)
Voltage (V for convenience_CC1, V _CC2) Is applied,
The threshold of the PMOS 14 (or 19) at the control terminal 16
Control voltage V having the following potential_contIs applied, PM
Both the OSs 14 and 19 are turned on.

At this time, the voltage of the node 17 is
If it is within the range from the threshold value of 15 (about +0.6 V) to the breakdown voltage of the NMOS 15 (about +8 V) (hereinafter referred to as “detection range L”), the NMOS 15 is in the ON state,
The ON resistance has a value corresponding to the voltage of the node 17, specifically, a high resistance when the voltage of the node 17 is low, and a low resistance when the voltage of the node 17 is high.

Therefore, the current I ₁₁ flowing through the first current portion 11 is proportional to the on-resistance of the NMOS 15, so that the current I ₁₁ eventually shows a magnitude corresponding to the voltage of the node 17. On the other hand, the current I flowing through the second current section 12
₁₂ is proportional to the on-resistance of the NMOS 20 like the first current section 11, but the on-resistance of the NMOS 20 increases or decreases according to the external input voltage Vi _L given to the external input terminal 21. This external input voltage V
By adjusting i _L , the current I ₁₂ of the second current section 12 can be matched with the current I ₁₁ of the first current section 11.

Therefore, if the two currents I ₁₁ and I ₁₂ have the same value, the gate voltages of the NMOSs 15 and 20, that is, the voltage of the node 17 and the external input voltage Vi _L are naturally equal values, and the external input voltage Vi is the same. _L can be detected as equivalent to the voltage of the node 17. As described above, according to the present embodiment, the voltage of an arbitrary node can be detected without using the probe contact method, so that the damage avoidance of the LSI and the reliability of the voltage detection can be improved. A suitable technique can be provided for use in detecting the main node voltage of the flash memory (collective erasing type read-only memory) described in 1 above.

FIG. 3 is a block diagram of the main part of the flash memory. 30 is a memory cell array, 40 is a write amplifier, and 5 is a write amplifier.
Reference numeral 0 is a sense amplifier, and 60 is a source voltage control circuit.
The memory cell array 30 includes a large number (for convenience, 2 × 2 in the figure) of memory cell transistors 31 to 34 arranged in a matrix.
The control gates (CG) of the memory cells are shared by row units and connected to the word lines 35 and 36, respectively, and the drains (D) of the memory cell transistors 31 to 34 are shared by column units and connected to the bit lines 37 and 38, respectively. Further, all the sources (S) of the memory cell transistors 31 to 34 are made common and connected to the source line 39, and the potentials of the word lines 35 and 36, the bit lines 37 and 38, and the source line 39. Information is written in, erased from, and read from the memory cell transistor according to the relationship.

The write amplifier 40 has an inverter gate 4
1, the NAND gate 42 and the PMOS 43 are provided, and when the write data DATA is at the L level in the write mode (when the signal PGM is at the H level), the PMOS 4
3 is turned on to output the program power supply V _PP (+ 12V) to the bit line 37 (or 38) via the bus line 44 and the selection transistor 45 (or 46).

The sense amplifier 50 includes a PMOS 51 and an NM.
The bus line 44 having the OS 52 and the inverter gate 53
And the potential of the bit line 37 (or 38) is set to be slightly higher (about 1 V) than the input threshold of the inverter gate 53 via the selection transistor 45 (or 46), and the information of the selected memory cell transistor is set. The inverter gate 53 detects and outputs the potential of the bit line 37 (or 38) that changes in accordance with the above.

The source voltage control circuit 60 is an NMOS 61 which is turned on in the read mode or the write mode.
And a PMOS 62 that is turned on in the erase mode, and outputs V _SS (0V) to the source line 39 when the signal R / W becomes H level and the NMOS 61 is turned on (in the write or read mode). , When the signal ERASR becomes L level and the PMOS 62 is turned on (in the erase mode), the program power supply V _PP (+12) is applied to the source line 39.
V) is output.

FIG. 4 is a diagram showing a structure and an electrical equivalent circuit of a memory cell transistor (typically 31). The memory cell transistor 31 is a P conductive type silicon substrate 31a.
A first insulating film (tunnel oxide film) 31b, a floating gate FG, a second insulating film 31c, and a control gate CG are sequentially stacked on top of each other, and the N conductivity type is provided on both sides of the channel region directly below the floating gate FG. The source region S and the drain region D are formed.

The material of FG and CG is polysilicon, the material of the first insulating film 31b and the second insulating film 31c is SiO ₂ film, and the thickness of the first insulating film 31b is 10
The thickness of the second insulating film 31c is about 0 Å, and the thickness of the second insulating film 31c is about 250 Å. The charge of FG in the initial state of the memory cell transistor is zero, and this state is defined as "1" of information. Now, assuming that the potential of the substrate 31a and the source S is 0V, the potential of the CG is + 5V, and the potential of the drain D is + 1V, F due to capacitive coupling.
The potential of G rises to about + 3V and the transistor becomes conductive. Next, the potentials of the substrate 31a and the source S are left unchanged (0 V), the potential of CG is +12 V, and the drain D is
If the potential of is raised to +6 V, a so-called avalanche breakdown (electron avalanche breakdown) phenomenon occurs, and a large amount of high-energy electrons and holes are generated near the drain D. Then, some of the electrons pass through the first insulating film (tunnel oxide film) 31b and are captured by the FG (writing of information). In this state, even if the potential of CG is returned to +5 V and the potential of drain D is returned to +1 V, the potential of FG is a low value of about −2 V, so the transistor maintains the same state (non-conduction state). The non-conduction state is defined as "0" of information. Here, if the potential of the substrate 31a and CG is 0V, the drain D is open, and the potential of the source S is + 12V, a so-called tunnel phenomenon occurs and FG
From this, electrons are extracted to the source S, and the charge of FG decreases. By controlling the tunnel time, the electric charge of FG can be made almost zero, and the data can be erased.

In the write operation in FIG. 3, the source line control circuit 60 sets the potential of the source line 39 to V _SS (0V).
And the selected word line (eg 35) + 12V
And the potential of the selected bit line (for example, 37) is set to +6 V by the write amplifier 40. At this time, if 0V is applied to the unselected word line 36 and 0V to the unselected bit line 38, no information is written to the unselected memory cell transistors 32 to 34.

Further, the erase operation is performed simultaneously for all the memory cell transistors 31 to 34, which applies 0V to all the word lines 35 and 36 and opens all the bit lines 37 and 38. , And + 12V is applied to the source line 39. In the read operation, 0 V is applied to the source line 39, +5 V is applied to the selected word line (eg, 35), 0 V is applied to the non-selected word line (eg, 36), and the potential of the selected bit line (eg, 37) is set. The sense amplifier 50 detects whether or not a current flows at about + 1V. If the current flows, in other words, if the memory cell transistor 31 located at the intersection of the selected word line 35 and the selected bit line 37 is in the conductive state, the information "1" is read, and if the current does not flow, the information "0" is read.

Therefore, when the first embodiment is applied to this flash memory, the voltage (+6 V) of the bit line 37 (or 38) at the time of writing and the word line 35 (or 36) at the time of reading are applied. Voltage (+5
Various voltages that fall within the detection range L such as V) can be detected without relying on the probe contact method. Second Embodiment FIG. 5 is a diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention.

In FIG. 5, reference numeral 110 denotes an LSI chip. Inside the LSI chip 110, a semiconductor integrated circuit (not shown) (for example, “flash memory”) is formed, and the first current section 111 is also provided. And the second current portion 112 is formed. The first current unit 111 is L
The PMOS 114 and the NMOS 115 are connected in series between the first external power supply terminal 113 of the SI chip 110 and the low potential power supply V _SS , and the gate of the PMOS 114 is connected to the external control terminal 116 of the LSI chip 110.
The gate of the NMOS 115 is connected to an arbitrary node 117 of the semiconductor integrated circuit.

The second current section 112 is connected to the second external power supply terminal 118 of the LSI chip 110 and the low potential power supply V _SS.
, And a PMOS 119 and an NMOS 120 are connected in series, and the gate of the PMOS 119 is connected to the LSI chip 11
0 is connected to the external control terminal 116 and an NMOS
The gate of 120 is the external input terminal 1 of the LSI chip 110.
It is configured by connecting to 21.

Here, the PMOS 114, 119 and NM
Each of the OSs 115 and 120 uses an enhancement type MOS transistor having a high threshold and a high breakdown voltage. For example, the NMOS 115 and 120 have a threshold value of about + 1.0V and a breakdown voltage of about + 17V. In such a configuration, a state where individual power supply voltages (for convenience V _CC1 and V _CC2 ) having the same potential (for example, +5 V) are applied to the first external power supply terminal 113 and the second external control terminal 118 Then, the external control terminal 116 is connected to the PMOS 114,
When the control voltage V _cont having a potential equal to or lower than the threshold value of 119 is applied, both PMOS 114 and 119 are turned on.

At this time, the voltage of the node 117 changes to NMO.
From the threshold value of S115 (about + 1.0V), the same NMOS1
If it is within the range up to the withstand voltage of 15 (about +17 V) (hereinafter referred to as “detection range H”), the NMOS 115 is in the ON state, and its ON resistance is a value corresponding to the voltage of the node 117, specifically, The resistance is high when the voltage of the node 117 is low, and low when the voltage is high.

Therefore, the current I ₁₁₁ flowing through the first current portion 111 is proportional to the on-resistance of the NMOS 115, so that the current I ₁₁₁ eventually shows a magnitude corresponding to the voltage of the node 117. On the other hand, the current I ₁₁₂ flowing through the second current section 112 is equal to N as in the first current section 111.
Although proportional to the on-resistance of the MOS120, this NMOS1
The on-resistance of 20 is adapted to increase / decrease according to the external input voltage Vi _H given to the external input terminal 111. By adjusting this external input voltage Vi _H ,
The current I ₁₁₂ of the second current section 112 is transferred to the first current section 111.
Current I ₁₁₁ can be matched.

Therefore, if the two currents I ₁₁₁ and I ₁₁₂ have the same value, the gate voltages of the NMOS 115 and 120, that is, the voltage of the node 117 and the external input voltage Vi _H.
Are naturally equal values, and the external input voltage Vi _H is applied to the node 11
It can be detected as equivalent to the voltage of 7. Here, the detection range H of the second embodiment is the NMOS 115 (or 1).
20) threshold voltage to withstand voltage range (about +1.0 V ~
It is about +17 V) and can be applied to the detection of a relatively high node voltage. However, when detecting a node voltage lower than that, the first embodiment may be used together.

That is, the detection range L of the first embodiment
Is a range from the threshold voltage of the NMOS 15 (or 20) to the breakdown voltage (about 0.6V to about + 8V), and thus can cover a wide voltage range from about 0.6V to about + 17V in total. For example, the voltage of the word line 35 (or 36) (+12
V) and the voltage of the source line 39 at the time of erasing (+12
V) can also be detected.

[0031] Third embodiment FIG. 6 shows a third embodiment of the semiconductor integrated circuit device according to the present invention.
It is a diagram showing a wide voltage range with one circuit.
This is an example of doing so. In FIG. 6, 210 is an LSI
It is a chip, and the inside of the LSI chip 210 is not shown.
Abbreviated semiconductor integrated circuit (for example, "flash memo
") And the first current portion 211 is formed.
And the second current portion 212 is formed.

The first current section 211 is connected to the LSI chip 21.
0 is connected in series between the first external power supply terminal 213 and the low potential power supply V _SS , and the gate of the PMOS 214 is connected to the external control terminal 216 of the LSI chip 210, and the NMOS 215 is connected.
Is connected to an arbitrary node 217 of the semiconductor integrated circuit.

The second current section 212 is connected to the second external power supply terminal 218 of the LSI chip 210 and the low potential power supply V _SS.
And the PMOS 219 and the NMOS 220 are connected in series with each other, and the gate of the PMOS 219 is connected to the LSI chip 21.
0 external control terminal 216 and NMOS
The gate of 220 is connected to the external input terminal 2 of the LSI chip 210.
It is configured by connecting to 21.

Here, as the PMOSs 214 and 219, the enhancement type having a high threshold value and a high breakdown voltage is used as in the second embodiment, but the NMOS 21 is used.
The depletion type 5 and 220 have a negative threshold value and a high breakdown voltage. The NMOS 21
The threshold of 5 and 220 is about -3.0V, and the breakdown voltage is about +17.
V.

In such a structure, the first external power supply terminal 213 and the second external control terminal 218 have individual power supply voltages (for convenience, V for convenience) having the same potential (for example, +5 V).
_CC1 and V _CC2 ) are applied to the external control terminal 216
When a control voltage V _cont having a potential equal to or lower than the thresholds of the PMOSs 214 and 219 is applied to the
Both 9 are turned on.

At this time, the voltage of the node 217 changes to NMO.
From the threshold of S215 (about -3.0V), the same NMOS2
If it is within the range up to the withstand voltage of 15 (about +17 V) (hereinafter referred to as “detection range L / H”), the NMOS 215 is in the ON state, and its ON resistance is a value corresponding to the voltage of the node 217, specifically Has a high resistance when the voltage of the node 217 is low, and a low resistance when the voltage of the node 217 is high.

Therefore, the current I ₂₁₁ flowing through the first current portion 211 is proportional to the on-resistance of the NMOS 215, so that the current I ₂₁₁ eventually shows a magnitude corresponding to the voltage of the node 217. On the other hand, the current I ₂₁₂ flowing through the second current section 212 is equal to N as in the first current section 211.
This NMOS2 is proportional to the on-resistance of MOS220.
The ON resistance of 20 is adapted to increase _/ decrease according to the external input voltage Vi _{L / H} given to the external input terminal 221, and the second current is adjusted by adjusting the external input voltage Vi _{L / H.} The current I ₂₁₂ of the section 212 is set to the first current section 2
11 current I ₂₁₁ can be matched.

Therefore, if the two currents I ₂₁₁ and I ₂₁₂ have the same value, the gate voltages of the NMOSs 215 and 220, that is, the voltage of the node 217 and the external input voltage Vi.
_Of course, _{L / H is} also an equal value, and the external input voltage Vi _{L / H} can be detected as being equivalent to the voltage of the node 217. Here, the detection range L / H of the third embodiment is the NMOS 215
(Or 220) from the threshold to the breakdown voltage,
Specifically, it is a wide range from about -3.0V to about + 17V.

Therefore, according to the third embodiment, since the detection range L of the first embodiment and the detection range H of the second embodiment can be covered by one circuit, the structure is simplified. Therefore, it is possible to obtain a unique effect that the cost can be improved. Further, the third embodiment is superior to the first and second embodiments in that a voltage close to 0 V (for example, the source voltage of the flash memory) can be measured.

That is, the first embodiment cannot measure a voltage of +0.6 V or less, and the second embodiment has +1.
Since a voltage of 5 V or less cannot be measured, the source voltage cannot be detected when applied to a flash memory, for example. Furthermore, in the third embodiment, since the depletion type transistors (NMOS 215, 220) are used, the voltage detection range can be expanded from -3V to around + 17V, and a wide range of voltage detection can be performed by one circuit. be able to. On the contrary, the first embodiment and the second embodiment
In the embodiment, it is necessary to predict the magnitude of the voltage to be measured and determine which of the embodiments should be used, which complicates the design. For example, when the first embodiment is incorporated into the flash memory, the word line voltage at the time of reading can be detected, but if the word line voltage at the time of writing is detected, the NMO is insufficient due to the insufficient withstand voltage of the NMOS 15.
Since S15 is destroyed, the word line voltage cannot be detected during writing. Alternatively, if the word line voltage at the time of writing is detected by mistake, the NMOS 15 is detected at this detection time.
Is destroyed, and nothing can be detected after that. That is, when the first and second embodiments are applied to the flash memory, the designer needs to correctly predict the magnitude of the measured voltage, but since 100% perfect prediction cannot be expected, the designer of The risk of destruction cannot be completely eliminated. In this respect, in the third embodiment, since a wide range of −3 V to +17 V can be detected by one circuit, there is no such risk, and there is a unique merit that the load at the time of design can be greatly reduced.
Therefore, it is possible to completely prevent the breakdown of the transistor due to the erroneous prediction (mis-estimation) of the voltage, and even if the voltage level is unexpectedly low, it can be detected without any trouble as long as it is -3 V or higher.

The first external power supply terminal 13 (113 or 213) and the second external power supply terminal 18 in each of the above-mentioned embodiments.
(118 or 218), external control terminal 16 (116 or 216) and external input terminal 21 (121 or 212)
May be a dedicated terminal, but considering that it is used only for the evaluation test, it is desirable that it is also used as another terminal.

[0042]

According to the present invention, only by monitoring the two currents flowing through the first and second current sections 3 and 4 and the input voltage of the second current section 4, the input of the first current section is detected. It is possible to indirectly detect the voltage of an arbitrary node connected to. Therefore, the voltage of an arbitrary node inside the device can be detected without using the probe contact method, and it is possible to provide a technique effective in preventing damage and improving the reliability of voltage detection.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment.

FIG. 3 is a main part configuration diagram of a flash memory to which the present invention is preferably applied.

FIG. 4 is a configuration diagram and an electrically equivalent circuit diagram of a memory cell transistor of a flash memory.

FIG. 5 is a configuration diagram of a second embodiment.

FIG. 6 is a configuration diagram of a third embodiment.

[Explanation of symbols]

1: Semiconductor integrated circuit 2: Node 3: First current section 4: Second current section 10: LSI chip (semiconductor integrated circuit) 11: First current section 12: Second current section 15, 20: NMOS 17: Node 110: LSI chip (semiconductor integrated circuit) 111: First current part 112: Second current section 115, 120: NMOS 117: Node 210: LSI chip (semiconductor integrated circuit) 211: First current section 212: Second current section 215, 220: NMOS 217: Node

Front page continued (51) Int.Cl. ⁷ identification code FI H01L 29/788 29/792 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/28 H01L 21/822 H01L 27/04 H01L 21/8247

Claims (4)

(57) [Claims] 1. A first current section (3) for flowing a current (Ia) having a magnitude corresponding to a voltage (Ea) of an arbitrary node (2) inside a semiconductor integrated circuit (1), and the first current section (3). A current part (3) and a second current part (4) having the same voltage / current characteristics, and the same current (Ib) as the current (Ia) flowing through the first current part (3) is The input voltage (Eb) of the second current portion (4) when flowing into the second current portion (4) is detected as corresponding to the voltage (Ea) of the arbitrary node (2). Semiconductor integrated circuit device. 2. The first current section and the second current section each include enhancement type N-channel MOS transistors (15, 20), and the drain current of each N-channel MOS transistor is set to the current (Ia). , (I
2. The semiconductor integrated circuit device according to claim 1, which is b). 3. An enhancement-type N-channel MOS transistor (115, 12) having a high threshold value and a high breakdown voltage, respectively, in the first current portion and the second current portion.
0), and the drain current of each N-channel MOS transistor is set to the currents (Ia) and (Ib). 4. A depletion type N-channel MOS transistor (215, 22) having a negative threshold voltage and a high breakdown voltage, respectively, in the first current portion and the second current portion.
0), and the drain current of each N-channel MOS transistor is set to the currents (Ia) and (Ib).