JPS58118091A - Semiconductor storing circuit - Google Patents

Abstract

PURPOSE:To establish data held until writing is performed to a preset value, after the power supply is turned on by delaying the power supply to the load of one driving transistor from that to the load of another driving transistor. CONSTITUTION:In the diagram, a power source VDD1 is raised to the VDD level at time t1. At this time, a gate input terminal 2 is at O level, because the VDD2 has the same electric potential as that the VSS has by the work of a delay circuit 6. Then, the power source VDD2 is raised to the VDD level at time t2. At this time, the electric potential of a terminal 2 is raised up only to the VL level, because a terminal 1 is held at the VDD level and a driving transistor T4 is conductive, and, therefore, an electric current flows to the driving transistor T4 through a load transistor T3. Therefore, a driving transistor T2 is left non-conductive, and the terminal 1 maintains the VDD level. In this way, it is sure that the terminal 1 maintains the VDD level at time T3 elapsed a prescribed time after the power supply is turned on, and thus, the uncertainly of data is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit (memory) composed of transistors.

FIG. 1 shows a configuration example of a memory cell of a conventional MOS static random access memory (hereinafter referred to as MMol-3-RA).

In this figure, T1. T3 is a pair of load transistors consisting of depletion type (hereinafter referred to as DMO3) transistors; T2. T4 is the transistor TI,
This is a pair of drive transistors consisting of an enhancement type MO3 (hereinafter referred to as 1MO8) transistor which together with T3 constitutes a flip-flop.

1 is a gate input terminal, which includes the gate and source of the load transistor T1, the drain of the drive transistor T2,
It is also connected to the gate of the drive transistor T4. 2 is also a gate input terminal and is connected to the gate and source of the load transistor T3, the drain of the drive transistor T4, and the gate of the drive transistor T2.

'f, the drains of the load transistors TI and T3 are both connected to the power supply VDD, and the drains of the load transistors T2 and T3 are connected to the power supply VDD.
．． Both sources of T4 are connected to ground potential VS5. Then, each of the terminals 1 and 2 is removed, and furthermore, 1M
A transmission gate transistor T5. fulfills all the functions of a gate circuit consisting of an O8 transistor. The gates of the transmission gate transistors T5 and T6 are both connected to the word line 5 through T6.

To explain, when the potential of terminal 1 is equal to VDD,
The drive transistor T4 becomes conductive, and the potential of the gate input terminal 2 falls below the threshold potential of the drive transistor T2.

Conversely, when the potential of the terminal 2 is equal to vnn, the drive transistor T2 becomes conductive, and the potential of the terminal 1 falls below the threshold potential of the drive transistor T4. In this way, by maintaining complementary potentials between terminals 1 and 2, one bit of data is stored.

However, in such a conventional MOS-8-RAM, the drains of the load transistors T1 and Ts are connected to a common power supply vnn, so when this power supply VDI) is turned on, the paired transistors TI, T2 and Ts
, T4, the levels of terminals 1 and 2 cannot be completely determined. Therefore, there is a drawback that the read data cannot be determined to a constant value after the power is turned on.

In addition, as a method for alleviating the above-mentioned defects, the above-mentioned T1 to T
It is also conceivable to determine the level of terminal 1.degree. 2 when the power is turned on by changing the dimensions of transistor 4 to make it asymmetrical. However, in this case, the levels of terminals 1 and 2 become asymmetrical, which affects the sense amplifiers connected to data lines 3 and 4, slowing down the read response speed, or causing problems in semiconductor manufacturing for determining data. There were drawbacks such as an increase in the number of types of masks available.

In addition, conventionally, the above-mentioned drawbacks have been solved by using an N-channel E/D MOS circuit as shown in FIG.
Not only MO3-8-RAM but also MOS-3- constituted by P channel or E/E MOS circuit.
A similar problem existed in RAM as well.

The present invention has been made in order to eliminate all the drawbacks of the conventional art, and after the power is turned on, the data stored at n+1 can be fixed to a preset value.
The object of the present invention is to provide a semiconductor memory circuit such as a MOS-8-RAM that can perform the same function as writing after power is turned on, and can maintain the symmetry of each transistor.

A semiconductor memory circuit according to the present invention includes a pair of drive transistors and a pair of loads each having one end connected to a power supply and the other end connected to the drive transistor, and the drive transistor side of each load. In a memory circuit that stores all data by keeping terminals at complementary potentials, when the power is turned on, the entire power supply to one of the loads is delayed, and the data terminal after the power is turned on is delayed from the power supply to the other load. This will fix the previously set value.

Hereinafter, the present invention will be explained in more detail based on embodiments shown in the drawings.

FIG. 2 shows an embodiment in which the present invention is applied to a MOS-5-RAM, in which load transistors T1. Ts, drive transistor T2. T4. Gate input terminal 1.2, transmission gate transistor T5. T6. The ground voltage 6, VSS, data lines 3 and 4, and word line 6 have exactly the same structure as in the conventional example shown in FIG.

The drain of the load transistor T1 is connected to the power supply vDD.
The drain of the load transistor T3 is connected to the power supply VDD 2.

Here, the power supply VDD 2 is set using a delay circuit 6 for a period of 9 hours after the power is turned on. , power supply V, )D is a power supply delayed from 1. Also, when VDD 2 overshoots, the capacitive load 7
Inserted between n2 and ground potential VSSO.

Note that the total threshold voltage VTD of the load transistors TI and T3
(VTD < O) + WE movement) LA7 register T
2. Threshold voltage f Vt+i (VTK >
O), when the drain output voltage of the drive transistor 2i7y[T4 when the input voltage at the gate of T4 is vnn, the drain output voltage 1vL (vTI:>Vl,) OL after the rise of the power supplies VDn 1 and Vnn 2 becomes sufficiently stable. It is assumed that the potential f Vnn (VDn>0) and the ground potential Vss==O.

Next, the entire operation of this embodiment will be explained using a signal waveform diagram shown in Figure 3.

7"-' 1. At the time of "to" in FIG. 3, the power supply VDD11
B OF F state, T'E 9 VDD I = Vs
There is sf. At this time, the sources of the load transistors TI and T3 are in PN junction with the substrate, so their potential is V
Since it does not fall below Bs, the load transistor TI.

T3 is in a conductive state. Therefore, terminal 1.2
is at the same potential as VSg, as shown in FIGS.

Further, as shown in FIG. 3(E), in the period from tO to t5, the word line 5 is also maintained at the 0 level i*nVL level.

Next, at time t1, the power supply is raised to the level 'Vnn 1 f Vnn.

At this time, due to the function of the delay circuit 6, VDD2 becomes V
Since it is at the same potential as Sg, gate input terminal 2 is at 0 level. Therefore, the drive transistor T2 is in a non-conducting state.
Since current flows through the load transistor T1 and charges are accumulated at the gate of the driving transistor T4, the potential at the terminal 1 rises to the VDD level. As a result, the drive transistor T4 becomes conductive, but since the power supply Vnn2 is still at the O level, the O level is still maintained at the terminal 2.
The drive transistor T2 is kept non-conductive.

Next, at time t2, the power supply VDD 2 rises to the VDD level. At this time, since terminal 1 is kept at the VDD level and drive transistor T4 is in a conductive state, current flows to drive transistor T4 through load transistor T3'j5, so that the potential of terminal 2 changes to VB. The soil only reaches the level. Therefore, drive transistor T2[
11 is in a non-conductive state, and terminal 1 maintains the full Vnn level. In this way, at time T3, which is a predetermined time after the power is turned on, the terminal 1 is always maintained at the VDD level, and data uncertainty is resolved.

Note that after the power is turned on, until writing is performed, terminal 2 is
If you want to maintain the perfect VDn level, the drains of the load transistors TI and T3 and the power supplies VDD 1 and V
Connection relationship with nn 2? Just reverse the procedure shown in Figure 2.

-f, and, as is clear from the above explanation, in such a MOS and 5-RAM with all cells integrated, T3 (7
) Dray 7k, so nzo n power supply VOID I, VD
Depending on which of the load transistors T2 is connected to, it can be determined whether the data at each address is set to "O" or "1" immediately after power is turned on.Then, the load transistor T
, T 3 ,! : VDD I, VDD 2
In an actual circuit, the selection of the connection relationship with the power supply can be made simply by selecting the power supply aluminum wiring.

Note that the present invention is applicable to N-channel E/
As is clear from the above description, the present invention can be applied not only to semiconductor memory circuits composed of DMOS circuits, but also to semiconductor memory circuits composed of P-channel or HE/EMO8 circuits. In the semiconductor memory circuit, the following effects can be obtained by delaying the power supply to the load of the second drive transistor and the power supply to the load of the second drive transistor.

(b) After the power is turned on, the data stored until writing is performed can be fixed at a preset value. Performs the same function. Therefore, computers, especially microcomputers? If used as a memory element in an applied device, there is no need to distinguish between RAM and ROM, and the memory unit can be configured with a single type of memory element, and the initial setting program can be omitted. It becomes possible.

(b) Since the symmetrical structure of each transistor constituting the entire memory circuit can be maintained, the read/write speed is not adversely affected and the variety of semiconductor manufacturing masters for data processing is not increased.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a conventional MOS+-5-RAM cell, FIG. 2 is a circuit configuration diagram of a semiconductor memory circuit according to an embodiment of the present invention, and FIG. 3 is a signal waveform diagram in the embodiment. . TI, T3...DMO3 load transistor, T
2. 'r4...EMO3 drive transistor, T
5゜111"-2 T6... EMO3 transmission gate transistor, V
III11+VDD2...Power supply, VSS...
...Ground potential, 1,2...Gate input terminal,
3, 4...Data line, 6...Word line,
6... Delay circuit, 7... Capacitive load. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 to tt tz tJ

Claims (1)

[Claims] a pair of drive transistors; a pair of loads each having one end connected to a gold power source and the other end connected to the drive transistor;
A semiconductor memory circuit characterized in that, when power is turned on, power is supplied to one of the loads, and a delay means is provided for delaying power supply to the other load.