JPS6263354A - Hang-up detecting system - Google Patents

Abstract

PURPOSE:To detect rapidly the hang-up concerning the main memory access in the minimum monitoring time by resetting the clocking means such as the counter and starting the clocking when the condition display of the memory bank designated by the address is changed from the unused condition display to the using condition display. CONSTITUTION:A bank condition detecting circuit 6 connected to a request buffer register 10 for the test is the same as the conventional one, branches the output of an OR gate 16 of the circuit and connects to a flip-flop 21 to generate the signal for controlling a counter 20 which is a clocking means. The flip-flop 21 generates the resetting pulse of the counter 20 together with a flip-flop 22 and a gate 23. Thus, when the necessary address is set to the request buffer register 10, the condition display of the equivalent memory bank can be monitored and the hang-up can be detected rapidly.

Description

[Detailed Description of the Invention] [Summary] This is a control method for detecting a hang-up due to a failure in main memory access of a computer system. A test address is held in a register that holds an address for selecting the status display corresponding to a memory bank, and when the status display of the memory bank specified by the address changes from unused to in use, a counter, etc. By resetting the timer and starting timekeeping, a hang-up related to main memory access can be quickly detected with a minimum amount of monitoring time.

[Industrial application field]

The present invention provides main memory access in a computer system,
This invention relates to a control method for detecting hang-up due to failure.

A system is often used in which a storage device constituting a main memory or the like is divided into a plurality of storage banks so that accesses to different storage banks can be executed simultaneously and in parallel.

In a storage control device that controls access in this case, a status display is provided to indicate that the storage bank is in use for a predetermined access control time from the start of use of each storage bank,
Control subsequent access requests.

If such a system suffers a hang-up, in which the main memory is not accessed for a long time due to some kind of failure, access requests within the system will no longer be executed, so it should be detected as soon as possible. It is necessary to be able to collect information that is useful for investigating the cause.

[Conventional technology]

FIG. 2 is a block diagram showing an example of the configuration of a computer system.

Access source device 1 such as central processing unit, channel processing device, etc.
issues an access request to the storage control device 2 and accesses the storage device 3 under the control of the storage control device 2.

It is assumed that the storage device 3 is composed of a plurality of storage banks that can operate in parallel.

In the storage control device 2, corresponding to each access source device 1,
A request buffer register 4 is provided, and a request buffer register 1o is provided for testing. Further, a bank status display circuit 5 is provided which is composed of a latch corresponding to each storage bank and displays the unused/used status of each bank.

Note that the request buffer register 1o is provided for testing the storage control device 2 by, for example, setting a necessary access request from a service processor and attempting access in the same way as other request source devices.

The output signal of each latch of the bank status display circuit 5 is input to the bank status inspection circuit 6 for each request buffer register 4.10. This input signal is assumed to indicate that the corresponding storage bank is in use, for example, by an on signal.

When an access request is set in the request buffer register 4.10, the information in the access destination storage bank designation part in the request information is input to the bank status inspection circuit 6.
The output of the latch of the corresponding bank in the bank status display circuit 5 is selected, and its negation signal is input to the priority selection circuit 7. Therefore, when the storage bank to which the access is requested is displayed as unused, an on signal is input to the priority selection circuit 7.

The priority selection circuit 7 selects one of the simultaneously input requests using a predetermined logic and passes required request information of the request to the access control section 8, thereby performing a known method for accessing the storage device 3. Start control. At that stage, the request buffer register marked with receiving the request is disabled,
Subsequent requests can be issued.

The address of the specified storage bank of the access request selected by the priority selection circuit 7 is also passed to the status display control section 9. The status display control unit 9 turns on the latch of the corresponding bank in the bank status display circuit 5, and then resets the latch after a predetermined access control time has elapsed.

FIG. 3 is a block diagram showing the detailed structure of the part of the bank state inspection circuit 6 connected to the bank state display circuit 5 and the request buffer register 10 that is related to the above description.

In the bank status display circuit 5 shown in the figure, 11 is a latch that displays the status of each bank, and 12 is a latch that decodes the storage bank address from the status display control unit 9 to
A decoder 13 sets the display to be in use, and 13 is a decoder to reset the display to unused.

Further, in the bank state inspection circuit 6, the decoder 14 and the gate 15 select the output of the latch 11 for the specified storage bank address of the request buffer register 1°,
It is configured to gate the negative signal of the output of the OR gate 16 through a signal line 17 and output it to the priority selection circuit 7.

The output of the signal g17 is controlled by a valid bit signal indicating the validity of the contents of the request buffer register 10. This valid bit is reset by the priority selection circuit 7, for example, when the request is accepted.

[Problem to be solved by the invention] In the above configuration, a hang-up state related to main memory access occurs, such as when main memory access from the access requesting device does not occur or access is not completed due to some kind of failure. When this occurs, conventionally, the access source device monitors, for example, the time until the instruction is completed, and detects that the time is longer than a predetermined value.

This monitoring time needs to be long enough to avoid misjudging normal waiting times as failures, so prompt detection is not possible, and furthermore, there is a possibility that information for searching for the cause may be lost at the time of detection. There were some problems.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

In the figure, the bank state inspection circuit 6 connected to the test request buffer register 10 is the same as the conventional one, and the output of the OR gate 16 of this circuit is branched to run the counter 20 which is the time measuring means of the present invention. It is connected to a flip-flop 21 for generating a control signal.

Flip-flop 21, together with flip-flop 22 and gate 23, generates a reset pulse for counter 20.

[For production]

When a test address is set in the test request buffer register 10, the corresponding latch 11 of the bank status display circuit 5 is set.
output is selected.

When the bank is in use, the corresponding latch is set on.

When the latch 11 is on, the output of the corresponding gate 15 is turned on, and therefore the output of the OR gate 16 is turned on, so that the flip-flop 21 is turned on in the next control cycle.

In the next control cycle, the flip-flop 22 is also turned on in response to the output of the flip-flop 21, but during the previous control cycle, the output of the gate 23 was turned on, and this pulse signal resets the counter 20. ,
Start counting a predetermined time.

If the latch 11 corresponding to 8.0 is reset to off, the output of the OR gate 16 is turned off, so the flip-flop 21 and then the flip-flop 22 are reset.

If the latch 11 is not reset and therefore the flip-flop 22 remains set on, the counter 20 will overflow after a certain period of time and a signal will be output on the signal line 24 indicating the presence of a fault. I can do it.

In this configuration, by setting a required address in the request buffer register 10, it is possible to monitor the status display of the corresponding storage bank, and it is possible to quickly detect a hang-up.

〔Example〕

In FIG. 1, the bank status display circuit 5, bank status inspection circuit 6, priority selection circuit 7, status display control section 9, etc.
It is assumed that the operation is the same as in the conventional case.

When request information including a test address is set in the test request buffer register 10, a status check of the request destination storage bank is executed as in the past, and if the bank is unused,
A request is input to the priority selection circuit 7, and as a result, the corresponding latch 11 of the bank state display circuit 5 is set to the busy state.

By setting the latch 11, the output of the corresponding gate 15 is turned on, and therefore the output of the OR gate 16 is turned on, so the flip-flop 2 is turned on in the next control cycle.
1 turns on.

The flip-flop 21 is always set to the output state of the OR gate 16, and the flip-flop 22 is set to the output state of the flip-flop 21.

In the next control cycle, the flip-flop 22 is also turned on in response to the output of the flip-flop 21, but during the previous control cycle, the output of the gate 23 was turned on, and this pulse signal resets the counter 20. ,
Start counting a predetermined time.

Thereafter, if control proceeds normally and the corresponding latch 11 is reset to off, the output of the OR gate 16 is turned off, so the flip-flop 21 and then the flip-flop 22 are reset.

Thereafter, each time the bank is selected by another access request and the latch 11 is turned on, the counter 20 is reset in the same manner as described above.

This operation is repeated every time the priority selection circuit 7 selects an access request to the storage bank specified by the address part of the request puffer register 10 by itself or another request puffer register 4, and the counter 20
is reset on each iteration.

However, if the state of not being reset continues for a predetermined period of time, the counter 20 overflows and the signal is output to the signal line 24, which can be received by an appropriate control circuit and used as a trigger for starting troubleshooting.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, hang-ups in main memory access of a computer system can be solved by
Since it can be detected quickly, it has a significant industrial effect of increasing system availability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a computer system, and FIG. 3 is a block diagram of a conventional configuration. In the figure, 1 is an access source device, 2 is a storage control device, 3 is a storage device, 4.10 is a request buffer register, 5 is a bank status display circuit, 6 is a bank status inspection circuit, 7 is a priority selection circuit, and 8 is a Access control unit, 9 is status display control unit, 11 is lunch, 12, 13, 14 is decoder, 15 is gate, 16 is OR gate, 17
21 and 22 are flip-flops, 20 is a counter, and 23 is a gate.

Claims (1)

[Scope of Claims] A computer system receives an access request specifying a storage bank of a storage device from an access source device, and indicates whether the request destination storage bank is in use by displaying a status display ( 5) in a storage control device configured to inspect and identify the status, means (10) for holding an address for selecting the status display;
, selects the status display (5) corresponding to the address held in the address holding means (10), detects a change in the selected status display (5) from unused to in-use, and outputs a signal. A hang-up detection method characterized by comprising: means (21, 22, 23) for generating a detection signal, and a timekeeping means (20) for starting timekeeping from an initial state each time the detection signal is generated.