JPS6263349A - Memory access controlling system - Google Patents

Abstract

PURPOSE:To shorten the time required for partial writing, by setting updating data from a processor in a part of a register relevant to the partial writing at the timing when one word which is subjected to the partial writing is read out from a memory and set in the register and writing the data held by the register is the memory. CONSTITUTION:In the course of partial writing, a processor 2 reads one word to be written from a memory 1 to a data register 4. At the timing of this readout, updating data are sent to a data line 5 and, simultaneously, only writing data from the processor 2 corresponding to the updating sections 11-0-11-3 are made valid by means of a control line 13 by inhibiting the reading of data from the memory 1. Therefore, data of one word, in which readout data and updating data are combined, are set in the data register 4 at the timing when the data read out from the memory 1 are inputted to the data register 4. Therefore, control of the writing on the memory 1 can be started in succession to the readout and the processing cycle of partial writing can be extensively shortened.

Description

[Detailed Description of the Invention] [Summary] This is an access control method for controlling partial writing to local memory, etc. At the timing when a word to be partially written is read from the memory and set in a register, update data from the processor is set in the part of the register corresponding to the partial write, and the data held in the register in this way is transferred to the memory. Write to. With this configuration, the processing time for partial writing can be shortened.

[Industrial application field]

The present invention relates to an access control method for controlling partial writing of a memory such as a local memory in a processing device of a computer system.

A so-called partial write, in which a part of one word of data, which is the unit of reading/writing data in memory, is updated is a process in which information is Often executed during processing.

Such partial write processing involves reading the one word from memory, updating the required part of the read data, and then
Since it requires a step to write the data to memory,
Access time tends to be relatively long.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram showing an example of the configuration of the memory device 6. As shown in FIG.

In the figure, memory 1 is a so-called local memory that processor 2 uses, for example, as a work area.

The memory 1 has a configuration in which one word is made up of 4 bytes, for example, and reads data at a word address set in the address register 3 from the processor 2 and sets it in the data register 4.
The contents of the data register 4 are transferred to the processor 2 for processing.

Also, in a write operation, the memory device 6 is
By switching the selector 8 using the control line 7 and setting it in the data register 4 to generate a write signal, one word of write data transferred by the data line 5 is transferred to the word address specified by the address register 3. The data is configured to be written.

Therefore, in the case of partial writing, one edict is first read into the data register 4, the processor 2 creates data by updating the required part of this data, and the processor 2 transfers this data to the data register 4, and then performs the write operation. I do.

FIG. 3 (al) is a diagram explaining the control timing of this partial writing.

When the READ instruction of the microinstruction of the processor 2 is executed in the first control cycle (hereinafter referred to as the first cycle, etc.), address calculation etc. are performed, and the address register 3 is set in the second cycle, and read The operation is started and the read data is transferred to data register 4 in the third cycle.
is set to

In line with this timing, processor 2 waits for the second cycle with a dummy NOP instruction, and then waits for the third cycle's L
By executing the OAD instruction, the data in the data register 4 is fetched into a register in the processor 2 at the end of the cycle, and the data fetched by the next MERGE instruction and the partial write data are merged to form write data.

By executing the 5TOPE instruction in the fifth cycle, this one word of merged data is set in the data register 4 at the end of the cycle. In the sixth cycle, a WRITE command is executed to start writing and calculate the address, and in the seventh cycle, the contents of the data register 4 are written to the address set, and the partial write is completed.

As mentioned above, it is necessary to spend 7 control cycles (however, in the 7th cycle, the next instruction can be processed in parallel, so the effective number of cycles is 6 cycles) for memory access processing for partial writing. Therefore, it has been desired to shorten this time and improve the processing capacity of the system.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

° The figure shows the configuration of the memory device 10, 11-O to 11
-3 is a selector that switches the passage of one byte each of data read from the memory 1 and write data.

The selectors 11-0 to 11-3 are controlled by a control line 13 from the processor 2.

[For production]

In partial writing, processor 2 writes one of the writing targets.
The word is read from memory 1 into data register 4.

At this time, the updated data is sent to the data line 5, and at the same time, the control line 13 blocks the read data of the memory 1 only for those corresponding to the updated part of the selectors 11-0 to 11-3. Enable write data.

Therefore, at the timing when the read data from the memory 1 is input to the data register 4, one word of data, which is a combination of the read data and the update data, is set in the data register 4.

As described above, writing control to the memory 1 can be started following reading, and the processing cycle for partial writing can be significantly shortened.

[Embodiment] In FIG. 1, the selectors 11-O to 11-3 pass the read data from the memory l to the data register 4 when the control line 13 is off, and therefore
Control of reading or writing words is performed in the conventional manner.

Control of partial writing will be explained with reference to the timing diagram of FIG. 3(b).

In a partial write, processor 2 writes R in the first cycle.
When the EAD instruction is executed, a read operation similar to the conventional one is started in memory l, and one word of data is read from the address determined in the second cycle.If it is a normal read operation, the read data is transferred to the third data register 4 in cycle
is set to

In the case of partial writing, the processor 2 sends the update data to the required hide position of the data line 5 by executing the 5TOPIE instruction in parallel in the second cycle, and at the same time controls the signal vA13 to select the data of the update byte. so that the update data passes through the selectors 11-0 to 11-3.

Therefore, at the timing of the third cycle when the read data from the memory 1 is input to the data register 4, one word of data obtained by merging the read data and the update data is set in the data register 4.

In parallel, processor 2 performs WRIT in the third cycle.
By executing the E instruction, the merged data on data register 4 is written to memory l in the fourth cycle, completing the partial write. That is, the partial write process that required six effective cycles in the conventional example is shortened to three effective cycles (the fourth cycle is parallel to the processing of the next instruction).

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the processing time for partial memory writing in a computer processing device or the like is significantly shortened, so that there is a significant industrial effect of improving the performance of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a conventional configuration, and FIG. 3 is a timing diagram. In the figure, 1 is memory, 2 is processor, 3 is address register, 4 is data register, 5 is data line,
6.10 is a memory device, and 7.13 is a control line 8.11-0 to 11-3 are selectors.

Claims (1)

[Claims] When writing data from the processor (2) to the memory (1), a register (4) that holds read data from the memory (1); and a register (4) that holds the data read from the memory (1); and the register (
The register (4) is set in synchronization with the timing set in the register (4).
) has means (11-0 to 11-3) for setting data to be written from the processor, and the register (4)
1. A memory access control system characterized by being configured to write data set in the memory (1).