JPS6262523A - Pattern forming method - Google Patents

Pattern forming method

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Publication number
JPS6262523A
JPS6262523A JP60201751A JP20175185A JPS6262523A JP S6262523 A JPS6262523 A JP S6262523A JP 60201751 A JP60201751 A JP 60201751A JP 20175185 A JP20175185 A JP 20175185A JP S6262523 A JPS6262523 A JP S6262523A
Authority
JP
Japan
Prior art keywords
resist
preventive film
pattern
film
baking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60201751A
Other languages
Japanese (ja)
Inventor
Minoru Takeda
実 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP60201751A priority Critical patent/JPS6262523A/en
Publication of JPS6262523A publication Critical patent/JPS6262523A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To largely improve the stability and reliability of forming a pattern by sufficiently baking a reflection preventive film at high temperature, then drying the coating resist in vacuum, further exposing, developing and etching to prevent the resist from deforming. CONSTITUTION:In a method of forming a pattern having the step I of forming a reflection preventive film on an article to be etched, the step III of forming a resist layer on the reflection preventive film, the step V of exposing and developing the resist layer to pattern it, and the step VI of selectively etching the article, the step II of baking in advance at high temperature so as not to remove the preventive film by developing the resist layer and the step IV of drying in vacuum the resist layer are provided. In other words, the reflection preventive film is applied on a high reflection metal base layer, sufficiently baked at high temperature, the resist layer is applied, dried in vacuum, exposed and then developed to form a resist pattern, and the preventive film and the base layer are eventually etched by reactive ion etching by allowing the preventive film to remain.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、パターン形成方法に関する。本発明のパター
ン形成方法は、例えば半導体装置の製造(超LSIの製
造)などに適用することができる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern forming method. The pattern forming method of the present invention can be applied, for example, to manufacturing semiconductor devices (manufacturing very large scale integrated circuits).

〔発明の概要〕[Summary of the invention]

本発明はパターン形成方法において、反射防止膜を高温
で十分にペイキングしてから、塗布されたレジストを真
空乾燥し、さらに露光、現像、エツチングを行うことに
より、レジストの変形を防止してパターン形成の安定性
、信頼性を大幅に向上させるようにしたものである。
In the pattern forming method of the present invention, the anti-reflection film is sufficiently baked at high temperature, the applied resist is vacuum-dried, and further exposed, developed, and etched to prevent deformation of the resist and form a pattern. This greatly improves the stability and reliability of the system.

〔従来の技術〕[Conventional technology]

従来、高反射性の下地層(被エツチング物)上に微細パ
ターンを形成する場合、反射防止膜の塗布とペイキング
、レジストの塗布とペイキングを順次行った後で、露光
、現像を行い、現像と同時に下地層を含めた各層を一時
に除去することが行われていた。
Conventionally, when forming a fine pattern on a highly reflective underlayer (object to be etched), an anti-reflection film is applied and painted, a resist is applied and painted in sequence, and then exposure and development are performed. At the same time, each layer including the base layer was removed at the same time.

即ち従来、半導体基板上にAβ等の金属配線をパターニ
ングする場合は、半導体基板上にへ!等の金属下+I!
層を積層形成してから該下地層上に直接ポジ型フォトレ
ジストを塗布し、さらに所定のマスクを用いて露光する
ことが行われていた。しかし、A1の下地層は高反射性
を有しているため・露光が不十分となる恐れがあった。
That is, conventionally, when patterning metal wiring such as Aβ on a semiconductor substrate, it is necessary to pattern the metal wiring on the semiconductor substrate! etc. under metal +I!
After laminating layers, a positive type photoresist is applied directly onto the underlayer, and then exposed using a predetermined mask. However, since the base layer of A1 has high reflectivity, there was a risk that the exposure would be insufficient.

このようなところから、下地層の上に反射防止膜、例え
ばARC(B rewer S cience社の商品
名、ポリイミド主体)を直接塗布してから該反射防止膜
を所定の温度(168℃)でペイキングしたうえで、該
反射防止膜上に塗布したレジストを90〜100℃でペ
イキングし、さらに縮小投影露光装置によって露光、現
像する時に該反射防止膜とA1下地層を溶かしてしまう
方法が行われていた。この方法は、該反射防止膜がレジ
ストの現像液であるアルカリ現像液に可溶であり、ヘイ
キング温度が高くなる程現像速度が低下して硬化し、低
くなる程現像速度が増大して可溶性が増大するという特
性を利用して、該反射防止膜のアルカリ現像液に対する
溶解速度を該反射防止膜のペイキング温度を制御するこ
とによって調整するものである。この方法によれば4.
該反射防止膜をある最適の温度で均一に焼成することに
よって、レジスト現像時に下地層まで溶解することがで
きる。しかしながらこのヘイキング温度制御による方法
は、大口径のウヱハーにおいては、仮に高精度のペイキ
ング装置を用いたとしても均一焼成が困難であるため場
所によってペイキングの程度にバラツキが発生し、ある
部分では該反射防止膜の熔解速度が早いために現像後に
該反射防止膜のアンダーカットが大きくなって上層のレ
ジストが剥離したり、他の部分では溶解速度が遅くなっ
て現像後に該反射防止膜が、残留してスカムを生じさせ
るというように、プロセスの安定性、信頼性の点で問題
があった。第3図は反射防止膜にアンダーカットが形成
された状態を示し、符号2は下地層、3はアンダーカッ
トが形成された反射防止膜、4はレジストをそれぞれ示
す。また、溶解速度の早い部分(現像温度の低い部分)
では、レジストとARCとの密着性が悪いためにARC
に僅かのアンダーカットが入っただけでも、レジストと
の接触面積の低下によりレジストが剥離を起こしてパタ
ーニングの安定性と信頼性を低下させることが多かった
For this reason, an anti-reflective film such as ARC (trade name of Brewer Science, mainly made of polyimide) is applied directly onto the base layer, and then the anti-reflective film is baked at a predetermined temperature (168°C). After that, the resist coated on the anti-reflection film is baked at 90 to 100°C, and then the anti-reflection film and the A1 underlayer are melted when exposed and developed using a reduction projection exposure device. Ta. In this method, the antireflection film is soluble in an alkaline developer that is a resist developer, and as the haking temperature increases, the development speed decreases and hardens; Taking advantage of this property of increasing the amount of water, the dissolution rate of the antireflective film in an alkaline developer is adjusted by controlling the baking temperature of the antireflective film. According to this method, 4.
By uniformly baking the antireflection film at a certain optimum temperature, even the underlying layer can be dissolved during resist development. However, with this method of controlling the baking temperature, it is difficult to achieve uniform baking in large-diameter wafers even if a high-precision baking device is used, so the degree of baking varies depending on the location, and in some areas the reflection The dissolution rate of the anti-reflective film is fast, so the undercut of the anti-reflective film becomes large after development and the upper resist layer peels off, and the dissolution rate becomes slow in other areas, causing the anti-reflective film to remain after development. There were problems with the stability and reliability of the process, such as the formation of scum. FIG. 3 shows a state in which an undercut is formed in the antireflection film, where 2 represents the base layer, 3 represents the antireflection film with the undercut, and 4 represents the resist. Also, areas where the dissolution rate is fast (areas where the developing temperature is low)
Then, due to poor adhesion between the resist and the ARC, the ARC
Even a slight undercut in the pattern often causes the resist to peel off due to a decrease in the contact area with the resist, reducing the stability and reliability of patterning.

また、反射防止膜を約168℃でへイキングする従来の
方法では反射防止膜の硬化が十分でなく、レジストをペ
イキングするときに両者の界面で混合が起こり、その結
果、現像後のレジストの形状が第3図に示すように据広
がりになる虞れがあった。このような形状は、パターニ
ングの精度上問題であるばかりでなく、プロセスとして
の解像力を低下させるという点でも問題であった。
In addition, with the conventional method of baking the anti-reflective film at about 168°C, the anti-reflective film is not sufficiently cured, and when the resist is baked, mixing occurs at the interface between the two, resulting in the shape of the resist after development. However, as shown in Figure 3, there was a risk that the area would become stagnant. Such a shape not only poses a problem in terms of patterning accuracy, but also in that it reduces the resolution of the process.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来技術には、反射防止膜全面に対する
ペイキング温度を均一に制御することが困難であったた
めにレジストと反射防止膜との密着性にバラツキが発生
しパターニングの安定性と信頼性が低下するという問題
と、反射防止膜とレジストをペイキングしただけでは両
者の界面における混合を防止することができないために
現像後にレジストの形状が劣化して種々の不都合を生し
させるという問題があった。
As mentioned above, in the conventional technology, it was difficult to uniformly control the paking temperature over the entire surface of the anti-reflective film, which caused variations in the adhesion between the resist and the anti-reflective film, resulting in poor patterning stability and reliability. Another problem was that simply painting the anti-reflection film and resist cannot prevent mixing at the interface between the two, resulting in deterioration of the shape of the resist after development, resulting in various inconveniences. .

本発明の目的は、反射防止膜を均一に高温へイキングし
てからレジストを真空乾燥することによってレジストと
反射防止膜の剥離及びレジストの形状の劣化を防止して
パターニングの安定性と信頼性を向上させることができ
るパターン形成方法を提供するものである。
The purpose of the present invention is to uniformly heat the anti-reflective film to a high temperature and then dry the resist in vacuum, thereby preventing peeling of the resist from the anti-reflective film and deterioration of the shape of the resist, thereby improving the stability and reliability of patterning. The present invention provides a pattern forming method that can be improved.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のパターン形成方法は、第1図に例示の如く被エ
ツチング物上に反射防止膜を形成する工程Iと、該反射
防止膜上にレジスト層を形成する工程■と、該レジスト
層を露光、現像してパターニングする工程■と、該被エ
ツチング物を選択的にエツチングする工程■とを有する
パターン形成方法において、前記レジスト層の現像によ
って前記反射防止膜が除去されないように予め高温焼成
する工程nと、前記レジスト層を真空乾燥する工程1■
とを有することによって上記目的を達成することができ
る。
The pattern forming method of the present invention includes a step I of forming an antireflection film on an object to be etched, a step II of forming a resist layer on the antireflection film, and exposing the resist layer to light, as illustrated in FIG. , a pattern forming method comprising a step of developing and patterning; and a step of selectively etching the object to be etched; Step 1 of vacuum drying the resist layer
The above object can be achieved by having the following.

〔発明の作用〕[Action of the invention]

すなわち本発明は、反射防止膜を高反射金属下地層上に
塗布して十分に高温でへイキングし、レジスト層を塗布
形成後真空乾燥してから露光、現像することによってレ
ジストパターンの形成を行い、最後に反射防止膜を残し
たまま反応性イオンエツチング(RI E)で反射防止
膜、下地層のエツチングを行う・ようにしたため、反射
防止膜のペイキング温度制御の困難性を原因とした不均
一ペイキングに基(レジストと反射防止膜との剥離、及
び反射防止膜とレジストとの界面における混合を原因と
したレジストの形状劣化を防止してパターニングの精度
を向上させることができる。
That is, in the present invention, a resist pattern is formed by coating an antireflection film on a highly reflective metal base layer, baking it at a sufficiently high temperature, and applying and drying a resist layer in vacuum, followed by exposure and development. Finally, the anti-reflective film and the underlying layer were etched using reactive ion etching (RIE) while leaving the anti-reflective film, resulting in non-uniformity due to the difficulty in controlling the baking temperature of the anti-reflective film. Based on paking, patterning accuracy can be improved by preventing deterioration of the shape of the resist caused by peeling of the resist and anti-reflection film and mixing at the interface between the anti-reflection film and resist.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明のパターン形成方法について詳細に説明す
る。
Hereinafter, the pattern forming method of the present invention will be explained in detail.

第1図は本発明方法のフロー図、第2図(イ)〜(へ)
は本発明方法の一実施例の工程説明図である。この実施
例においては、第2図(イ)に示すようにSi等の半導
体基板1上にAlからなる間反射性の下地N(被エツチ
ング物)2を積層形成したものを処理する場合について
説明する(第2図(イ)は、第1図の工程I前の状態を
示す。)。
Fig. 1 is a flow diagram of the method of the present invention, Fig. 2 (a) to (f)
1 is a process explanatory diagram of an embodiment of the method of the present invention. In this embodiment, as shown in FIG. 2(A), a case will be explained in which a reflective base N (object to be etched) 2 made of Al is laminated on a semiconductor substrate 1 made of Si or the like. (FIG. 2(a) shows the state before step I in FIG. 1.)

第2図(ロ)は、ARCから成る反射防止膜3を/l下
地N2上に回転塗布(工程ILLだあと高温ペイキング
する工程■を示す。ペイキング温度としては180〜1
90℃が好ましい。このような高温へイキングによれば
均一なペイキングが可能であり、高温へイキングによっ
て反射防止膜3を全面的に硬化させることによって、次
工程で塗布されるポジレジストのアルカリ現像液に対す
る可溶性を低下させることができる。
Fig. 2 (B) shows the step (2) of spin-coating the anti-reflection film 3 made of ARC on the base N2 (process ILL) and then high-temperature painting.The baking temperature is 180-1
90°C is preferred. Such high-temperature baking enables uniform baking, and by curing the anti-reflection film 3 on the entire surface by high-temperature baking, the solubility of the positive resist to be applied in the next step in an alkaline developer is reduced. can be done.

第2図(ハ)は、ポジレジスト(層)4を反射防止膜3
上に塗布形成したあと真空乾燥によってレジスト中の溶
剤を除去する工程[[[、IV後の状態を示す。真空乾
燥温度としては約25℃が好ましい。反射防止膜3の高
温ペイキングとポジレジスト4の真空乾燥は何れも必須
であり、一方が欠けても十分な効果を得ることはできな
い。ポジレジスト4は後のエツチング除去においてマス
クとして使用されるため、その膜厚は反射防止膜よりも
十分に厚く構成する。
Figure 2 (c) shows a positive resist (layer) 4 and an anti-reflection film 3.
The process of removing the solvent in the resist by vacuum drying after coating on the resist [[[, shows the state after IV. The vacuum drying temperature is preferably about 25°C. Both high-temperature baking of the antireflection film 3 and vacuum drying of the positive resist 4 are essential, and even if one of them is missing, sufficient effects cannot be obtained. Since the positive resist 4 is used as a mask in the subsequent etching removal, its film thickness is made sufficiently thicker than the antireflection film.

第2図(ニ)は、マスク5を用いてポジレジスト4を露
光する工程を示す。
FIG. 2(d) shows a step of exposing the positive resist 4 using the mask 5. As shown in FIG.

第2図(ホ)は、レジストの形状保持のためのPEB 
(Post Exposure Baking )工程
を示し、この工程を経ることによってレジストの肩部が
丸くなることを防止することができる。FEBの温度と
しては、80°C程度が好ましい。FEBは露光後に行
われるため、反射防止膜とレジストとが混合する虞れは
殆どない。
Figure 2 (e) shows the PEB used to maintain the shape of the resist.
(Post Exposure Baking) This step can prevent the shoulders of the resist from becoming rounded. The temperature of FEB is preferably about 80°C. Since FEB is performed after exposure, there is almost no possibility that the antireflection film and resist will mix.

第2図(へ)は、ポジレジスト4を現像後の構造を示す
。この工程■において反射防止膜上にレジストパターン
が形成される。
FIG. 2(f) shows the structure after the positive resist 4 is developed. In this step (2), a resist pattern is formed on the antireflection film.

第2図(+・)(チ)は、RI E (Reactiv
eI on  E Lching)法によって反射防止
膜3とA6下地層2を順次選択的に異方性エツチングす
る工程■を示す。レジスト4の膜厚は反射防止膜の膜厚
よりも十分に厚いのでレジストをマスクとして反射防止
膜のエツチングが行われる。RIEにおいては、例えば
ciq系イオンを使用する。
Figure 2 (+・) (ch) shows RI E (Reactive
The process (2) is shown in which the antireflection film 3 and the A6 underlayer 2 are sequentially and selectively anisotropically etched by the eI on E Lching method. Since the thickness of the resist 4 is sufficiently thicker than that of the antireflection film, the antireflection film is etched using the resist as a mask. In RIE, for example, ciq-based ions are used.

第2図(す)は、レジスト4と反射防止膜3を酸素プラ
ズマで剥離除去する工程■を示す。この工程は下地層2
が完全にエツチング除去された後に行われる。
FIG. 2(S) shows step (2) in which the resist 4 and antireflection film 3 are peeled off and removed using oxygen plasma. This process is the base layer 2
This is done after the etching has been completely removed.

第2図(ヌ)は、A1配線バターシ石成された状態を示
す。
FIG. 2 (N) shows the state in which the A1 wiring batashite is formed.

以上のように本発明方法においては、反射防止膜3を高
温ペイキングで均一に加熱硬化させてから、その上に塗
布されるレジストの現像液を真空乾燥で除去することに
よって両層の界面における混合を防ぐと同時にレジスト
4の現像後に反射防止I+733を全面的に残留させ、
さらにRIEによって反射防止膜3及び下地層2の除去
を順次行うようにしたため、ヘイキングのバラツキに基
く不要な反射防止膜の残留や、反射防止膜とレジストと
の密着不良や、レジストの形状の劣化(裾引き)を原因
としたパターニングの安定性及び信鎖性の低下を防ぐこ
とができる。また、反射防止膜の反射防止効果を十分に
発揮させて下地層の反射の影響を受けることなく高精度
な配線パターンを形成することができる。
As described above, in the method of the present invention, the antireflection film 3 is uniformly heated and cured by high-temperature baking, and then the developer of the resist applied thereon is removed by vacuum drying, thereby mixing at the interface between the two layers. At the same time, after developing resist 4, anti-reflection I+733 remains on the entire surface,
Furthermore, since the anti-reflective film 3 and the base layer 2 are sequentially removed by RIE, unnecessary anti-reflective film remains due to variations in hazing, poor adhesion between the anti-reflective film and the resist, and deterioration of the shape of the resist. Deterioration of patterning stability and reliability due to (hemming) can be prevented. Moreover, the antireflection effect of the antireflection film can be fully exhibited, and a highly accurate wiring pattern can be formed without being affected by reflection from the underlying layer.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明のパターン形成方法によれば、ペイ
キング温度のバラツキに基く不要な反射防止膜の残留や
、反射防止膜とレジストとの密着不良や、レジストの形
状の劣化を原因としてパターニングの安定性及び信鎖性
の低下を防ぐことができ、さらにはプロセスとしての解
像度の低下を防止することができる。
As described above, according to the pattern forming method of the present invention, patterning is prevented due to unnecessary residual anti-reflective film due to variations in paking temperature, poor adhesion between the anti-reflective film and resist, and deterioration of resist shape. Deterioration in stability and reliability can be prevented, and furthermore, deterioration in resolution as a process can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法の工程を示すフロー図、第2図(イ
)〜(ヌ)は本発明方法の一実施例の工程説明図であり
、(イ)はプロセス開始前の状態、(ロ)は反射防止膜
塗布及び高温焼成工程、(ハ)はレジスト塗布及び真空
乾燥工程、(ニ)は露光工程、(ホ)はFEB工程、(
へ)は現像工程、(ト)(チ)はエソチング工程、(す
)はレジスト剥離工程、(ヌ)は完成状態をそれぞれ示
す。 第3図は従来のパターン形成方法において反射防止膜及
びレジストの形状が劣化した状態を示す。 1・・・・・−半導体基板、 2−・−・−・高反射金
属下地層、3・−・−・・−反射防止膜、 4・・・−
レジスト、 5・−・−・−マスク。
FIG. 1 is a flow diagram showing the steps of the method of the present invention, and FIGS. B) is an anti-reflection film coating and high temperature baking process, (C) is a resist coating and vacuum drying process, (D) is an exposure process, (E) is an FEB process, (
(f) shows the developing process, (g) and (ch) show the etching process, (su) shows the resist stripping process, and (nu) shows the completed state. FIG. 3 shows a state in which the shapes of the antireflection film and the resist have deteriorated in the conventional pattern forming method. 1...- Semiconductor substrate, 2---- Highly reflective metal underlayer, 3-- Anti-reflection film, 4--
Resist, 5・−・−・−Mask.

Claims (1)

【特許請求の範囲】 1、被エッチング物上に反射防止膜を形成する工程と、 該反射防止膜上にレジスト層を形成する工 程と、 該レジスト層を露光、現像してパターニン グする工程と、 該被エッチング物を選択的にエッチングす る工程とを有するパターン形成方法において、前記レジ
スト層の現像によって前記反射防 止膜が除去されないように予め高温焼成する工程と、 前記レジスト層を真空乾燥する工程を有す ることを特徴とするパターン形成方法。
[Claims] 1. A step of forming an anti-reflection film on an object to be etched, a step of forming a resist layer on the anti-reflection film, and a step of patterning the resist layer by exposing and developing it. The pattern forming method includes the step of selectively etching the object to be etched, the step of pre-baking at a high temperature so that the anti-reflection film is not removed by developing the resist layer, and the step of vacuum-drying the resist layer. A pattern forming method characterized by comprising:
JP60201751A 1985-09-13 1985-09-13 Pattern forming method Pending JPS6262523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60201751A JPS6262523A (en) 1985-09-13 1985-09-13 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60201751A JPS6262523A (en) 1985-09-13 1985-09-13 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS6262523A true JPS6262523A (en) 1987-03-19

Family

ID=16446331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60201751A Pending JPS6262523A (en) 1985-09-13 1985-09-13 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS6262523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348404B1 (en) 1997-07-02 2002-02-19 Yamaha Corporation Wiring forming method
KR100365434B1 (en) * 2000-10-26 2002-12-18 주식회사 하이닉스반도체 Method for removing ring type residue on wafer edge

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348404B1 (en) 1997-07-02 2002-02-19 Yamaha Corporation Wiring forming method
US6509261B2 (en) 1997-07-02 2003-01-21 Yamaha Corporation Wiring forming method
KR100365434B1 (en) * 2000-10-26 2002-12-18 주식회사 하이닉스반도체 Method for removing ring type residue on wafer edge

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