KR960016828B1 - Patterning method of semiconductor device - Google Patents
Patterning method of semiconductor device Download PDFInfo
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- KR960016828B1 KR960016828B1 KR1019880004896A KR880004896A KR960016828B1 KR 960016828 B1 KR960016828 B1 KR 960016828B1 KR 1019880004896 A KR1019880004896 A KR 1019880004896A KR 880004896 A KR880004896 A KR 880004896A KR 960016828 B1 KR960016828 B1 KR 960016828B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Abstract
Description
제1도는 종래의 Si-레지스터 단층 광석판술을 타나낸 도면이다.1 is a view showing a conventional Si-registered tomographic ore plate graft.
제2도는 종래의 노르말 레지스터/ARC 유사이중층 광석판술을 나타낸 도면이다.2 is a view showing a conventional normal register / ARC-like double layer ore lithography.
제3도, 제4도, 제5도, 제6도는 본 발명의 Si-레지스트/ARC 이중 층광석판술을 나타낸 도면이다.3, 4, 5, and 6 show the Si-resist / ARC double layer ore lamination of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
a : 스텝b : 식각층a: step b: etching layer
c : ARC층d : 레지스트층c: ARC layer d: resist layer
본 발명은 반도체 제조공정 중 사진 석판기술(Photolithography)에 관한 것으로 특히 알미늄(Aluminium), 폴리실리콘(Polysilicon), 실리사이드(Silicide)와 같이 반사도가 큰 재질과 토로로지(Topologh) 기복이 심한 기판으로 이루어진 웨이퍼의 감광제 패턴(Pattern)을 형성하는데 있어서 고해상력, 고식각저항성 등을 갖는 것을 특징으로 하는 이중층 사진석판기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to photolithography in a semiconductor manufacturing process, and in particular, made of a highly reflective material such as aluminum, polysilicon, and silicide, and a substrate having a high topologh ups and downs. The present invention relates to a double layer photolithography technology characterized by having high resolution, high etching resistance, and the like in forming a photoresist pattern of a wafer.
종래의 Si-레지스트를 사용한 단층 사진석판기술은 제1도에서와 같이, 실리콘기판 및 산화막(a) 위에 형성되는 식각층(b)에 Si-레지스트(d)를 도포하고 연화굽기(Soft bake), 정렬 및 노광 (Align &Expose) 그리고 현상(Develop) 시킨 다음, 식각층(b) 식각 및 Si-레지스트 제거를 실시하는 것이다.In the conventional single-layer photolithography using Si-resist, as shown in FIG. 1, the Si-resist (d) is applied to the etching layer (b) formed on the silicon substrate and the oxide film (a), and soft bake. After alignment, exposure and development, etching (b) etching and Si-resist removal are performed.
또한 종래의 일반적인 레지스트/ARC(Anti Reflective Coating) 광반사방지막을 사용한 유사 이중층 사진석판기판은 제2도에서와 같이 실리콘기판 및 산화막 (a) 위에 형성되는 식각층(b)에 ARC(c)를 도포하고 ARC 굽기(150℃, 5분간)를 한 후 이 위에 레지스트(d)를 도포하고 연화굽기, 정렬 및 노광 그리고 현상 (Wet develop)시킨 다음 식각층(b)을 식각하고 레지스트/ 제거를 실시하는 것이다.In addition, the conventional double-layer photolithographic substrate using a conventional resist / ARC (anti-reflective coating) antireflective coating has ARC (c) on the etching layer (b) formed on the silicon substrate and the oxide film (a) as shown in FIG. Apply, ARC bake (150 ° C, 5 min), apply resist (d) on it, soften, align, expose and develop, then etch the etching layer (b) and resist / remove It is.
그러나 이상과 같은 선행기술에 있어서, 전자의 경우 고반사 매질(Aluminum, Polysilicon, Silicide) 기판에서는 정상파(Stahnding Wave), 난 반사 등의 효과에 의해 감광제선의 열화로 해상력이 떨어지고, 기판의 기복이 심한 위상에서는 벌크(bulk) 현상(난반사 등에 의해 발생되는 notching현상)의 제거가 어렵다.However, in the prior art as described above, in the case of the former, in the case of the high reflection medium (Aluminum, Polysilicon, Silicide) substrate, the resolution decreases due to deterioration of the photoresist line due to the effects of staging wave, egg reflection, etc. In the phase, it is difficult to eliminate the bulk phenomenon (notching phenomenon caused by diffuse reflection or the like).
또한 후자의 경우 기판 위상 기복이 있는 웨이퍼에서의 포토레지스트/ ARC습식현상시에 기판층 모서리 및 하부의 상대적으로 두꺼운 ARC의 환전현상을 위새허는 노르말 레지스트 선의 치수(Critical Dimension) 손실이 크다.Also, in the latter case, the critical dimension loss of the normal resist line which causes the exchange of relatively thick ARC at the edge and the bottom of the substrate layer during the photoresist / ARC wet phenomenon in the wafer with the substrate phase relief is large.
또한 언더커트(Under cut), 점착성(Adhesion) 부족을 방지하기 위한 공정제어의 어려움이 있으며 ARC에 대한 노르말 레지스트의 식각 선택비가 적으므로 RIE(Reactive ion Etch)O2레지스트 식각기에 의한 상층 패턴을하층에 전달하는 이중층 PCM(Portable Comfnmal Mask) 공정응용이 곤란하다.In addition, it is difficult to control the process to prevent under cut and lack of adhesion, and since the etching selectivity of the normal resist to ARC is small, the upper layer pattern by the reactive ion etching (RIE) O 2 resist etcher is reduced. Application of a double layer PCM (Portable Comfnmal Mask) process to be delivered to the lower layer is difficult.
따라서 본 발명은 이상의 선행기술의 문제점을 해결하고, 고 해상력을 갖는 양호한 식각 패턴의 기판을 제조하는데 그 목적이 있다.Accordingly, an object of the present invention is to solve the above problems of the prior art and to manufacture a substrate having a good etching pattern having high resolution.
즉, 본 발명은 하부에 약 1 내지 1.5㎛의 비교적 두꺼운 ARC를 도포하고 균일표면을 만든 후, 이 위에 다시 약 0.5 내지 0.8㎛의 얇은 Si-레지스트막을 형성시킴으로써 비록 고반사 기판에서도 고 해상력을 갖는 감광제 패턴과 이의 제조방법에 관한 것이다.That is, the present invention is applied to a relatively thick ARC of about 1 to 1.5㎛ on the bottom to make a uniform surface, and then to form a thin Si-resist film of about 0.5 to 0.8㎛ again on the high resolution even on a high reflective substrate It relates to a photosensitizer pattern and a method of manufacturing the same.
또한 형성된 상층 Si-레지스트 패턴은 O2플라즈마에대한 큰 식각 저항성을 나타내므로 비록 얇은 두께(약 0.5∼0.8㎛)로도 ARC 하층 식각 접촉 마스크로서 충분하다.In addition, the formed upper Si-resist pattern exhibits a large etching resistance to O 2 plasma, so even a thin thickness (about 0.5 to 0.8 mu m) is sufficient as an ARC lower etching contact mask.
즉, 이 상층 마크를 이용하여 O2RIE레지스트 건조식각기로써 하층에 패턴을 전달한 후 기판(Aluminum, Polysilicon, Silicide) 식각을 할 수 있다.That is, the substrate (Aluminum, Polysilicon, Silicide) can be etched after the pattern is transferred to the lower layer using the O 2 RIE resist dry etcher using this upper layer mark.
이때에도 상층Si-레지스트는 기판 식각시 큰 식각 저항성을 나타내므로 최종적으로 양호한 기판 식각 패턴을 얻을 수 있다.In this case, since the upper layer Si-resist exhibits large etching resistance during substrate etching, a good substrate etching pattern may be finally obtained.
본 발명의 실시예가 다음과 같이 이루어진다.An embodiment of the present invention is made as follows.
1) 제3도와 같이 단차가 형성되는 기판에 알미늄, 폴리실리콘 또는 실리사이드 등으로 형성되는 식각층(b) 웨이퍼에 레지스트 도포기를 사용하여 기판 표면에 형성되어 있는 막의 단차정도에 따라 최적 평탄화를 이룰 수 있는 두께(약 1∼1.5㎛)로 ARC(Brewer 사 제품, ARC-L5)(c)를 도포한다.1) By using a resist applicator on an etching layer (b) wafer formed of aluminum, polysilicon, or silicide, etc., on the substrate having the step difference as shown in FIG. 3, an optimum planarization can be achieved according to the level of the step formed on the surface of the substrate. ARC (Brewer Co., ARC-L5) (c) is applied to a thickness (about 1 to 1.5 m).
2) Si-레지스트 도포시 ARC와의 혼합방지 및 상층 Si-레지스트(d) 현상시하층 ARC막 (c)의 용해를 최소화 하기 위해서 경화굽기(약 150℃ 핫 플레이트 오븐에서 약 5분간)하거나, 강한 UV전면노광(동시에 약 150∼180℃로 가열) 또는 CF4플라즈마 처리(CF4가스를 사용하는 드라이 식각기를 사용하여 약 2∼5분간)한다.2) In order to prevent mixing with ARC and to minimize the dissolution of upper layer Si-resist (d), the lower layer ARC film (c) when Si-resist is applied, hardening baking (about 5 minutes in a hot plate oven of about 150 ° C.) or strong UV front exposure (simultaneously heated to about 150-180 ° C.) or CF 4 plasma treatment (about 2-5 minutes using a dry etcher using CF 4 gas).
3) Si-레지스트를 사용하여 상층 Si-레지스트(d) 도포 (두께 약 0.5∼0.8㎛) 및 연화굽기(약 98℃ 핫 플레이트오븐에서 약 45초간)하여 제4도의 Si-레지스트층(d)을 형성한다.3) Si-resist layer (d) of FIG. 4 was applied by applying an upper layer Si-resist (d) (thickness about 0.5 to 0.8 mu m) and softening baking (about 45 seconds in a hot plate oven of about 98 DEG C) using a Si-resist. To form.
4) 제5도에서와 같이 마스크를 사용하여 필요한 패턴을 형성하기 위해 상층(Si-레지스트(d)을 정렬(Stepper 사용), 노광 및 현상한다.4) The upper layer (Si-resist (d) is aligned (using a stepper), exposed and developed to form the necessary pattern using a mask as in FIG. 5).
5) 제6도에서와 같이 하층(ARC)(C) 식각(O2RIF 레지스트 폴라즈마 드라이 식각기 사용)을 실시한다.5) As shown in FIG. 6, an underlayer (ARC) (C) etch (using an O 2 RIF resist polasma dry etcher) is performed.
6) 식각층(b) 식각을 실시한다.6) Etching layer (b) Etching is performed.
7) 이어서 Si-레지스트(d) 및 ARC(c) 제거한다.7) The Si-resist (d) and ARC (c) are then removed.
이 공정에 있어서 식각층(b)이 금속인 경우에는 유기물 제거재인 R-10폴리실리콘 또는 실리사이드 기판인 경우에는 황산(H2SO4: H2O2→3 : 1 : 120℃)을 사용하여 습식 제거한다.In this process, when the etching layer (b) is a metal, R-10 polysilicon, which is an organic material removing material, or sulfuric acid (H 2 SO 4 : H 2 O 2 → 3: 1: 120 ° C.) is used. Wet remove.
이상과 같이 식각된 식각층은 해상력이 우수하여 종래의 방법으로 제조된 기판 보다 우수할 뿐만 아니라 종래의 기술보다 간편하고 대량 생산이 가능하다.The etching layer etched as described above is excellent in resolution and superior to a substrate manufactured by a conventional method, and is simpler than a conventional technology and is capable of mass production.
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