JPS6262229A - Camera with multi-split photometer - Google Patents

Abstract

PURPOSE:To obtain a camera capable of quick photographing continuously, by arranging a photometry circuit for emanating a brightness signal dividing an object field, a means of generating a brightness signal in a specified area as the reference value, a means of extracting brightness differences area wise and a means for generating proper exposure value from a brightness distribution. CONSTITUTION:A photometry circuit 13 for automatic exposure control receives four signals for A/D conversion start, CP for A/D conversion, reference CP and reading information from CPU and sends brightness information of an object field divided serially to a CPU to be converted into a parallel signal. An automatic focus detection circuit 14 receives signals for start, stop and chip select for controlling read from the CPU and sends a detection ending signal to a gate circuit 23 through a switch SO and display information to the CPU. The CPU identifies the brightness distribution using the brightness in a specified area of an object at the completion of a focus adjustment as the criteria generate proper exposure information according to the results and this enable quick photographing continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a camera equipped with a photometric device for determining an appropriate exposure amount.

Conventional technology As a means of determining the exposure amount of a camera, the field is divided into multiple regions and the brightness is measured using a photoelectric element, and the average value of the multiple brightness signals corresponding to each region is obtained. At the same time, the exposure amount is determined by determining how far the brightness of each area is from the previous average value.In this case, the average brightness value is biased due to extremely bright or dark areas. Since it may be difficult to determine the appropriate exposure amount, separate signals are generated to determine the upper and lower limits of how bright or dark areas should be measured from the average value. Alternatively, there is a method that determines the exposure amount by excluding brightness information of dark areas. (Jikko 60-
(Refer to Publication No. 1.1475) To measure the brightness of a field, spot light metering is performed at the center of the field, and average light metering is performed at the periphery, and the difference in average brightness at the periphery with respect to the brightness at the center is calculated. An exposure amount determining means has been proposed which calculates the difference and applies a predetermined exposure amount correction when the difference is greater than a predetermined value. (For example, JP-A-57-622, JP-A-58-10083)
(See Publication No. 9).

Problems to be Solved by the Invention As described above, in the conventional exposure amount determining means, the subject is divided into multiple areas and measured, the average brightness of each area is calculated, and the brightness within a predetermined range from the average value is determined. The difference in brightness between the divided areas, that is, the width of the brightness, is determined, and the exposure amount is determined based on this. However, since each photometric value is used as is, the measurement result It takes a considerable amount of time to process the signals, and this problem still remains in cases where rapid continuous shooting is required.

Means to Solve the Problem In order to solve the above-mentioned problems, this invention divides the field into a plurality of regions, measures the brightness of each of the plurality of regions individually, and uses the brightness of a predetermined region as a reference. For other areas, calculate the difference between the brightness of the predetermined area and process the reference value of the predetermined area and the brightness difference values obtained for the other areas to calculate the brightness distribution in the subject. It is configured to recognize the state and determine the appropriate exposure amount based on the result.

To explain this with reference to FIG. 1 corresponding to the embodiment, 1 is a photoelectric conversion element that divides the field into multiple regions and measures the brightness of each region, and its output signal is used for automatic exposure control. The signal is processed in a photometric circuit (hereinafter referred to as AE) 13, where the luminance of a predetermined area is used as a reference value, and the luminance signals of other areas are extracted as signals of differences from the reference value. These brightness signals and brightness difference signals obtained are input to the processor 15 and processed, the brightness distribution state of the object field is identified, and an appropriate exposure amount is determined based on the results.

When photometrically dividing the field into multiple areas and determining the exposure amount, the brightness of a predetermined area is used as a reference, and in processing the brightness signals of the multiple photometered areas, this reference value and other values are used. Since it is extracted and processed as a difference signal from the luminance signal of
The size of the value to be processed is small, and signal processing can be performed faster.

/″ /′ −〇　１ Example Examples of the present invention will be described below.

(1) Overview of Configuration FIG. 1 is a block diagram schematically showing an automatic exposure and automatic focus control device for a camera incorporating the photometric device of the present invention.

In the figure, 1 is a photoelectric conversion element that divides the field into multiple regions and measures the brightness of incident light for each area, and 13 is an automatic exposure that processes the output signal from the photoelectric conversion element 1 and converts it from A/D. A control photometry circuit (hereinafter referred to as AE), 10 an automatic focus detection element, 14 an automatic focus detection circuit (hereinafter referred to as AF) that processes the output signal of the detection element 10, 15 an input from the automatic exposure control photometry circuit and others. A processor (hereinafter referred to as CPU) that processes signals, determines the exposure amount, etc., and instructs each control mechanism to operate, and 16 is a read-only memory (16) that stores information unique to the lens F number and focal length ring lens. (hereinafter referred to as ROM), 17 is a signal processing circuit for displaying the photographing conditions etc. as a result of processing by the CPU on the outside of the camera, and 18 is an automatic control circuit for controlling the exposure mechanism of the camera based on the appropriate exposure signal output from the CPU. Exposure control section (hereinafter referred to as AE control), 19 is an automatic focus control section (hereinafter referred to as AF control) that controls the focus control mechanism of the camera based on the focus control signal output from the CPU, SOl 51%
S2 is an operation switch installed on the camera, and the switches of photometry SOS, automatic focus S1%, and release S2 are turned on in order by using one common operation part. 23 is a gate circuit, and 24 is a setting section for predetermining exposure conditions and the like for the camera.

FIG. 2 shows how the field is divided into a plurality of regions and the photoelectric conversion elements 1 are arranged in each region in order to measure the brightness of the field and its distribution state.

FIG. 3 is a cross-sectional view showing the photometric device of the present invention incorporated into a camera. The light incident on the lens system 2 is reflected by the main mirror 4, passes through the upper condenser lens 5 and the ventazolism 6, further passes through the half prism 7 and the relay lens 8, and is incident on the photoelectric conversion element 1 arranged above it. Image. Further, the light transmitted through the semi-transparent part formed at the center of the mirror 4 is reflected downward by a sub-mirror behind the mirror 4, passes through the relay lens 9, and enters the detection element 10 for automatic focus detection. Note that this detection element 10 detects the in-focus state of the central part of the field of view shown in the figure. Also,
3 is an aperture, 11 is a shutter curtain, 12 is a film surface, and 19 is an automatic focus control section (hereinafter referred to as AF control).

FIG. 4 shows in slightly more detail the circuit configuration between the operation switch section, AE section, AF section and CPU in the block diagram shown in FIG. 1.

The operation switch section has a common operation section, and the photometry switch S
O% Auto focus switch 51% Release switch S2
The ON state can be set in this order. Photometering switch S
When O is turned ON, two interrupts lNTl, ! are sent to the CPU via the gate circuit. NT2 signal is sent and CPU
Interrupts are processed by the internal interrupt mechanism, but it is also possible to disable interrupts using an interrupt disable signal from the CPU side.

The photometry circuit 13 for automatic exposure control receives an A/D conversion start signal ADSTR and an A/D conversion clock signal AD from the CPU side.
CP, reference clock reference SCK.

Receives four types of input signals of data read signal AESTR,
The luminance information of the object field processed within the AE is sent to the CPU as serial data. Note that the luminance information sent as serial data from the AE is converted into a parallel signal by a serial-to-parallel converter (SP converter) in the CPU.

Auto focus detection circuit (AF) 14 is the AF on the CPU side.
It receives a start signal, an AF stop signal, and a chip select signal C8 used for data read control, and sends an automatic focus detection end signal AFE to the gate circuit connected to the photometry switch S, and also sends display data to the CPU side. do.

(2) AE Section FIG. 5 shows the circuit configuration of the AE section which processes the signal from the photoelectric conversion element, A/D converts it, and sends it to the CPU. below,
This circuit and its operation will be explained.

The output signals of the photoelectric conversion elements PDo-PDg arranged in each of the plurality of divided object fields are logarithmically compressed by the amplifier An-A8 to obtain brightness values BVO to BV8.

Among the obtained brightness values BVO-BV8, the brightness value BVo in the center of the field is used as the reference value, and the brightness value BV in other areas
, ~BVa as a difference including the sign from the reference value, it is possible to recognize the brightness distribution of the entire field with the center of the field as a reference. Therefore, the brightness value BVO of the central part of the field is converted into an 8-bit signal by the A/D converter ADo, and the reference value BV is also converted.

and the brightness values BVl-BVs of other areas are input to the controllers CP1 to CP8 to obtain the positive and negative signs, and the (Bvi - BVo) value (here i = 1 to 8) is input to A.
The signal is converted into a total of 6 bits (5 bits + sign bit) by the /D converter Arch''-ADa.

Each A/D converter has a data register that temporarily stores the converted data, and is selected by the chip select register C5o%C5s issued from the P/S control section to send the converted data as serial data to the CPU. The contents are sent from the data register to the P/S control section as an 8-pit noralel signal to the pass line. Noξ received from the P/S control section Babasu line
Converts the parallel signal into a serial signal and sends it to the CPU. Note that details of the P/S control section will be explained later based on FIG. 9.

Note that the logarithmic compression amplifier A used in FIG.
As for i, as illustrated in FIG.
, a compression diode 28, and a level conversion buffer 29.

(3) The A/D converter shown in FIG. 7 shows the A/D converter oil 0, ADi (i=
1 to 8), FIG. 7 0) shows oil 0, and FIG. 7 ←) shows ADZ. Since AD2 to ADa have exactly the same configuration, they have been omitted.

The means of A/D conversion is basically the same for AD and AD1 to AD8, and a double integration method is adopted. That is,
First, an integrating capacitor is charged with a luminance value input as an analog quantity for a certain period of time. In this case, the charging current changes depending on the brightness value, so the charge after being charged is an integral value of the brightness value. Next, this is discharged under a constant current, and the discharge time is counted using a clock pulse, and the sum of the clock pulses indicates the brightness value.

To briefly explain the circuit configuration of Oki 0, an input signal with a brightness value BVo is input to one of the switching elements 200.

Further, two types of reference level signals Vstd and VrefO are supplied from the power supply circuit 300, and the reference level signal Vr
ef(1 is input to the other switching element 200,
A reference level signal Vstd is applied to a first input of the oi-anzo 120. The output side of the switching element 200 is connected to the second input side of the amplifier 120 via a resistor R. An integrating capacitor C is connected between the output side and the second input side of the oscillator amplifier 120, and a switching element 201 is connected parallel to this. The output of the amplifier 120 is input to the first input side of the controller 121, and the reference level signal Vstd is input to the second input side of the controller. Konnozoreta 121
The output is input to the control input side of the switching element 201, the gates 202 and 203, and the flip-flop 204 to the control input side of the launch 310.

Further, the A/D conversion circuit is provided with a counter 30 that counts the charging/discharging time of the integrating capacitor C, and a latch 31 that holds the counted contents. From the CPU side, A/
The D conversion clock pulse ξADCP is supplied to the l side (counting input side) of the counter 30 via the gate 211, and the A/D conversion start signal ADSTR is supplied to the R side (reset signal side) of the counter 30. Supplied.

The ADo counter 30 is used not only as a counter for A/D conversion of the input brightness value BVo, but also as a counter for A/D conversion of the brightness values BV, .about.BVg, which are A/D converted in AD, .about.AD8.

Next, the operation of the circuit will be explained. First, the reference signal V
It is assumed that std is smaller than the input brightness value BVo, and that the counter 30 is in a reset state. At this time, the output of the gate 205 is in the "L" state. The output of the game) 205 is H'' when the contents of the counter 30 are other than 0OOH to OFF in hexadecimal notation.In other words, the counter 30 has been reset and the ADST
The output of the gate 205 to which the R signal is input is “I”.
,'' and at this time, the switching element 200 is set to the state shown in FIG. 7(a).

The input brightness value BV is input to the O-R Anzo 120 via the switching element 200° resistor R, and the difference between it and the reference signal Vstd input to one of them is output. Next, the differential signal of Jin is input to the converter/F converter 121 and compared with one input Vstd.
d, the output of the connominator 121 is set to "L". At this time, since the switching element 201 is in the OFF state as shown in FIG.
Vstd)/R flows and charging starts.

On the other hand, the counter 30 receives the A/D conversion start signal ADSTR from the CPU and starts counting the A/D conversion clock ξ pulse ADCP sent through the gate 211. When the count value reaches a certain value, that is, after a certain period of time has elapsed, a signal is sent to the gate 205, and the gate 205
H'' state. This state is transmitted to the switching element 200 via the line 102 and inverted. Since the second reference voltage Vrefo is applied to the input terminal of the switching element 2000 on the inverted side, the output voltage is The input side of the Anzo 120 has a first reference voltage Vstd and a second reference voltage lower than the first reference voltage Vstd.
The reference voltage Vrefg is input, and as a result, the charges charged in the integrating capacitor C are
It is discharged at td -Vref o )/R.

As a result of the discharge, the terminal voltage 100 of the integrating capacitor becomes the first
When the voltage becomes lower than the reference voltage Vstd of
``'' state, short-circuiting the terminals of the integrating capacitor and inverting the gate 202 to the "H" state. When the gate 202 becomes the "H" state, its output passes through the gate 203 to the flip-flop. 204, a data input command is given to the terminal of the latch 31, and the counter 3
The count content of 0 is transferred to the latch 31.

On the other hand, the output of the counter 30 is also input to the gate 2o9, and if the output of the gate 202 does not go to the "H" state before the output of the gate 209 is inverted to the "H" state by the output from the counter 3o, that is, , when it takes a long time to discharge the integrating capacitor, the content of the counter becomes 1.
Proceeds to hexadecimal number IFOH, at this time gate 209 is "
The flip-flop 204 applies a data input command to the terminal of the latch 31 via the gate 203, and the count contents of the counter 30 are transferred to the latch 31.

The output of the counter 30 is also input to the gate 212, and when the count of the counter advances to 7EH in hexadecimal, the gate 212 becomes "H" state, and the AD
A latch 32 provided in the converters AD, -ADs operates to latch the count contents of the counter. Note that the contents latched at this time are 5 bits up to BL-BS of the counter.

Next, the AD converter AD shown in FIG. 7(b) will be explained.

The circuit configuration is basically the same as AD, but BV is used as an input signal and a reference signal to judge the brightness of the field.
, a converter 230, switching elements 221 and 222, and a flip-flop 220 are added, which compare the input luminance value BV1 of the first region with the reference signal BV and send out a positive or negative sign, and a counter is added. A latch 32 is provided which holds the contents of 30.

Next, the operation of ADl will be explained. Input brightness value Bv
The two input signals 1 and the reference signal BV are compared by the converter ξ converter 230, and when BVo>BVI, the converter 230 outputs the "L" state, and the AD converter A
It is input to the DI 7 lip 70 tsuzo 220. On the other hand, the fall signal of the AD conversion start signal STR sent from the AD converter ADO described above, which is generated when the gate 205 is in the "L" state in ADO, is used to integrate It determines the timing to start charging the capacitor, and when this falling signal is input to the 7-lip 7-lodge 220, the "L" state of the output of the converter 230 is transmitted to its output side. be done.

As a result, the switching elements 221 and 222 are set to the illustrated state. This can be thought of as if, in the AD converter described in FIG. 7(a), BVo is unchanged, Vstd is replaced by BVI, and Vrefl is replaced by Vrefl.

Now, when the oil conversion start command signal ADCH sent from the D converter AD enters the "L" state, the switching element 2
23 is set to the state shown. The reference signal BVO and the f11 signal BV are input to the operational amplifier 122, and the output difference (BVo - BVI) is
However, one input of the connominator 123 is BVI, and when BV>BVI, the output of the connominator 123 is in the "L" state.

As a result, the switching element 224 is set to the state shown in the figure, so that the integrating capacitor CK has a current (BVo -
BVl)/R flows and charging starts.

On the other hand, the counter 30 (shown in FIG. 7(a)) common to each AD converter ADo = ADs has started counting as described above, and when the count value reaches a predetermined value, the gate 208 is closed. “H” state, this result game) 210
The output of the ADCH becomes "H" state and ADCH becomes "H" state. As a result, the switching element 223 is inverted from the state shown in the figure, and the input side of the operational amplifier 122 has Bvl and BVl.
-Vrefl is applied, and the charge of the integrating capacitor C is a constant current (BVl-(BVt-Vrefl)
)/R=Vref l/R.

When the terminal voltage 105 of the integrating capacitor becomes lower than the input brightness value BVI due to discharge, the output of the converter 123 is inverted, switching the switching element 224 to the "ON" state, and short-circuiting the terminals of the integrating capacitor. At the same time, the gate 225 is inverted to the "H" state. gate 225
The output of is inputted to the 7-resoflop 227 via the gate 226, which issues a data input command to the latch 32, so that the contents of the counter 30 are latched.

FIG. 8 is a time chart illustrating the operation of the AD conversion unit, and FIG.

First, to explain the operation timing of each part of ADo, C
AD conversion start signal ADSTR sent from PU is “H”
”, the integration capacitor starts charging,
The terminal voltage 100 falls. The counter 30 starts counting and stops counting at the hexadecimal number IFOR. The output signal 101 of the converter 121 is in the "H" state during the charging and discharging period of the capacitor, and the output signal 102 (STR) of the gate 205 which switches charging and discharging is in the state of "H" during the charging and discharging period of the capacitor. The latch command signal 103 goes to "H" when the capacitor finishes discharging.
" state. Also, the output signal 104 of the gate 209 becomes "H" when the counter advances to the hexadecimal number IFOR.
state.

Next, the operation timing of each AD, -ADs will be explained. When ADSTR becomes "H" state, charging of the integrating capacitor is started and the terminal voltage 105 decreases. The counter 30 has started counting, but the count value is 7E in hexadecimal.
When it reaches H, the gate 212 of wholesale 0 becomes "H" state and the LAT signal becomes "H", and the contents of the counter at that time are held in the latch 32.The switching timing for charging and discharging the integrating capacitor is AD.

This is done by the signal ADCH sent from the gate 208 when the count value of the counter reaches 3F in hexadecimal notation at a set time, which is relatively short.

The chip select signal is the counter 30 for C8o.
It is sent after the contents of C8l to C88 reach the hexadecimal number IFOR, and the contents of the counter 30 reaches 16 for C8l to C88.
After reaching the base number 7EH, it is sent out sequentially and continuously. .

(4) P/S control unit FIG. 9 is a block diagram showing the configuration of the P/S control unit. This control section has a function of converting the A/D converted 8-pit parallel signal into a serial signal and sending it to the CPU.

The control section includes a timing signal generation section 91 that operates based on the reference clock signal SCK input from the CPU and the AE section data readout signal AESTR, and an AE readout signal AES.
The 7-bit counter 92 starts counting at TR, and the chip select signal C5o-
It is comprised of a decoding section 93 that generates CSS, and a p/s register 94 that converts parallel signals into serial signals and sends them out.

Next, to explain its operation, the P/S control section starts operating in response to the section data read signal, the 7-bit counter 92 counts the clock pulses, the counted value is sequentially decoded by the decoding section, and the A/D Generates chip select signals C8o and C8a to select the converter, and selects the AD converter AD.
o Send to ADs. From the AD converter, A is selected sequentially by chip select signals C8o C5a.
D conversion unit ADo = 8-bit brightness value from ADH is P
/S register 94.

The p/S register 94 temporarily holds the input 8-pit parallel signal under the control of the timing signal and clock signal sent from the timing section, converts it into a serial signal, and transfers it to the CPU.

(5) Signal processing within the CPU Next, the signal processing performed within the CPU will be explained based on the flowcharts shown in FIGS. 10 to 14.

First, among the operation switches that turn on in the order of photometry, autofocus, and release, when the photometry switch So is turned on, an interrupt signal is sent to the CPU from the gate 23 shown in FIG. 4, and interrupt processing is started. . In Figure 10, “INT
It is designated as soJ. Next, the Ato and So routines with interrupts disabled are entered, but first the state of the autofocus switch Sl is checked, and if it is ON, the routine jumps to Sl. If it is OFF, check the status of the photometry switch SO and turn it OFF.
If it is F, it is due to a malfunction of the Sθ switch, so the interrupt is enabled, the process is stopped, and the process waits for the switch SO to be turned on again.

On the other hand, if the switch SO is ON, the program jumps to the AE subroutine for automatically determining the exposure amount. The AE subroutine will be explained later.

When returning from the AE subroutine, autofocus switch S
1 is checked, and if it is OFF, the routine returns to checking the switch So. If the switch S1 is ON, the routine of S1 is entered. AF start signal to automatic focus detection circuit 1
Send to 4.

After this, a series of operations such as automatic focus adjustment focus detection and motor operation are performed independently of the processing within the CPU. After sending out the AP start signal, the state of Sl is checked, and if it is OFF, an AF stop signal is sent to the automatic focus detection circuit 14. This allows focus detection and motor operation to be stopped independently of the CPU. When the sending of the AF stop signal is finished, the process jumps to INTS. If the switch S1 is ON, the process jumps to the AE subroutine, and when the process returns after completing a series of processes, interrupts are enabled and the state of the switch S1 is checked. If it is OFF, output the AF stop signal and INT.
If the switch Sl is ON, the process jumps to the fart subroutine again. After the above-mentioned interrupt is enabled, when the AF matching signal AFE is sent from the automatic focus detection circuit 14 to the gate 23, the falling edge signal of rNT2 is sent from the gate 23 to the interrupt mechanism. Figure 11 INT A
Enter the FE routine.

In the INT AFE routine shown in FIG. 11, interrupts are first disabled, an AF stop signal is sent to the automatic focus detection circuit 14, and the focus adjustment mechanism is disabled. Then A
After jumping to subroutine E and performing a series of processes, the state of switch S1 is checked. If it is OFF, a routine is entered to check the state of the switch SO, but if it is ON, the state of the release switch S2 is checked. If S2 is OFF, the routine returns to check the state of S1 again.

In this way, the camera continues to wait until the release switch S2 is turned ON, but when the AF switch S1 is turned OFF, the camera is unable to operate the release and enters a routine to check the state of the photometry switch So. If the release switch S2 is ON, the user enters the release operation, sets the shutter speed, aperture value, etc., and operates the shutter.

After this, the state of the photometry switch So is checked, and if it is OFF, interrupts are permitted and the process is stopped.

If the switch SO is ON, the program jumps to the SO routine and starts executing the INTSo routine again.

In the AE subroutine shown in FIG. 12, AD conversion is executed and the D conversion value is taken into the CPU.

Next, the program jumps to the subroutine for division processing, which will be explained later, performs division photometry processing, and returns from the processing routine as a result.
Let's move on to APEX calculations. Here, the shutter speed and aperture value are determined, necessary display data is prepared and sent to the display circuit shown in the third diagram, the fart subroutine is ended, and the process returns to the original routine.

Next, the subroutine of the division process will be explained using FIGS. 13 and 14. In this routine, after determining the exposure value from the brightness values of each area of the subject, the state of the metering mode selector switch SA, which is operated from outside the camera, is checked, and the
Return to routine N.

If photometry mode switch SA is OFF, 4Bmax
- Jump to the min routine and check the brightness BVi of each area of the object.
The maximum value AB of the difference Vi between and the brightness BVo at the center of the field
Vmax 1 second largest value ABVA.

The minimum value ΔBVmin and the brightness width ΔBVw are determined. This will be explained later.

When the processing in the ΔBmax -min routine is finished, the process returns to the division processing subroutine again, and in order to judge the maximum brightness, BVo+ΔBVmax) 11.3 BV is determined, and if it is not greater than 11.3BV, △BVmax)
2.3 Jump to BY judgment routine. If it is larger than 11.3BV, the BV is used to judge the brightness in the center of the field.
) If 11.3 is greater than 11.3, then
ΔBVmax) Jump to the routine after the judgment in 2.3,
Also, if the lever is not larger than 11.3, ΔBmax −mi
The maximum value ΔBVma of the brightness difference of the object field determined by the n routine
x is discarded, and the second largest value ΔBVA is adopted as the new maximum value of the brightness difference. Here, the position where the film latitude exists is determined according to the luminance distribution state of the object field, such as the maximum value, minimum value, and middle luminance difference of the luminance difference, and the luminance value BVc necessary for controlling the exposure amount is determined.

The processing procedure is to calculate the maximum value of brightness difference aBVmax:) 2.3
The brightness values BVc to be adopted are classified into three through the determination of the minimum value of the brightness difference ΔBVmin (-2, 7, and the determination of the brightness medium ABVw). If we organize this, 1, △BVmax ) 2.3 is satisfied, -(1
) △BVmin (BVc = B when -2,7
VO・・・・・・・・・・・・(2)(2) ABV
Satisfying min≧−2,7, (i) ABVw:
) 5, BVc = BV(1+ΔBVmin +2.7 --
・(5)(II) When 4BVw≦5, BVc ”= BVo +ΔBVmax-2,3...
・-(6)2, ΔBVmax≦2.3 is satisfied, (1
) ΔBVmin (-2, 7 are met, (1) AB
Vw ) 5, BVc ” BVo+ΔBVmax-2,3--・(3
) (it) When ABVw≦5, BVc = BVo+ΔBVmin+2.7−-= (
4) (2) BV when aBVmin≧-2,7
c = BVo・・・・・・・・・・・・
...lives as (1). For example, BVc "" BVo
The number shown on the left as (1) is the same as the classification number shown at the bottom of the flowchart in FIG.

FIG. 15 shows an example of the brightness value processing results. To explain this simply, the vertical axis shows the brightness value, and the horizontal direction shows examples. To explain using the example on the far left, this means that Vmax≦2.3, ABVmin≧-2,
In case 7, BV is adopted as BVc.

The classification number in this case is 1. Also, to explain the fourth example from the right, ΔBVmax) 2.3, ΔBVmi
In the case where n≧2.7 and the brightness is ΔBVw)5, it is shown that BVo + Vmin + 2.7 is adopted as BVc. The classification number in this case is 5. .

In addition, the number displayed below the vertical line is BVmax - Bym.
It shows the size of in, <5 is smaller than 5EV, = 5
indicates 5EV, and >5 indicates greater than 5EV.

Finally, a subroutine for calculating ABVmax-min will be explained. In this routine, the field of view is divided into a plurality of regions, and the maximum value aBVmax of the difference between the brightness BVi of each region and the brightness BVo of the center of the field of view is determined.

The second largest value BVA, also the smallest difference ΔBVmin
, the brightness width aBV is reduced, and a flowchart thereof is shown in FIG. Here, an example is shown in which the field is divided into nine parts, and since eight areas other than the central area serving as the reference are to be processed, i=1 to 9.

First, the initial value of the variable is set at i=1. ΔB
Vmax == ARVi, ΔBVmin−ΔB
Set Vi, ABVA=0. Next, ABVmi
To find n, judge the size of ABVmin〉8BVi, and if ABVmin is large, set ΔB as ABVmin.
Store Vi and proceed. Moreover, if it is not larger, i is incremented by one and the process proceeds as i = i + 1.

Next, ΔBVmax is calculated, but first ΔBVmax)ΔB
Determine the size of Vi, and if ΔBVmax is not large, it is a residence v
ABVmax is stored as A, ΔBVi is stored as ΔBVmax, and the routine proceeds to a repeat determination. ΔB
If Vmax25' is large, the second largest difference value △BVA is obtained, but first a judgment is made as to whether ∆BVA > ABV i, and if ∆B is large, the process proceeds to repeat the routine.

If △BVA is not large yet, △BVA is changed to ∆BVi.
is stored and proceeds to the routine repetition determination.

In routine repetition judgment, ABV while i is less than 9.
Returning to the part that calculates min, when the process reaches 9 times, that is, when the brightness of all areas of the divided object scene has been processed, the iterative process is terminated, and the previously calculated ΔBVmax x and A
The difference ΔBVw from BVmin is determined, this subroutine is ended, and the process returns to the original routine.

zu1゛,: 21・:・-）Dojri' As described in detail, in the camera having the multi-segment photometry device of the present invention, the field of view is divided into a plurality of areas, and each area is divided into a plurality of areas. The brightness of a predetermined area is taken as a reference value, and the brightness of other areas is taken out as a difference value from the reference value. When identifying the brightness distribution state in the subject, the reference value and the difference value from the reference value are processed.
The size of the information value to be processed is small, and rapid signal processing is possible, so even when continuously photographing a subject that is constantly moving and whose brightness changes, it is possible to always obtain the appropriate exposure level. can be set.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the automatic exposure and automatic focus control portions of the camera of the present invention. FIG. 2 is a diagram showing the arrangement of photoelectric conversion elements. FIG. 3 is a cross-sectional view schematically showing the camera of the present invention. FIG. 4 is a block diagram showing in slightly more detail the main parts of the block diagram shown in FIG. 1, FIG. 5 is a block diagram of a photometric circuit, and FIG. 6 is a diagram showing an example of a logarithmic compression circuit. 7th
The figure is a block diagram showing the circuit of the A/D converter, and Figure 8 is A
FIG. 9 is a time chart illustrating the operation of the /D converter, and FIG. 9 is a block diagram showing the circuit of the P/S control unit. 10th
10 to 14 are flowcharts of signal processing.
The figure shows signal processing in photometry and focus detection. FIG. 11 shows signal processing up to release. FIG. 12 shows the AE subroutine. FIG. 13 shows a subroutine for division processing. FIG. 14 shows a subroutine for determining the maximum value of luminance difference and other values in the division process. FIG. 15 shows an example of the processing result of the luminance value of the object field by the division processing. 1: Photoelectric conversion element, 13: Photometry circuit for automatic exposure control, 1
0: automatic focus detection element, 14. automatic focus detection circuit, 15
: Processor, 5o1Sl, S2: Operation switch, SA
:Photometering mode selector switch Fig. 1 Fig. 3 I Fig. 6 C Fig. 9 Fig. 10

Claims (1)

[Claims] a photometry circuit that divides a field into a plurality of regions, measures the light, and generates a plurality of brightness signals corresponding to the plurality of regions;
A means for generating a luminance signal corresponding to a predetermined region among the plurality of divided regions as a reference value, and extracting the luminance of the other regions as a luminance difference value between the luminance signal corresponding to these regions and the reference value. and a means for identifying the brightness distribution state in the subject from the brightness reference value and the brightness difference value of other areas, and generating an appropriate exposure amount based on the result. A camera with a distinctive multi-segment photometry device.