JPS6260052A - Phase control system - Google Patents

Abstract

PURPOSE:To perform respective phase processing, message processing, etc., speedily by dividing and storing the execution processing contents of a message in a phase buffer and a data transmission buffer. CONSTITUTION:When data transfer between an initiator 1 and a target 2 is controlled by an interface SCSi for a small computer system, contents which are transmitted and received are divided and stored in the phase buffer 124 stored with processing contents of respective phases and the data transfer buffer 125 stored with transfer data. Then, various commands, messages, etc., which are transmitted by the SCSi are converted into phase addresses, which are used to access the buffers 124 and 125, thereby performing respective phase processing, message processing, etc., speedily and efficiently.

Description

[Detailed Description of the Invention] [Summary] Phase 13 executed using SC5i interface
In the '4111 system, when data transfer between the inineator and the target is controlled by the SC5i interface, transmission/reception processing is performed for each hide using a microprogram, whereas each phase C The contents read from the phase buffer storing the processing contents and the data transfer buffer storing the transfer y'-y make it possible to execute the processing quickly and efficiently.

1' Field of Industrial Application] The present invention relates to a method for controlling the transfer of data and various signals using an SCSI interface, which is a low-speed interface, and in particular, a system for controlling the execution processing of each phase using hardware. Concerning a phase control method for high-speed processing.

For example, when controlling the input/output of data or signals to/from an input/output device connected to a host device, unified connection conditions (interfaces) are used to achieve flexibility in system configuration.

Connection methods for these input/output interfaces include a helical connection method using a common bus, and a star connection method in which, for example, one channel connects Vi to the input/output control device individually.

On the other hand, there are two types of input/output interface signal methods: the acknowledgment method, in which control proceeds while each mutually confirming the mutual signals, and the synchronous method, in which the signals on the interface are sent and received according to a fixed clock signal. There is something like that.

The SC5i interface was developed as one of the input/output control interfaces, and uses a synchronous method for high-speed transfer, and is a method that allows data transfer control using the SC5i interface to be performed at higher speeds. The development and practical application of this technology are awaited.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram illustrating a conventional example, and FIG. 3 is a system configuration diagram.

This system diagram shown in FIG. 3 shows a central processing unit 11 (hereinafter referred to as CPIJII) that issues various commands to a plurality of input/output devices 2 (hereinafter referred to as targets) constituting the system and controls the human output of data. ), and multiple targets 2 (0) to 2 (
an adapter 12 that transmits commands from the CPU II and reports from multiple targets, l-2(0) to 2(n); and a device under control 21 ( 0) to 21 (n) Controller that executes data input/output control operations:
, 21 and data recording devices 21(0) to 21
(n) and a plurality of targets 2(0) to 2(n).

Of these, the CPU II and Agebuta 12 are referred to as a host device 1 (hereinafter referred to as initiator 1), and a plurality of initiators 1 may be connected to the same system as shown by dotted lines. In addition, this inineator 1 and tar 1γ'sol-2 (0
) to 2(n) is the same SC type.
It is assumed that the SC5 uses the Si interface.
For the transmission and reception of signals on the i-interface, the following procedure is roughly executed at predetermined intervals.

(2) Selection of selected device 21 (0) to 21 (
n) Identification to confirm number, (3) Issuance of prescribed command, (41 data transfer, (5) Status transfer, (C)) Command cop read report, 2. Each item in Jiki is called a phase.

In addition, -, Phases (1) to (4) of L are initiator 1.
(51, (
6) Phase is transmission from targets 2(0) to 2(n) to initiator 1 (hereinafter referred to as message in).

Normally, the message out processing described above is programmed. That is, as shown in FIG. 2, there is a memory for storing a program inside the processor 121 in the input/voter 1, and the program is activated by a clock signal on the 5CSi interface stored in the register 127.
Messages and data are transferred to and from the predetermined target 2(i) via the request/anok control circuit 126.

On the other hand, for example, after the selection phase processing, targets 2(0) to 2(n) that have received a predetermined command make preparations for processing the predetermined command using hardware processing, and then move the initiator 1 to the data transfer phase. , and waits for an acknowledgment character (hereinafter referred to as ACK) response from initiator 1.

Note that the 5C5i interface retains requests and ACKs in the same way as the acknowledgment method when transitioning between each phase, but for example, data transfer is processed on the selected device 21(i). It is not necessary to immediately respond with an ACK to the sending of a request consisting of multiple offsets; it is possible to perform interface control by confirming an ACK consisting of the same number of offsets even if the request is delayed within a predetermined range. be.

The data buffer 128 is used to temporarily store processing contents in order to facilitate the transfer of the contents of each phase between the initiator 1 and the selected device 2Hi) and the data to be transferred.

As mentioned above, the phase control of the initiator 1 is controlled by decoding the phase using a microprogram.
If (n) is a high-speed magnetic disk device, there is a problem in that the control of one example of the vinyl shake is delayed.

[Means for Solving the Problems] FIG. 1 shows a block diagram for explaining the present invention in detail.

The block diagram of this embodiment is the processor 1 explained in FIG.
21. Request/assign control circuit 126 and 5C5i
Phase bar of each face and message contents etc. that are passed through the interface line.

a phase address conversion circuit 122 that converts into an address signal for the phase buffer 124; and an address counter 123 that specifies an address to specifically access the phase buffer 124 based on the address signal sent from the phase address conversion circuit 122.
and command phase area, status phase area,
A phase buffer 124 that has an area for storing the contents of each phase such as a message out area and a message in area, and a data transfer buffer 125 that stores data to be transferred.
It is composed of.

[Effect]

SC5 data transfer between initiator and target
When controlling with the i interface, the content to be sent/received is divided into a phase buffer that stores the processing content of each phase and a data transfer buffer that stores the transfer data, and is transmitted via the SC5i interface. Various commands.

By converting mesosage etc. into each phase address and accessing the phase buffer and data transfer buffer using the address, each phase process and each message process can be executed quickly and efficiently.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG. Note that the same reference numerals indicate the same objects throughout the figures.

Next, the operation of this embodiment will be explained. Furthermore, initiator 1
Message out is used to send a predetermined signal or data to target 2 (1) from target 2 (1).
The predetermined signals and data from i) to the initiator l will be referred to as mensage-in and will be described below.

Before executing the command, the processor 121 sends the contents of the command and message output that will be sent from the initiator 1.
is set in advance in the phase buffer 124 under the control of.

After selection phase processing, selected target 2
The phase content from (i) is converted by the phase address conversion circuit 122 into the address signal of the phase buffer 124 storing the phase to be executed from now on.

The address counter 123 determines a specific address based on the address signal from the phase address conversion circuit 122, accesses it using that address, reads the contents of a predetermined phase, and sends it to the target address via the request/association control circuit 126. i).

Note that the address of the phase buffer 124 specified by the address counter 123 is determined also taking into account a specific instruction from the processor 121.

When the phase processing content is data transfer, the data stored in the data transfer buffer 125 is sent to the data bus a via the request/anok control circuit 126. or,
When data is transferred from the target computer) 2(i), it is stored in the data transfer buffer 125.

After executing one phase, if it is status or message in, the ininator 1 is the phase buffer 12.
4 and read it to determine the next action.

The storage area of the phase buffer 124 is divided into many areas, each of which stores information such as checking the previous state and checking whether the currently executed sequence is good. It is possible to investigate depending on the content.

〔Effect of the invention〕

According to the present invention as described above, each phase process.

This has the advantage that each message process etc. can be executed quickly and efficiently, and the contents of the sequence currently being executed can be easily investigated.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the present invention in detail, FIG. 2 is a block diagram for explaining a conventional example, and FIG. 3 is a system configuration diagram. In the figure, l is the initiator, 11 is the CPU, 12 is the adapter, and 2
(0) to 2(n) are targets, 21 is a controller, 21(0) to 21(n) are devices, 121 is a processor, 122 is a phase address conversion circuit, 123 is an address counter, 124 is a phase buffer, 125 is a A data transfer buffer, 126 a request/anok control circuit, 127 a register, and 128 a data buffer, respectively.

Claims (1)

[Claims] An interface for a small computer system (
In a device that processes through each phase such as selection, identity, command, data transfer, status, and command cop read using the SCSi interface, the contents of each phase of the command and status are stored in the host device (initiator). an area for storing message out contents to be sent from the host device (initiator) to the partner device (target), and a message to be sent from the partner device (target) to the host device (initiator) (1). A phase buffer (124) having an area for storing input contents, etc., and a data transfer buffer (125) for storing transfer data.
an address counter (123) that specifies the address of the phase buffer (124); and an address counter (123) that specifies the address of the phase buffer (124);
) phase address conversion circuit (1
22), and the execution process contents of each phase processed after the selection processing and message out and message in left behind during each phase processing are stored in the phase buffer (12).
4) and a phase control method characterized in that the data is divided and stored in a corresponding area of the data transfer buffer (125), the contents of the corresponding area are read, and control is performed based on the contents.