JPS6259822B2 - - Google Patents

Info

Publication number
JPS6259822B2
JPS6259822B2 JP55033490A JP3349080A JPS6259822B2 JP S6259822 B2 JPS6259822 B2 JP S6259822B2 JP 55033490 A JP55033490 A JP 55033490A JP 3349080 A JP3349080 A JP 3349080A JP S6259822 B2 JPS6259822 B2 JP S6259822B2
Authority
JP
Japan
Prior art keywords
address
bus
signal
byte
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55033490A
Other languages
English (en)
Japanese (ja)
Other versions
JPS564828A (en
Inventor
Sayuaton Beekaa Deebitsuto
Furederitsuku Bantsu Deebitsudo
Jon Euanjirisutei Kaaro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS564828A publication Critical patent/JPS564828A/ja
Publication of JPS6259822B2 publication Critical patent/JPS6259822B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
JP3349080A 1979-06-18 1980-03-18 Common bus communication system Granted JPS564828A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/049,532 US4286321A (en) 1979-06-18 1979-06-18 Common bus communication system in which the width of the address field is greater than the number of lines on the bus

Publications (2)

Publication Number Publication Date
JPS564828A JPS564828A (en) 1981-01-19
JPS6259822B2 true JPS6259822B2 (es) 1987-12-12

Family

ID=21960316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3349080A Granted JPS564828A (en) 1979-06-18 1980-03-18 Common bus communication system

Country Status (6)

Country Link
US (1) US4286321A (es)
EP (1) EP0020908B1 (es)
JP (1) JPS564828A (es)
BR (1) BR8003769A (es)
DE (1) DE3065585D1 (es)
IT (1) IT1148833B (es)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US5526506A (en) * 1970-12-28 1996-06-11 Hyatt; Gilbert P. Computer system having an improved memory architecture
US4479178A (en) * 1981-07-02 1984-10-23 Texas Instruments Incorporated Quadruply time-multiplex information bus
US4811202A (en) * 1981-10-01 1989-03-07 Texas Instruments Incorporated Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package
JPS61175845A (ja) * 1985-01-31 1986-08-07 Toshiba Corp マイクロプロセツサシステム
US4779191A (en) * 1985-04-12 1988-10-18 Gigamos Systems, Inc. Method and apparatus for expanding the address space of computers
US4965723A (en) * 1987-10-23 1990-10-23 Digital Equipment Corporation Bus data path control scheme
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US4873028A (en) * 1988-02-22 1989-10-10 Baltimore Aircoil Company, Inc. Low silhouette cooling tower with trapezoidal fill and method of air flow therethrough
US5001625A (en) * 1988-03-24 1991-03-19 Gould Inc. Bus structure for overlapped data transfer
US5724540A (en) * 1988-03-28 1998-03-03 Hitachi, Ltd. Memory system having a column address counter and a page address counter
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
US5168562A (en) * 1989-02-21 1992-12-01 Compaq Computer Corporation Method and apparatus for determining the allowable data path width of a device in a computer system to avoid interference with other devices
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
EP0597601A1 (en) * 1992-11-13 1994-05-18 National Semiconductor Corporation Reflexively sizing memory bus interface
US5430676A (en) * 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
US5793990A (en) * 1993-06-11 1998-08-11 Vlsi Technology, Inc. Multiplex address/data bus with multiplex system controller and method therefor
GB9315753D0 (en) * 1993-07-30 1993-09-15 Communicate Ltd Digital communication unit monitoring
JP3168552B2 (ja) * 1993-12-17 2001-05-21 インターナショナル・ビジネス・マシーンズ・コーポレ−ション メモリ・アクセス制御システム及びその方法
AU682959B2 (en) * 1994-04-13 1997-10-23 Ericsson Inc. Efficient addressing of large memories
EP0690382B1 (en) * 1994-07-01 2003-01-02 Sun Microsystems, Inc. Computer system with a multiplexed address bus and pipelined write operations
US5715205A (en) * 1996-03-29 1998-02-03 Cypress Semiconductor Corporation Memory with a selectable data width and reduced decoding logic
US5845098A (en) * 1996-06-24 1998-12-01 Motorola Inc. Address lines load reduction
DE19638772A1 (de) * 1996-09-21 1998-03-26 Philips Patentverwaltung Telekommunikationsgerät, insbesondere Mobilfunkendgerät
US6157970A (en) * 1997-09-24 2000-12-05 Intel Corporation Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
US6119189A (en) * 1997-09-24 2000-09-12 Intel Corporation Bus master transactions on a low pin count bus
US6131127A (en) * 1997-09-24 2000-10-10 Intel Corporation I/O transactions on a low pin count bus
US5991841A (en) * 1997-09-24 1999-11-23 Intel Corporation Memory transactions on a low pin count bus
US6243798B1 (en) * 1997-10-28 2001-06-05 Microchip Technology Incorporated Computer system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction
US6567884B1 (en) * 2000-03-21 2003-05-20 Cypress Semiconductor Corp. Endian-controlled counter for synchronous ports with bus matching
US7222202B2 (en) * 2004-02-17 2007-05-22 Broadcom Corporation Method for monitoring a set of semaphore registers using a limited-width test bus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3223982A (en) * 1962-04-06 1965-12-14 Olivetti & Co Spa Electronic computer with abbreviated addressing of data
DE2364254B2 (de) * 1973-12-22 1976-03-18 Schaltungsanordnung fuer datenverarbeitende geraete
DE2364408C3 (de) * 1973-12-22 1979-06-07 Olympia Werke Ag, 2940 Wilhelmshaven Schaltungsanordnung zur Adressierung der Speicherplätze eines aus mehreren Chips bestehenden Speichers
US4156905A (en) * 1974-02-28 1979-05-29 Ncr Corporation Method and apparatus for improving access speed in a random access memory
US4016545A (en) * 1975-07-31 1977-04-05 Harris Corporation Plural memory controller apparatus
US4045782A (en) * 1976-03-29 1977-08-30 The Warner & Swasey Company Microprogrammed processor system having external memory
US4112490A (en) * 1976-11-24 1978-09-05 Intel Corporation Data transfer control apparatus and method
US4158227A (en) * 1977-10-12 1979-06-12 Bunker Ramo Corporation Paged memory mapping with elimination of recurrent decoding

Also Published As

Publication number Publication date
BR8003769A (pt) 1981-01-13
EP0020908A1 (en) 1981-01-07
IT8022426A0 (it) 1980-05-30
DE3065585D1 (en) 1983-12-22
JPS564828A (en) 1981-01-19
EP0020908B1 (en) 1983-11-16
IT1148833B (it) 1986-12-03
US4286321A (en) 1981-08-25

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