JPS6258722A - Programmable logic device - Google Patents

Abstract

PURPOSE:To reduce the number of wasteful programmable elements and to raise the density of integration by forming in advance a functional cell constituted so as to realize a counter or a shift register. CONSTITUTION:The logic of a AND array part is programmable and the logic of a OR array part is fixed. Conductors 2-1, 2-2,... connected to an input terminal are connected to non-inversion input wires 6-1, 6-3,... and inversion input wires 6-2, 6-4,... through input buffer circuits 4-1, 4-2,.... Also, each of AND array conductors 8-1, 8-2,... is connected to sense amplifiers 10-1, 10-2,..., and EPROMs as programmable elements at each cross point of the input wires 6-1, 6-2,... and the AND array conductors 8-1, 8-2,... are provided. The outputs of appropriate number of sense amplifiers 10-1, 10-2,... are connected to OR gates 12-1, 12-i, 12-j,... and the outputs of the OR gates 12-1, 12-i and 12-j are inputted respectively to a F/F14 and functional cells 16 and 18 and the Q-output of the F/F14 is connected to an output terminal 20 and the Q-output is feedbacked to the AND array part. The functional cells 16 and 18 can be used as the shift register or the counter and the output is feedbacked to the AND array part.

Description

Detailed Description of the Invention (Technical Field) The present invention includes programmable elements (hereinafter referred to as programmable elements), and by programming these elements, an arbitrary logic circuit can be configured.
AC programmable logic array) and PAL (
The invention relates to programmable logic devices (PLDs) such as programmable array logic (programmable array logic).

(Prior Art) A programmable logic device has an AND array section and an OR array section, and both or one of the AND array section and the OR array section is provided with a programmable element.

By programming a predetermined programmable element to turn on or off, a desired logic circuit can be constructed from the AND array section and the OR array section.

There is also a device that includes a flip-flop in addition to the AND array section and the OR array section, so that the output of the OR array section can be input to the flip-flop to form a sequential circuit.

Programmable logic with flip-flops
According to the device, by feeding back the output of a flip-flop to an AND array section or an OR array section, logic such as a counter or a shift register can be freely configured.

When increasing the scale of a programmable logic device, if the AND array part is programmable, the size of the array in the AND array part is 2 of the number of inputs i.
It increases in proportion to the product (2i·P) of the multiplication factor and the number of product terms P.

However, as arrays grow larger, programmable
In actual use of the logic device, the wasted area is also large. When constructing a 4-bit counter using

Although 3200 programmable elements are provided, the number of programmable elements actually used is 74.
It is individual. Therefore, most of the programmable elements will not be used. This becomes more noticeable as the scale of the programmable logic device becomes larger.

(Objective) The present invention aims to increase the degree of integration by reducing unnecessary programmable elements in a programmable logic device.

(Configuration) The present invention is a programmable logic device that includes two programmable elements and can configure any logic circuit by programming those elements, and is configured to realize a counter, a shift register, etc. It is made up of functional cells.

The pre-formed functional cells are MSI-sized cells that implement frequently used functions such as counters and registers.

The programmable logic device to which the present invention is applied is a PLA in which both the logic of the AND array section and the logic of the OR array section are programmable, and the logic of the AND array section is programmable and the logic of the OR array section is fixed. The logic of PAL and AND array part is fixed and O
The logic of the R array section includes programmable logic.

As programmable elements, EPROM, EEPRO
M, a junction breakdown type element of a bipolar transistor, a fuse element, etc. can be used.

Examples will be specifically described below.

Figure 1 shows that the logic of the AND array section is programmable and the logic of the AND array section is programmable.
This figure shows an embodiment in which the present invention is applied to a PA in which the logic of the R array section is fixed.

2 1 g 2-21... are conducting wires connected to the input terminals, and the input buffer 7 circuits 4-1.4-2.・・・
. . , non-inverting input line 6-1.6-3.・・・・・・
... and inverted input line 6-2.6-4. ·····It is connected to the.

8-1.8-2. . . . are conducting wires constituting the AND array, and each AND array conducting wire 8-1.8-2
゜... is sense amplifier 10-1.10-2.・
Input line 6 connected to 1.6-2.
6-3°...and AND array conduction! 1i8-1.
8-2. --- An EFROM as a programmable element is provided at each intersection so that the connections can be programmed.

Appropriate number of sense amplifiers 10-1.10-2.・・・・・・
The output of OR gate 12-1. ...12-4
゜12-j , connected to OR gate 1
The output of 2-1 is input to the flip-flop 14 and OR
The output of gate 12-1 is input to functional cell 16.

The output of OR gate 12-j is input to functional cell 18. In the flip-flop 14, the Q output is the output terminal 20.
is connected to A through the input cover sofa circuit 22
It is fed back to the ND array section.

Functional cells 16.18 can be used as 4-bit shift registers or counters as described later, and the output of each functional cell 16.18 is sent to input buffer circuits 24-5.
．． 24-2. It is fed back to the AND array section via .

A plurality of functional cells 16. +8. It is also possible to connect . . . to form a circuit with functions of 8 bits or more.

Although the outputs of the functional cells 16 and 18 are fed back in FIG. 1, they may be outputted to the outside.

FIGS. 2 to 4 show functional cell i6. This functional cell example, which shows a specific example of ia, is configured such that an up counter, a down counter, or a shift register are switched and realized by a common circuit.

FIG. 2 shows the connection relationship between the functional cells 16 and 18.

Functional cell 16. Each X8 includes a circuit C2 serving as a 4-bit counter or shift register, and inputs and outputs data between the functional cells 16 and 18 I', ) 1) 11
HD i 4 and carry person output signal C○.

C4 should be connected or input by transfer gates TG+ to TG4 controlled by the C8 signal.

C, , ] signal is programmed to low level (rOJ), transfer gate TG:=, TG3 is turned off, disconnecting between both functional cells 16 and 18, and transfer gate TGi, TGi is turned on. Each functional cell 16, 18 becomes a 4-bit counter or shift register. Also, the C8 signal is at high level (rlJ
), the transfer gate TG:
, TG3 are turned on to connect both functional cells 16.18, and transfer gates TG1 and TG4 are turned off so that both functional cells 16.18 constitute an 8-bit counter or shift register.

The 62 circuits included in the functional cells 16 and 18 are 4-bit circuits to which four C1 circuits are connected, as shown in FIG. Each C1 circuit is shown in FIG. Here, d
t is a shift register selection signal, and u/d is a signal for selecting an up type or down type of counter. sft
When both #1 and u/d signals are programmed to high level, the circuit in Figure 3 becomes a 4-bit shift register. *When the sft signal is programmed to low level and the u/d signal to high level, It becomes a down counter, and when both the sfL signal and the u/d signal are programmed to low level, it becomes a 4-bit up counter.

The above results are summarized in the following table.

These signals sft, u/d, and C8 need only hold constant values during operation of the programmable logic device, regardless of speed.

In FIG. 5, these signals sft, u/d, .
A circuit for programming C8 is shown.

TGi is a transfer gate shown in FIGS. 2 and 4, and a MOS type EPROM memory cell Q3 is used as a programmable element for programming sft, u/d, and C8.

This programmable element Q3 is the same as the programmable element used in the AND array section of FIG. Q+ is a pull-up element, and Q= is a MOS transistor that limits the voltage applied to the drain of memory cell transistor Q3. If the memory cell transistor Q3 is not written, the node Nl is at a low level, the node N2 is at a high level, and the transfer gate TGi is turned on. Further, when the memory cell transistor Q3 is written, the node N1 becomes high level, the node N2 becomes low level, and the transfer gate TGi is turned off.

In this embodiment, the same programmable element used in the AND array section is used to switch between these functions so that an up counter, a down counter, or a shift register can be realized using a common circuit as a functional cell. Since it can be done with a switch, it is easy for two users to find the optimal structure.
Less waste. Furthermore, since the same functional cells are used, device design is also simplified.

(Effects) According to the present invention, in programmable logic devices such as PLA and PAL, by providing functional cells configured in advance to realize frequently used circuit functions, The logic scale can be increased while suppressing the number of programmable elements in the section.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a specific example of a functional cell including Jt included in the same embodiment, and Fig. 3 is a block diagram showing the 02 circuit in Fig. 2. 4 is a circuit diagram showing the C1 circuit in FIG. 3, and FIG. 5 is a circuit diagram showing a portion for switching the functions of the functional cells in the same embodiment. 6-1.6-2.・・・・・・；Input line, 8-118-
21...; AND array conductor, 12-1 r
...=.12-i+ l 2 J: OR gate. 16.18; Functional cell.

Claims (1)

[Claims] (1) In a programmable logic device that includes programmable elements and can configure any logic circuit by programming those elements, a function configured to realize a counter, shift register, etc. A programmable logic device characterized in that cells are preformed.