JPS61145792A - Memory circuit - Google Patents

Abstract

PURPOSE:To attain the reading or writing of a memory circuit with plural circuits with the same timing in terms of time and to facilitate the easy connection among plural devices, by defining a circuit element having two electrically stable states as a basic cell and connecting plural signal lines and control lines to said basic cell. CONSTITUTION:Both control lines 133 and 138 selected out of different groups are set at '1' at a time. The contents of basic cells 141, 145, 149 and 153 are read out to a group of signal lines 125-128 in the form of the output. While the contents of basic cells 142, 146, 150 and 154 are delivered to a group of signal lines 129-132 respectively. Otherwise the data of one of both groups of control lines are written to or read out of the other group and vice versa as long as those signal lines are connected to the writing circuit of a memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a memory circuit, and facilitates connection with a plurality of external circuits.

Conventional technology FIG. 4 shows an example of the configuration of a conventional memory circuit.

In a conventional storage circuit called a memory, a basic cell serving as a unit of storage is connected to only a single signal line 1 among the signal lines 1 to 4, and it is selected by a group of control lines 5 to 8. Was. For example, a plurality of basic cells 9 to 12 are connected in parallel to this signal line 1, and it is determined which basic cell among the plurality of connected basic cells 9 to 12 is electrically connected to the common signal line. Control lines 5 to 8 to be controlled were input to each basic cell 9 to 12 one tree at a time. Furthermore, the control line 5
- 8 are common control lines for a plurality of basic cells in parallel, and one control line 5 connects a plurality of basic cells 9.
, 13, 17.2) to the corresponding signal lines 1.2, 3.4 were simultaneously controlled. When the basic cell and the signal line are electrically connected, a voltage level is generated in the signal line depending on the internal state of the basic cell, and the stored contents are read out, or conversely, the voltage level of the signal line is Accordingly, the internal state of the basic cell is newly determined and the memory is written.

FIG. 5 shows an example of the configuration of a basic cell of a memory circuit.

In this figure, 25 is a signal line, 26 is a control line, 27 is a control gate, 28 and 29 both constitute a two-state circuit element, and 2
7 to 29 form a basic cell 30.

Note that depending on the configuration of the basic cell, as shown in FIG. A control gate 35 is connected to the other signal line 32 via
There is a basic cell 38 consisting of memory elements 36 and 37, each having an opposite voltage level, and two sets of signal lines may be used to transmit one signal.

Problems to be Solved by the Invention However, in the configuration of such a memory circuit, it is not possible to simultaneously control a set of basic cells controlled by a plurality of different control lines. When it is desired to use the memory circuit as a common memory circuit, there is a drawback that the memory circuit must be used at different timings. Another drawback is that writing and reading operations cannot be performed simultaneously.

11. The present invention solves the above-mentioned drawbacks, and provides a memory circuit that allows multiple circuits to read or write at the same timing, and facilitates connection of multiple devices. It is something.

Means for Solving the Problems In summary, the present invention uses a circuit element having two electrically stable states as a basic cell, and connects a plurality of signal lines and a plurality of control lines to each of the basic cells. This is a memory circuit.

Effect: With this configuration, different control signals can be applied to the basic cell from multiple control systems at the same time, and different signals can be formed on multiple signal lines. Therefore, reading or writing can be performed at the same timing. It is possible to do so.

Embodiment FIG. 1 shows an embodiment of the structure of a memory circuit according to the present invention. In the figure, 125 to 132 are signal lines, and 133
˜140 is a control line. The signal lines 125 to 128 and the signal lines 129 to 132 each constitute a set of signal lines connected to one output system or input system. Still control line 133~1
36, control lines 137 to 140 similarly form a pair of control lines connected to different control systems.

In this configuration example, the memory circuits 141 to 166 can be connected to two different circuit systems, and the signal line sets 125 to 1
28 and control line sets 133 to 136 are connected to one device, and signal line sets 129 to 132 and control line sets 137 to 14 are connected to one device.
0 connects to the other device. And one basic cell is
It is connected to two tree signal lines and two tree control lines, and the two signal lines belong to different signal line groups, and the two control lines also belong to different control line groups. There is.

FIG. 2 shows an example of the configuration of the basic cell corresponding to FIG. 1. As shown in the figure, one control line 161 is input to the gate of the control element (FET) 1es,
By turning 0N and OFF, one signal line 15
9 and the basic cell 157, and the other control line 160 similarly connects 1cFET1e4iON, OFF
and controls the electrical connection between the other signal line 168 and the basic cell 167.

In each set of control lines, two or more control lines will never become "1" at the same time, so two or more basic cells will be electrically connected to one signal line at the same time. There isn't.

In such a configuration, the following operations are possible, for example. The contents of the control line 133 and the control line, which are each a tree in a set of different control lines, are read out as output, and at the same time, the contents of the basic cells 142, 146, 150, and 154 are read out in the set of signal lines 129 to 132. is output. Alternatively, if the signal line is connected to the writing circuit of the memory circuit at that time, one signal line set 125
~128 (or 129-132) is written to one basic cell (141, 145, 149, 153 (or 142, 148, 150, 154)), and read from the other in the same manner as described above.

Alternatively, if both sets of signal lines are connected to the write circuit at that time, the basic cell 141.1
45,149,153 and 142°146.150,15
Independent data is written to 4.

Also, control lines 133 and 137 in the same column are “1” at the same time.
In the case of reading with both, the same data is output to the two sets of signal lines.

When one set of signal lines is connected to a write circuit, the operation differs depending on the design. When both are write circuits, such control lines in the same column must be prohibited from becoming "1" at the same time.

In this way, by having two sets of signal lines and two sets of control lines that control them independently, it becomes possible for two different devices to use the same memory circuit at the same timing.

The above is a case where two signal lines are connected to the basic cell, but it goes without saying that a plurality of signal lines, such as three or four, may be provided. Also, as shown in Figure 6, even when the signal line and return signal line are connected to the basic cell in pairs, it is possible to connect two pairs of signal lines as shown in Figure 3. allows the storage circuit to be connected to two devices. In FIG. 3, 167 to 170 are signal lines, 171 and 172 are control lines, 174 and 176 are memory elements, and 175 to 178 are control gate elements.

Also, in this case, it goes without saying that a plurality of signal line pairs may be provided, such as three or four. In the above example, since the control line is connected to the basic cell, it is of course necessary to provide a sufficient length to control the independent signal line. Also,
Of course, the two sets of signal numbers and the two sets of control lines may be connected to any circuit outside of this basic cell arrangement, and they do not need to be connected to multiple separate devices. Of course.

Effects of the Invention According to the present invention, it is possible to realize a memory circuit in which reading or writing can be performed by a plurality of devices at the same timing, and the plurality of devices can be easily connected.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 are block diagrams of memory circuits according to embodiments of the present invention, and FIGS. 4, 5, and 6 are block diagrams of conventional memory circuits. 125-132... Signal line, 133-140.
...Control line, 141-166...Basic cell, 164°165, 175-178...River/FET
0 Name of agent Patent attorney Souo Nakao Haga 1 person Figure 1 Figure 4 Figure 5 Figure 6

Claims (2)

[Claims] (1) A circuit having two electrically stable states is used as a basic cell, and has a configuration in which these basic cells are arranged, and a plurality of signal lines connected to the basic cell, and a number of the signal lines. A memory circuit comprising a plurality of corresponding basic cells and a control line for controlling electrical connection of signal lines. (2) In the basic cell, the drains of a plurality of MOS transistors are connected to one or both of the connection parts of a pair of inverters whose input and output parts are electrically connected, and the other electrode is used as a signal line, and 2. The memory circuit according to claim 1, wherein the gate is a control line.