JPS6258692A - Manufacture of semiconductor light emitting device - Google Patents

Manufacture of semiconductor light emitting device

Info

Publication number
JPS6258692A
JPS6258692A JP60198951A JP19895185A JPS6258692A JP S6258692 A JPS6258692 A JP S6258692A JP 60198951 A JP60198951 A JP 60198951A JP 19895185 A JP19895185 A JP 19895185A JP S6258692 A JPS6258692 A JP S6258692A
Authority
JP
Japan
Prior art keywords
layer
inp
semiconductor
light emitting
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60198951A
Other languages
Japanese (ja)
Inventor
Tamotsu Iwasaki
保 岩崎
Susumu Kashiwa
柏 享
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP60198951A priority Critical patent/JPS6258692A/en
Publication of JPS6258692A publication Critical patent/JPS6258692A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054Methods of obtaining the confinement
    • H01S5/2095Methods of obtaining the confinement using melting or mass transport
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Weting (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To improve the controllability of the width of an active layer and to improve the controllability and efficiency for burying high-resistance InP into an etching part formed in a double hetero junction by fabricating a semiconductor layer by a predetermined step. CONSTITUTION:On a p-InP substrate 1, a p-InP buffer layer 2, a p-InP cladding layer 3, a p-InGaAsP active layer 4, an n-InP cladding layer 5, and an n-InP cap layer 6 are laminated in order, after which a tungsten film 7 is vapor- deposited. Next, the film 7 is patterned to form a stripe electrode 8 which is then used as a mask for the mesa etching of the layer 6 to 3. Further, the layer 4 is over-etched. Subsequently, mass transportation is done to bury the active layer 4' by the InP layer 10. After that, the buried layer 11 consisting of InP crystal is epitaxially grown to fabricate a semiconductor laser.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体発光装置の製造方法に関し、特に埋込み
層の形成工程を改良した半導体発光装置の製造方法に係
わる。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly to a method for manufacturing a semiconductor light emitting device in which the process of forming a buried layer is improved.

〔従来挟術及び問題点〕[Conventional pincer technique and problems]

半導体発光装置は、小形、高効率、軽量、機械的撮動に
強い等半導体素子に共通な特長の他に、高速の直接変調
が可能、光ファイバとの高効率結合が可能等の特長を持
つことから、近年、オプトエレクトロニクス用光源とし
て実用化が進んできているが、その利用分野を更に拡大
するためには、製造工程の改良による大幅なコストダウ
ンが必要である。
Semiconductor light emitting devices have features common to semiconductor devices such as small size, high efficiency, light weight, and resistance to mechanical imaging, as well as features such as high-speed direct modulation and high efficiency coupling with optical fibers. Therefore, in recent years, it has been put into practical use as a light source for optoelectronics, but in order to further expand its field of use, it is necessary to significantly reduce costs by improving the manufacturing process.

ところで、半導体発光装置の一つとして、I[[−V族
化合物半導体の結晶でダブルヘテロ接合構造とし、かつ
導波路をストライブ状にするために活性層より屈折率の
低い■−v族化合物半導体で埋込み、更に結晶を糖量し
て得られる接合面に対して垂直な糖量面を反射面とする
埋込み型半導体レーザが知られている。かかる半導体レ
ーザ(InP系の半導体レーザ)は、例えば従来より以
下に説明する方法により製造されている。
By the way, as one of the semiconductor light emitting devices, in order to have a double heterojunction structure with a crystal of an I[[-V group compound semiconductor and to form a waveguide in a stripe shape, a ■-V group compound semiconductor having a lower refractive index than the active layer is used. An embedded type semiconductor laser is known in which a semiconductor laser is embedded with a semiconductor, and the crystal is further filled with sugar to form a reflecting surface that is perpendicular to the bonding surface. Such semiconductor lasers (InP-based semiconductor lasers) have been conventionally manufactured, for example, by the method described below.

まず、n型1nP基板上にn型1nPからなるクラッド
層、InGaAsPからなる活性層及びp型のInPか
らなるクラッド層を順次積層してダブルヘテロ接合を形
成した後、最上居のクラッド層上に5i02パターンを
選択的に形成する。
First, a cladding layer made of n-type 1nP, an active layer made of InGaAsP, and a cladding layer made of p-type InP are sequentially laminated on an n-type 1nP substrate to form a double heterojunction. 5i02 pattern is selectively formed.

つづいて、該SiO+パターンをマスクとしてダブルへ
ゾロ接合を所定深さまでメサエッチングする。ひきつづ
き、液相成長法によりエツチング部にp型及びn型のl
nPを交互にして埋込み層を選択的に成長させる。次い
で、SiO2パターンを除去し、クラッド層と基板裏面
に正負の1fflを形成した後、ダブルヘテロ接合に対
して垂直方向に糖量して、反射面となる勇開面を形成し
てInPのクラッド層と埋込み層によってInGaAs
Pの活性層領域に電流と光の閉込めを行った埋込み型半
導体レーザを製造する。
Subsequently, using the SiO+ pattern as a mask, a double-to-zero junction is mesa-etched to a predetermined depth. Subsequently, p-type and n-type l are formed in the etched area by liquid phase growth.
The buried layer is selectively grown by alternating nP. Next, after removing the SiO2 pattern and forming positive and negative 1ffl on the cladding layer and the back surface of the substrate, sugar is applied in the direction perpendicular to the double heterojunction to form an open plane that will serve as a reflective surface, and the InP cladding is InGaAs layers and buried layers
A buried semiconductor laser is manufactured in which current and light are confined in a P active layer region.

しかしながら、上述した製造方法では液相成長法を採用
するため、量産性に欠け、しかも膜厚制御性が低いとい
う問題があった。
However, since the above-described manufacturing method employs a liquid phase growth method, it lacks mass productivity and has problems in that film thickness controllability is low.

(発明の目的〕 本発明は、活性層の幅を容易、かつ再現性よく制御性で
き、しかもダブルヘテロ接合に形成したエツチング部に
高抵抗のInP結晶層を選択的に効率よく、かつ制御性
よく埋込むことが可能で、更にマスク材をそのまま電極
として利用でき、工程の大幅な短縮化及び高性能化を達
成した半導体発光装置の製造方法を提供しようとするも
のである。
(Objective of the Invention) The present invention enables easy and reproducible control of the width of the active layer, and selectively and efficiently deposits a high-resistance InP crystal layer in the etched portion formed in the double heterojunction. It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device that can be easily embedded, can use the mask material as it is as an electrode, and has achieved a significant reduction in process steps and improved performance.

〔発明の概要〕[Summary of the invention]

本発明は、InP基板上にダブルヘテロ構造を有するl
nP系半導体層を形成する工程と、この半導体層上に高
融点金属の電極を形成する工程と、この電極をマスクと
して化学的エツチングにより前記半導体層を所望深さ選
択的に除去すると共に、該半導体層の構成材である活性
層をオーバエツチングする工程と、リンを含む雰囲気で
熱処理して前記オーバーエツチング部をInPで埋込む
工程と、気相エピタキシャル成長により前記半導体層の
エツチング部に高抵抗の101層を選択的に結晶成長さ
せる工程とを具備したことを特徴とするものである。か
かる本発明によれば、既述の如く活性層の幅を容易、か
つ再現性よく制御性でき、しかもダブルヘテロ接合に形
成したエツチング部に高抵抗のInP結晶層を選択的に
効率よく、かつ制御性よく埋込むことが可能で、更にマ
スク材をそのまま電極として利用でき、工程の大幅な短
縮化及び高性能化を達成した半導体発光装置を得ること
ができる。
The present invention provides an l having a double heterostructure on an InP substrate.
A step of forming an nP-based semiconductor layer, a step of forming an electrode of a high melting point metal on this semiconductor layer, and selectively removing the semiconductor layer to a desired depth by chemical etching using this electrode as a mask. A process of over-etching the active layer, which is a constituent material of the semiconductor layer, a process of heat-treating in an atmosphere containing phosphorus to fill the over-etched part with InP, and a process of injecting a high-resistance layer into the etched part of the semiconductor layer by vapor phase epitaxial growth. This method is characterized by comprising a step of selectively growing crystals of the 101 layer. According to the present invention, the width of the active layer can be easily and reproducibly controlled as described above, and a high-resistance InP crystal layer can be selectively and efficiently formed in the etched portion formed in the double heterojunction. It is possible to embed the mask material with good controllability, use the mask material as it is as an electrode, and obtain a semiconductor light-emitting device with significantly shortened process steps and improved performance.

〔発明の実施例] 以下、本発明をInP系の埋込み型半導体レーザに適用
した例について第1図〜第4図を参照して詳細に説明す
る。
[Embodiments of the Invention] Hereinafter, an example in which the present invention is applied to an InP-based buried semiconductor laser will be described in detail with reference to FIGS. 1 to 4.

まず、p型のInP基板1上に厚さ0.5μmのp型I
nPからなるバッファ層2、厚さ2μmのn型1nPか
らなるクラッド層3、厚さ0. 1μmのp型InGa
ASPからなる活性層4、厚さ2μmのn型1nPから
なるクラッド層5及び厚さ0.2μmのn型1nPから
なるキャップ層6を順次積層した後、該キャップ層6上
にスパッタリング法により厚さ0.2μmのタングステ
ン膜7を蒸着した(第1図図示)。つづいて、タングス
テン膜7をパターニングして40μm以下の幅を有する
ストライブ状の電極8を形成した後、該電極8をマスク
としてBr2−メタノール液によりキャップ層6からク
ラッド層3までを選択的にメサエッチングしてエツチン
グ部9を形成した。
First, a p-type I film with a thickness of 0.5 μm is placed on a p-type InP substrate 1.
A buffer layer 2 made of nP, a cladding layer 3 made of n-type 1nP with a thickness of 2 μm, and a thickness of 0. 1 μm p-type InGa
After sequentially laminating an active layer 4 made of ASP, a cladding layer 5 made of n-type 1nP with a thickness of 2 μm, and a cap layer 6 made of n-type 1nP with a thickness of 0.2 μm, a thick layer is formed on the cap layer 6 by sputtering. A tungsten film 7 having a thickness of 0.2 μm was deposited (as shown in FIG. 1). Subsequently, after patterning the tungsten film 7 to form a striped electrode 8 having a width of 40 μm or less, the electrodes 8 from the cap layer 6 to the cladding layer 3 are selectively coated with a Br2-methanol solution using the electrode 8 as a mask. Etched portions 9 were formed by mesa etching.

ひきつづき、硫酸、過酸化水素及び水からなるエツチン
グ液により活性層4をオーバエツチングしたく第2図図
示)。
Subsequently, the active layer 4 is over-etched using an etching solution consisting of sulfuric acid, hydrogen peroxide, and water (as shown in Figure 2).

次いで、温度700℃でPH3の雰囲気に曝してマスト
ランスポートを行った。この時、第3図に示すようにオ
ーバエツチングされた活性層4の上下のクラッド層3.
5のInがオーバエツチング部に移動すると共に、雰囲
気中のPがその中に拡散されてInP層10で埋込まれ
た所定幅の活性層4′が形成された。
Next, mass transport was performed by exposing the sample to a PH3 atmosphere at a temperature of 700°C. At this time, as shown in FIG. 3, the cladding layers 3 above and below the overetched active layer 4 are formed.
At the same time, the In of No. 5 moved to the overetching area, and the P in the atmosphere was diffused into the overetching area, thereby forming an active layer 4' of a predetermined width filled with the InP layer 10.

次いで、水素(キャリアガス)6000sccm。Next, hydrogen (carrier gas) at 6000 sccm.

トリメチルインジウム7 secm及びホスフイン50
0 secmの原料ガスを650℃の温度下で分解させ
る気相エピタキシャル成長法により高抵抗のInP結晶
を成長させた。この時、InP結晶は、第4図に示すよ
うにタングステンからなる電極8には全く成長せず、エ
ツチング部9のみに選択的に成長して、前記正M極8表
面と同レベルのInP結晶からなる埋込み層11が形成
された。
Trimethylindium 7 sec and phosphine 50
A high-resistance InP crystal was grown using a vapor phase epitaxial growth method in which 0 sec of source gas is decomposed at a temperature of 650°C. At this time, as shown in FIG. 4, the InP crystal does not grow at all on the electrode 8 made of tungsten, but selectively grows only on the etched part 9, and the InP crystal is at the same level as the surface of the positive M pole 8. A buried layer 11 was formed.

この後、図示しないが基板1裏面を所望の厚さ研磨し、
AU−ae−N+の合金からなる負電極を形成し、該基
板(ウェハ)のダイシング、埋込み層11の長さ方向に
対して直交する方向への見開を行なって、共擾器として
の糖量面(反射面)を有する半導体レーザを製造した。
After this, although not shown, the back surface of the substrate 1 is polished to a desired thickness.
A negative electrode made of an alloy of AU-ae-N+ is formed, and the substrate (wafer) is diced and spread in a direction perpendicular to the length direction of the buried layer 11, and the sugar as a coagulator is formed. A semiconductor laser having a reflective surface was manufactured.

しかして、本発明によればキャップ1IlG上に40μ
m以下の幅を有するタングステンからなるストライブ状
の電極8を形成し、該電極8をマスクとしてキャップ層
6からクラッド層3までの半導体層をエツチングし、更
に活性層4をオーバエツチングした後、所定温度のPH
3雰囲気に曝すマストランスボートを行うことによって
、活性層4のオーバエツチング部をInP層で埋込むこ
とができる。その結果、活性!!4′の幅を容易にかつ
精度よく制御でき、ひいては閾値電流の小さい半導体レ
ーザを簡単に製造できる。
Therefore, according to the present invention, 40μ
After forming a strip-shaped electrode 8 made of tungsten having a width of less than m, and etching the semiconductor layers from the cap layer 6 to the cladding layer 3 using the electrode 8 as a mask, and further over-etching the active layer 4, PH at a given temperature
By performing mass transfer by exposing the active layer 4 to three atmospheres, the overetched portion of the active layer 4 can be filled with an InP layer. As a result, it is active! ! The width of 4' can be easily and accurately controlled, and as a result, a semiconductor laser with a small threshold current can be easily manufactured.

また、前記選択的なエツチングによりエツチング部9を
形成した後、気相エピタキシャル成長を行うことによっ
て、該電極8上に高抵抗のInP結晶が成長することな
く、エツチング部9のみに同InP結晶を選択的に成長
でき、埋込み層11を形成できる。しかも、前記気相エ
ピタキシャル成長の工程でタングステンからなる電極8
とキャップ層6との間に良好なオーミック接触がなされ
る。従って、エツチング部9に埋込み層11を制御性よ
く、かつ効率的に形成でき、更に選択的な結晶成長に使
用したマスク材をそのまま正電極として利用できるため
、工程が大幅に短縮され、ひいては^性能め半導体レー
ザを量産的に得ることが可能となる。
Furthermore, by performing vapor phase epitaxial growth after forming the etched portion 9 by the selective etching, the InP crystal with high resistance is not grown on the electrode 8, and the same InP crystal is selected only for the etched portion 9. The buried layer 11 can be formed. Moreover, in the vapor phase epitaxial growth process, the electrode 8 made of tungsten is
A good ohmic contact is made between the cap layer 6 and the cap layer 6. Therefore, the buried layer 11 can be formed in the etched portion 9 with good controllability and efficiency, and the mask material used for selective crystal growth can be used as it is as a positive electrode, so the process is significantly shortened, and as a result, It becomes possible to mass-produce high-performance semiconductor lasers.

なお、上記実施例では高融点金属として、タングステン
(W)を用いたが、MOlTa、Ti。
In the above embodiment, tungsten (W) was used as the high melting point metal, but MOLTa, Ti.

Pt、Re、lr等の他の高融点金属を使用してもよい
。また、かかる高融点金属膜の蒸着に際して、その模の
パターニングにより形成される電極とInP半導体層と
のオーミック性を向上するために、MO等のドーパント
を混入させながら高融点金属膜を蒸着したり、高融点金
属の下地としてAffiやN1等の比較的低融点の金属
膜を形成したりしてもよい。
Other high melting point metals such as Pt, Re, Ir may also be used. In addition, when depositing such a high melting point metal film, in order to improve the ohmic properties between the electrode formed by patterning the pattern and the InP semiconductor layer, the high melting point metal film may be deposited while mixing a dopant such as MO. Alternatively, a relatively low melting point metal film such as Affi or N1 may be formed as a base for the high melting point metal.

上記実施例においては、半導体レーザ特性の再現性等を
良好にする目的で、p型InPバッファ層2、n型In
Pキャップ層6を成長されているが、場合によってはこ
れらを省略することも可能である。また、n型1nP基
板の代わりにn型InP基板を用いて発光装置を製造す
ることも勿論可能である。
In the above embodiment, in order to improve the reproducibility of semiconductor laser characteristics, the p-type InP buffer layer 2, the n-type InP buffer layer 2,
Although the P cap layer 6 is grown, it is possible to omit this depending on the case. Furthermore, it is of course possible to manufacture a light emitting device using an n-type InP substrate instead of an n-type 1nP substrate.

上記実施例において、選択的な気相エピタキシャル成長
を行う前のエツチング部の深さは、任意でよく、例えば
基板に達する深いエツチング部を形成しても実施例と同
様な効果を発揮できる。
In the above embodiments, the depth of the etched portion before performing selective vapor phase epitaxial growth may be arbitrary. For example, even if a deep etched portion reaching the substrate is formed, the same effects as in the embodiments can be achieved.

上記実施例では、InP系の半導体レーザについて説明
したが、埋込み構造を有する発光ダイオードや面発光型
半導体レーザにも同様に適用できる。
In the above embodiment, an InP-based semiconductor laser has been described, but the present invention can be similarly applied to a light-emitting diode having a buried structure or a surface-emitting type semiconductor laser.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本発明によれば活性層の幅を容易、
かつ再現性よく制御性でき、しかもダブルヘテロ接合に
形成したエツチング部に高抵抗のInP結晶層を選択的
に効率よく、かつIII III性よく埋込むことが可
能で、更にマスク材をそのまま電極として利用でき、工
程の大幅な短縮化及び高性能化を達成した半導体発光装
置の製造方法を提供できる。
As detailed above, according to the present invention, the width of the active layer can be easily adjusted.
Moreover, it can be controlled with good reproducibility, and moreover, it is possible to selectively and efficiently embed a high-resistance InP crystal layer in the etched portion formed in the double heterojunction with good III-III properties, and furthermore, it is possible to use the mask material as it is as an electrode. It is possible to provide a method for manufacturing a semiconductor light emitting device, which can be used to significantly shorten the process and achieve high performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は本発明の実施例における埋込み型半導
体レーザの製造工程を示す断面図である。 1・・・n型1nP基板(ウェハ)、 2・・・n型1nPのバッファ層、3・・・n型1nP
のクラッド層、4.4 ” ・I)型1 nGaAsP
の活性層、5・・・n型1nPのクラッド層、6・・・
n型1nPのキャップ層、8・・・タングステンからな
る電極、9・・・エツチング部、11・・・高抵抗In
Pからなる埋込み層。 出願人代理人 弁理士  鈴江武彦 C−In (’Q       −− CL)\丁C〜
1 to 4 are cross-sectional views showing the manufacturing process of a buried semiconductor laser according to an embodiment of the present invention. 1... N-type 1nP substrate (wafer), 2... N-type 1nP buffer layer, 3... N-type 1nP
cladding layer, 4.4” ・I) type 1 nGaAsP
active layer, 5... n-type 1nP cladding layer, 6...
n-type 1nP cap layer, 8... electrode made of tungsten, 9... etching part, 11... high resistance In
A buried layer consisting of P. Applicant's representative Patent attorney Takehiko Suzue C-In ('Q -- CL)\Ding C~

Claims (2)

【特許請求の範囲】[Claims] (1)InP基板上にダブルヘテロ構造を有するInP
系半導体層を形成する工程と、この半導体層上に高融点
金属の電極を形成する工程と、この電極をマスクとして
化学的エッチングにより前記半導体層を所望深さ選択的
に除去すると共に、該半導体層の構成材である活性層を
オーバエッチングする工程と、リンを含む雰囲気で熱処
理して前記オーバーエッチング部をInPで埋込む工程
と、気相エピタキシャル成長により前記半導体層のエッ
チング部に高抵抗のInP層を選択的に結晶成長させる
工程とを具備したことを特徴とする半導体発光装置の製
造方法。
(1) InP with double heterostructure on InP substrate
a step of forming a high-melting point metal electrode on this semiconductor layer, selectively removing the semiconductor layer to a desired depth by chemical etching using this electrode as a mask, and removing the semiconductor layer to a desired depth. A process of over-etching the active layer, which is a constituent material of the layer, a process of heat-treating in an atmosphere containing phosphorus to fill the over-etched part with InP, and injecting high-resistance InP into the etched part of the semiconductor layer by vapor phase epitaxial growth. 1. A method of manufacturing a semiconductor light emitting device, comprising the step of selectively growing crystals of a layer.
(2)高融点金属がタングステンであることを特徴とす
る特許請求の範囲第1項記載の半導体発光装置の製造方
法。
(2) The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the high melting point metal is tungsten.
JP60198951A 1985-09-09 1985-09-09 Manufacture of semiconductor light emitting device Pending JPS6258692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60198951A JPS6258692A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60198951A JPS6258692A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPS6258692A true JPS6258692A (en) 1987-03-14

Family

ID=16399656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60198951A Pending JPS6258692A (en) 1985-09-09 1985-09-09 Manufacture of semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS6258692A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995023445A1 (en) * 1994-02-24 1995-08-31 British Telecommunications Public Limited Company Semiconductor device
US5985685A (en) * 1994-02-24 1999-11-16 British Telecommunications Public Limited Company Method for making optical device with composite passive and tapered active waveguide regions
JP2001156398A (en) * 1999-05-19 2001-06-08 Canon Inc Method for fabricating semiconductor element, semiconductor element, and gyro
JP2009123720A (en) * 2007-11-09 2009-06-04 Sanken Electric Co Ltd Semiconductor light-emitting device and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128784A (en) * 1982-01-27 1983-08-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor light-emitting device
JPS58196088A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Semiconductor laser element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128784A (en) * 1982-01-27 1983-08-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor light-emitting device
JPS58196088A (en) * 1982-05-12 1983-11-15 Hitachi Ltd Semiconductor laser element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995023445A1 (en) * 1994-02-24 1995-08-31 British Telecommunications Public Limited Company Semiconductor device
US5985685A (en) * 1994-02-24 1999-11-16 British Telecommunications Public Limited Company Method for making optical device with composite passive and tapered active waveguide regions
JP2001156398A (en) * 1999-05-19 2001-06-08 Canon Inc Method for fabricating semiconductor element, semiconductor element, and gyro
JP2009123720A (en) * 2007-11-09 2009-06-04 Sanken Electric Co Ltd Semiconductor light-emitting device and its manufacturing method

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