JPS6258567B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude control device that can effectively perform multiplication operations between discrete values of different sampling frequencies.

Digital signal processing technology has been widely introduced into various control devices with the development of A/D converters and the like.
For example, digital signal control is also considered important in so-called PCM recording, in which an audio signal is converted to a digital signal and recorded and reproduced for the purpose of improving the signal-to-noise ratio of the signal. When adjusting the level of a digital signal in such digital signal control, it is generally achieved by multiplying the digital signal by a digital control signal value as an attenuation coefficient. For example, by multiplying a digitized information signal to be subjected to level adjustment by a digital value of several bits as a gain value, a level-controlled digitized information signal can be obtained.

By the way, the dynamic range uses a fader (gain setter) to output a 96dB audio signal.
In the case of variable setting from 0 to -∞ in 0.25 dB steps, 385 fader steps are required, and 9 bits of control information are required to represent this as a digital value. The above-mentioned level difference of 0.25 dB is almost impossible to discern because it corresponds to a sound level of -80 dB to the human ear.
Therefore, it can be said that substantially continuous variable settings can be made despite the stepwise gain control described above.

On the other hand, when digitally encoding the audio signal with high precision and high fidelity, it is generally converted into a 16-bit signal. In order to control this signal stably and accurately, a stable and accurate level control signal (digital signal) is required. Therefore, for example, an amplitude control device configured as shown in FIG. 1 is used.

In FIG. 1, reference numeral 1 denotes a variable resistor as a fader, to both ends of which a voltage V is applied from a stabilized DC power source (not shown). This resistor 1 has a so-called B-curve damping characteristic, and a voltage value proportional to the sliding position moved linearly or the rotational angular position moved rotationally is extracted from its sliding contact. It can be done. This voltage value (analog signal)
is input to an addressing control device 3 whose main component is an A/D converter 2. This addressing control device 3 converts and outputs, for example, a 9-bit digital signal corresponding to the voltage value and provides it as an addressing signal for the memory 4. This memory 4 consists of, for example, ROM (read only memory),
It constitutes a conversion table between the adjustment position of the fader and the corresponding signal level, and control information of a predetermined change characteristic is sequentially written in advance at each address. For example, address 0 has an information value of -0dB (=1.0000), and address 1 has a value of -0dB (=1.0000).
Information value of 0.25dB (=0.97163), - at address 2
0.50dB (=0.94406), -25dB for address 100
(=0.05634), -75dB (=
0.00018) and 385, an information value of -∞dB (=0.00000) is written as digital information. Each of these digital information values is addressed by a digital signal outputted from the addressing control device 3, that is, an addressing signal, and is selectively read out. The information is then input to the digital multiplier 5 as level adjustment information, and multiplied by the PCM encoded audio signal. In this way, the audio signal is indirectly level-adjusted (amplitude adjusted) by the level setting by the variable resistor 1 and output.

By the way, in this device configured as described above, when the audio signal is a 16-bit digital signal and the gain is to be adjusted with high precision using the level adjustment information expressed in 16 bits on this signal, the address specification of the memory 4 is As for information, considering the auditory static discrimination threshold as mentioned above, digital information of about 9 bits is sufficient to achieve the purpose.
From the perspective of dynamic auditory characteristics, there are cases where this is extremely inadequate, as will be described later. Furthermore, if the potential change of the slider of the resistor 1 is faster than the sampling period (A/D converter 2) of the level adjustment information, the change of the information may occur in multiple steps in one sampling period. This can lead to serious problems. For example, as shown in FIG. 2, which shows the level response of the output signal to a change in the resistor 1, when the amplitude of an input signal kept at a constant level is varied, a sharp level change may occur. However, ΔT
is the conversion time required for the addressing controller 3 and the memory 4 to convert the voltage set by the resistor 1 into a digital signal as level adjustment information, that is, the period of the level adjustment signal. It goes without saying that the arithmetic processing time of the digital multiplier 5 and the D/A conversion time at the final stage are set to be equal to or less than the sampling period of the audio signal and sufficiently shorter than the ΔT. . For example, set the audio signal sampling period to 20μs.
In this case, the calculation processing time is set to 5 μs, the D/A conversion time is set to 10 μs, and ΔT is set to about 2 μs. However, if the resistor 1 is varied to give a change in the output signal level as shown at A in the figure, the output signal will appear as a step-like change as shown at B in the figure. Since the step unit ΔG at this time is 0.25 dB as shown earlier, the level adjustment information is T ₁
As shown in the interval between ~ _T7 , there is a level difference of 0.25 dB between ΔT. As mentioned above, regarding this level change, no particular difference in level is recognized in terms of auditory sense. However, when resistor 1 is suddenly operated as shown in the period T ₇ to _{T 9} , the change in level adjustment information occurs in steps as described above, which generally produces a click sound, which is not smooth to the human ear. You may not feel it as a change in level. That is, when the change in characteristic A is faster than ΔT, the step of change in output B becomes larger. For example, in the section T ₇ to _{T 8} in Figure 2, there is a step change with a level difference of 2.5 dB, which is perceived by the human ear as a more rapid level change, and is accompanied by a large click noise, making it audible. This is not desirable as it gives a pleasant sensation. Therefore, in order to realize a digitally controlled level adjuster that can obtain extremely natural level changes in terms of auditory sense, including problems such as click noise, it is necessary to
Make the step level even smaller than 0.25dB,
The conversion time ΔT must also be made small enough to respond sufficiently to the voltage set by the resistor 1.

Now, if we consider the variable speed of this resistor 1, we can see that the time required to change the output level from 0 to -∞ by moving the resistor 1 in a very ordinary way by hand is, for example, Several hundred ms to several seconds
However, depending on the case, it may take an extremely short time. Therefore, although ΔT of several ms would normally be sufficient, it is required to be several tens of μs or approximately the same as the sampling period of the audio signal. For this reason, problems and inconveniences have arisen in that a high-speed A/D converter must be used as the A/D converter 2, and a memory with a short recall time must be used as the memory 4.

On the other hand, reducing the step level to less than 0.25 dB means increasing the number of bits of the A/D converter 2, and thus increasing the memory capacity of the memory 4. This, when combined with the above-mentioned ΔT problem, requires the use of an A/D converter and memory with higher speed, higher bits, or larger capacity than necessary, leading to an increase in the price of the entire device. Moreover, when using a multiplexer in the same device to perform time-division processing such as arbitrarily adjusting the level of input signals of multiple channels, even higher-speed A/D converters and memory are required. It was extremely difficult to realize this.

The present invention has been made in consideration of these circumstances, and its purpose is to generate level control signals without using high-speed, high-bit, or large-capacity A/D converters, memories, etc. An object of the present invention is to provide an amplitude control device that can reduce click noise that gives a feeling of discomfort by performing appropriate interpolation processing on a digital signal given as a digital signal, and can perform aurally smooth level adjustment.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic diagram of a device that is the premise of the present invention, and its feature is that an interpolation calculation device 6 and a shift register 7 are added to the conventional amplitude adjustment device shown in FIG. Components that are the same as those of the conventional device are given the same reference numerals, and the interpolation calculation device 6 and shift register 7, which are the features of the present device, will be described below. The level adjustment signal D outputted from the memory 4 is led to a subtracter 8, and a delay signal (gain value) S _t -1, which will be described later, is subtracted therefrom. The subtracted value output from the subtracter 8 is multiplied by 1/2 ⁿ by a coefficient unit 9 and then led to an adder 10 . However, n=
It is a positive integer of 1, 2, 3, 4... The coefficient unit 9 will be described in detail later, but it performs coefficient processing by simply truncating the digital signal value from the LSB side. The adder 10 adds the delayed signal S _t -1 to the output of the coefficient multiplier 9 to obtain an interpolated level adjustment signal S _t , that is, a new gain value S _t . This gain value S _t is input to the digital multiplier 5 and stored in the shift register 7, and is then input to the digital multiplier 5 and stored in the shift register 7.
+1) is supplied to the subtracter 8 and adder 10 as the delayed signal S _t . In other words, the aforementioned delayed signal S _t -1 is an interpolation level adjustment signal obtained by calculation at time t-1.

By the way, as a means for interpolating the level adjustment signal, it is conceivable to pass the level adjustment signal through a digital filter whose impulse response converges in a non-oscillatory manner. FIG. 4 is a signal flow diagram of a general first-order IIR type digital filter that can be considered in its implementation, and its transfer function H(z) is shown as follows.

H(z)=A/1−BZ ⁻¹ ...(1) However, Z=ε ^j 〓〓 ^t , ω: Input frequency Δt: Delay time due to shift register, j=√
-1 In order for the interpolation level adjustment signal that is the output of the digital filter to converge toward the input signal D, the DC response must be 1. That is, when ω=0, since Z=1, H(1)=A/1−B=1, and therefore B=1−A is required. However, in order to realize an actual digital filter using this coefficient, not only two coefficient units A and (1-A) are required, but also two coefficient units A and (1-A) are required.
Since the ratio of 1 to 1 has a large influence on the characteristics of the digital filter, when changing the characteristics using the coefficient A as a variable, the handling of the coefficient (1-A) becomes a problem.

Therefore, in principle, this device adopts the idea of this digital filter, has a simple structure, and performs signal processing as shown in FIG. 5. The transfer function for the signal flow configured in this way is H(z)=A/1-(1-A)Z ^-1 ...(2), so in equation (1), B=1-A. However, it can be realized by using only one coefficient multiplier, and has the advantage of being extremely easy to implement in actual hardware. That is, in this device, A = 1/2 ⁿ in the above equation (1), but if the signal transmission configuration shown in Fig. 4 is used, it is necessary to set B = 1-1/2 ⁿ . . Here, in order to obtain A=1/2 ⁿ , if we round down the digital value from the LSB side, we will obtain coefficients that become 1/2, 1/4, ... 1/2 ⁿ , By using this, the device can be easily realized. Naturally, in order to realize B=1-1/2 ⁿ , a digital multiplier as a full-fledged coefficient multiplier is required, which has the disadvantage of not only being uneconomical but also complicating the structure. Generally, when implementing a digital filter, there is a problem in that calculation errors occur due to the finite word length. In particular, when there are multiple coefficients, the ratio of the respective coefficient values is related to the stability condition of the digital filter, so B
=1-1/2 ⁿ is required to have sufficient accuracy, and therefore it is necessary to make the coefficient word length and operation word length sufficiently long. However, as mentioned above, if the unique configuration of this device is adopted, only one coefficient multiplier can be used, and even if A = 1/2 ⁿ , it is not related to the stability condition, so it is very difficult to design. It is convenient for
As mentioned above, A=1/2 ⁿ can also be easily obtained. In particular, with this device, the level adjustment signal, which is the input signal of this digital filter, can be processed as a parallel signal, so there is no need to use any circuit elements for the truncation operation from the LSB side, which reduces device manufacturing and cost. is also very advantageous.

Figure 6 shows the above device with n set to 0, 1, and 2.
This shows the effect of interpolation when As shown in this figure, n= which does not play the role of interpolation
It can be seen that as n is increased compared to the 0 state, large step changes in the output signal become smaller step changes. At this time, n may be set to a value such that click noise cannot be detected. However, setting the value of n larger than necessary not only delays the convergence of the interpolation level adjustment signal value, but also
This is not preferable because it also increases the error in the convergence value due to the calculation error. Note that the above calculation error will be explained later.

On the other hand, it is also necessary to determine Δt in the figure, that is, the calculation period of the interpolation digital filter of this device. This calculation cycle is determined by the clock cycle given to the shift register 9, but it is also related to the setting of n mentioned above.If n is increased, the number of calculations is sufficient to allow the interpolation level adjustment signal value to converge. It is necessary to set the value to . Note that it is not preferable to make the period shorter than the sampling period of the digital input signal because there is a risk that the meaning of interpolation will be lost.

As described above, by setting appropriate n and Δt, smooth level adjustment can be performed without detecting click noise.

Now, let us explain the calculation error mentioned earlier. Since the coefficient unit 9 is a simple truncation operation, the result is not exactly 1/2 ⁿ , but includes a certain amount of calculation error. However, since the purpose of this interpolation is to turn a large step change into a small step change, it is not necessary that the size of the small step change exactly according to a certain characteristic. That is, no audible click noise is detected in the output signal, and if the level difference is less than the recognition threshold, it is possible to completely ignore calculation errors in level adjustment changes. However, as shown in FIG. 7, the final convergence value of the interpolation level adjustment signal may cause a level error ε in the output signal value due to the above-mentioned calculation error. This level error ε is n
tends to increase as the value increases, and if the word length of the level adjustment signal D obtained from the memory 4 is sufficiently large, it becomes very small compared to the level difference recognition threshold. Although the level error ε does not cause a discernible level difference, it cannot be ignored if highly accurate gain adjustment is required.

Therefore, in the present invention, a zero detector 11 and a gate 12 are incorporated between the subtracter 8 and the adder 10 in the interpolation calculation device 6, as shown in FIG. This will solve the problem. This is because the zero detector 11 detects when the interpolation level adjustment signal converges, that is, when the output of the coefficient multiplier 9 becomes zero, and the gate 12 detects the coefficient of the coefficient multiplier 9 while it is at zero. 1”
, and forcefully eliminates the level error ε. As a result, level control characteristics as shown in FIG. 9 can be obtained. Furthermore, the zero detector 11 is not limited to zero, but can be set to an arbitrary value to speed up the convergence appropriately. In other words, if convergence is delayed when n is increased as mentioned earlier, the effect can be sufficiently improved by aborting the calculation midway and forcing convergence as shown in Figure 10. Demonstrated. This means that even if the interpolation calculation is continuing, if the difference between the interpolation level adjustment signal and the level adjustment signal from the memory 4 is at a value that makes it impossible to detect click noise, it will be converged all at once. In this way, Δt can be set longer or n can be made larger, so that the initial change in S _t in response to a step change in the level adjustment signal D can be made smoother. At the same time, device design can be further simplified.

Thus, according to the amplitude control device according to the present invention,
Since a step level change is converted into a smaller step level change, the unpleasant click noise that appears in the output signal can be lowered to below the detection limit, making smooth level adjustment possible. Moreover, as mentioned above, without using a high-speed, high-bit A/D converter or memory,
Even in a digital filter configured as an interpolation circuit, it can be implemented without requiring an expensive digital multiplier, so the configuration can be greatly simplified and implementation is easy.

FIG. 11 shows an example of a device according to the present invention. In the device of the previous embodiment, the level adjustment signal D obtained from the memory 4 is treated as a parallel signal,
This was subjected to parallel arithmetic processing, but as shown in FIG. The arithmetic unit and shift register 16 may be configured to perform serial arithmetic processing. In this case, the coefficient unit 17 requires a simple shift register for shifting n bits from the LSB, but there is no need to use something with a complicated and expensive configuration like a digital multiplier. It goes without saying that this embodiment has the same number of effects as the previous embodiment. In particular, such serial calculation is very effective because it does not require many calculation circuit elements even when the level adjustment signal D has a large number of bits.

FIG. 12 is a configuration diagram of a signal transmission system showing a modified example of the present invention, which is a configuration that is allowed only when the coefficient multiplier is 1/2, that is, n=1. The interpolation calculation device realized according to the processing flow is configured as shown in FIG. 13, for example. Although a serial calculation processing configuration is used here, it goes without saying that a configuration that performs parallel calculation processing may also be used. In this example, the coefficient is limited to only 1/2, but it has the advantage that the level error ε does not occur in the final convergence value of the interpolated level signal. It has the same effect as case 1.

By using this device having the above-mentioned effects, a digitally controlled muting device as shown in FIG. 14, for example, can be realized. The switch (SW) 19 consists of multiple interlocking switches,
For example, the digital values "111...1" and "000...
...0" has the function of switching
This mutes the input signal. In this case, if you simply connect the switch (SW) 18 directly to the digital multiplier 5,
Although there is a possibility that quite large click noise may be generated by turning the switch (SW) 19 ON/OFF, by adding the interpolation calculation device 6 according to the present invention, it is extremely effective and does not cause discomfort. It is possible to perform a miute action on the especially,
The attenuation speed can be changed depending on the values of n and Δt of the coefficient unit 9 in the interpolation calculation device 6, so by setting n and Δt to be slower, it can also be used as a digitally controlled automatic fade-out device. .

Note that the present invention is not limited to the above embodiments. For example, in each of the above embodiments, the memory 4 is addressed by the resistor 1 and the level adjustment signal D is obtained. However, this level adjustment signal can be changed by a switch (SW) or by following a certain program by a computer. It may be any data that can be obtained. Further, the number of signal bits, control level range, etc. may be determined according to specifications. Furthermore, the interpolation calculation period Δt may not be fixed to a constant period, but may be a continuously variable period such that, for example, Δt decreases with time between ΔTs. Further, in a digitally controlled automatic fade-out device, if Δt is set according to the above-mentioned continuously variable period, extremely natural damping characteristics can be obtained. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an example of a conventional device, FIG. 2 is a level characteristic diagram explaining the operation of the device shown in FIG. 1, and FIG. 3 is a schematic configuration diagram showing the device that is the premise of the present invention. , FIG. 4 is a signal flow diagram equivalent to the same device, FIG. 5 is a signal flow diagram of the same device, FIGS. 6 and 7 are level characteristic diagrams showing the operation of the same embodiment device, and FIG. 8 is the same as this example. 9 and 10 are level characteristic diagrams showing the operation of the device shown in FIG. 8, and FIG. 11 is a schematic configuration diagram showing yet another embodiment. , FIG. 12 and FIG. 13 are signal flow diagrams showing other control forms and their configuration examples, respectively. FIG. 14 is a diagram showing an example in which the device of the present invention is applied to a digitally controlled muting device. 1... Variable resistor, 2... A/D converter, 3...
...Addressing control device, 4...Memory, 5...
Digital multiplier, 6... Interpolation calculation device, 7, 16... Shift register, 8, 14...
Subtractor, 9, 17... Coefficient unit, 10, 15... Adder, 13... P/S converter, 18... S/P converter, 19... Switch.

Claims (1)

[Claims] 1 means for setting a gain control value for the encoded signal; a multiplier for setting the amplitude of the encoded signal by multiplying the encoded signal by a gain value generated based on the gain control value; and delaying the gain value for a certain period of time. delay means, means for obtaining a difference signal between the delayed gain value and the gain control value, means for multiplying the difference signal by a predetermined coefficient, and multiplying the difference signal by the predetermined coefficient when the difference signal reaches a predetermined level or less interpolation calculation control for generating a new gain value by adding the delayed gain value or the gain control value to a signal multiplied by the predetermined coefficient and supplying the new gain value to the multiplier; An amplitude control device comprising: