JPH0452650B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a highly practical method that can effectively determine the change characteristics of a digital control signal that controls processing operations such as amplitude adjustment and delay adjustment of a digital acoustic signal. This invention relates to an interpolation circuit for digital control signals.

[Technical background of the invention]

Digital signal processing technology has been widely introduced into various control devices with the development of A/D converters and the like. On the other hand, so-called PCM recording, in which audio signals are converted to digital signals and recorded and played back, has become popular for the purpose of improving the S/N of approximate signals, etc., and related to this, digital signal control is also being used in the field of audio signal processing. It is considered important. In such digital signal control, for example, when adjusting the level of a digital audio signal, this is generally achieved by multiplying the digital audio signal by a digital control signal value as an attenuation coefficient. For example, by multiplying a digitized information signal to be subjected to level adjustment by a digital value of several bits as a gain value, a level-controlled digitized information signal can be obtained.

By the way, the dynamic range uses a fader (gain setter) to convert a 96dB audio signal to approximately
In case of variable setting from 0 to -100 dB in 0.25 dB steps, 385 fader steps are required, and 9 bits of control information are required to represent this as a digital value. The above 0.25dB level difference is -80dB perceptual level to the human ear.
Since the volume corresponds to that of , it is almost impossible to distinguish. Therefore, it can be said that substantially continuous variable settings can be made despite the stepwise gain control described above.

On the other hand, when digitally encoding the audio signal with high accuracy and high fidelity, it is generally converted into a 12 to 16 bit signal. In order to control this signal stably and precisely, a stable and accurate level control signal (digital signal) is required. Therefore, for example, an amplitude control device configured as shown in FIG. 1 is used.

In FIG. 1, reference numeral 1 denotes a variable resistor as a fader, to both ends of which a voltage V is applied from a stabilized DC power source (not shown). This resistor 1 has a so-called B-curve damping characteristic, and a voltage value proportional to the sliding position moved linearly or the rotational angular position moved rotationally is extracted from its sliding contact. It will be done. This voltage value (analog signal) is input to an addressing control device 3 whose main component is an A/D converter 2. This addressing control device 3 converts and outputs, for example, a 9-bit digital signal corresponding to the voltage value and provides it as an addressing signal for the memory 4. This memory 4 is for example
It consists of a ROM (read-on memory) and constitutes a conversion table between the adjustment position of the fader and the corresponding signal level, and control information of predetermined change characteristics is sequentially written in advance at each address. It is. For example, address 0 has an information value of -0 dB (=1.0000), address 1 has an information value of -0.25 dB (=0.97163), address 2 has an information value of -0.50 dB (=0.94406), and address 100 has an information value of -25 dB. (=0.05634), ~, information of -75 dB (=0.00018) at address 300 and -∞dB (=0.00000) at address 385 are written as digital information, respectively. Each of these digital information values is addressed by a digital signal, that is, an addressing signal output from the addressing control device 3 mentioned above, and is selectively read out. And digital multiplier 5
is input as level adjustment information and multiplied by the PCM encoded audio signal. In this way, the audio signal is indirectly level-adjusted (amplitude adjusted) by the level setting by the variable resistor 1 and output.

[Problems with background technical description]

By the way, in this device configured as described above, when adjusting the gain of a 16-bit digital audio signal with high precision using level adjustment information (control signal) expressed in 16 bits, the addressing information of the memory 4 is used as address designation information. As mentioned above, considering the static discrimination threshold of the auditory sense, digital information of about 9 bits is enough to achieve the purpose, but from the perspective of dynamic auditory specialization, it is extremely insufficient as will be explained later. Cases may occur. Furthermore, if the potential change of the slider of the resistor 1 is faster than the sampling period (A/DB converter 2) of the level adjustment information, the change of the information may occur in multiple steps in one sampling period. This can lead to serious problems. For example, as shown in FIG. 2, which shows the level response of the output signal to a change in the resistor 1, when the amplitude of an input signal kept at a constant level is varied, a sharp level change of 0.25 dB or more occurs. However, ΔT is the voltage set by resistor 1 addressed by controller 3,
and the conversion time required for the memory 4 to convert into a digital signal as level adjustment information, that is, the period of the level adjustment signal. However, if the resistor 1 is varied to give a change in the output signal level as shown at A in the figure, the output signal will appear as a step-like change as shown at B in the figure. Since the step unit ΔG at this time is 0.25 dB as shown above, the level adjustment information shows a level difference of 0.25 dB between ΔT as shown in the section T ₁ to _{T 7} . As mentioned above, regarding this level change, statically, no difference in level is recognized from an auditory sense. However, dynamically, it has a feeling that can be described as "buzzing" and may be heard as a slight noise.
In addition, when resistor 1 is suddenly operated as shown in the period T ₇ to _{T 9} , the level adjustment information changes in steps as described above, which generally produces a click sound, which is difficult for the human ear to hear. Sometimes it doesn't feel like a change. That is, when the change in special A is faster than ΔT, the step of change in output B becomes larger. For example, in Figure 2
In the T ₇ to _{T 8} section, there is a step change with a level difference of 2.5 dB, which is perceived by the human ear as a sudden level change, and since it is accompanied by a large click nozzle, it causes discomfort to the auditory sense, so this is not desirable. do not have. Therefore, in order to realize a digitally controlled level adjuster that can obtain extremely natural level changes even when dealing with dynamic problems such as click noise, it is necessary to adjust the step level.
It is necessary to make it even smaller than 0.25 dB, and to make the conversion time ΔT small enough to sufficiently respond to the voltage set by the resistor 1.

Here, the variable speed of this resistor 1 is as follows: If you move the resistor 1 normally by hand and change the output level from 0 to -100 dB, the required speed is at most several hundred ms to several seconds. However, depending on the case, it may take an extremely short time. Therefore, ΔT should normally be on the order of milliseconds, but it is required to be several tens of microseconds or on the same order as the sampling period of the audio signal. For this reason, problems and inconveniences have arisen in that a high-speed A/D converter must be used as the A/D converter 2, and a memory with a short recall time must be used as the memory 4.

On the other hand, making the step level smaller than 0.25 dB means increasing the number of bits of the A/D converter 2. When combined with the ΔT problem mentioned above, this requires the use of an A/D converter with higher speed and higher bits than necessary, leading to an increase in the price of the entire device.
Moreover, when using a multiplexer or the like in the same device to perform time-resolved processing such as arbitrarily adjusting the levels of input signals of multiple channels, an even higher-speed A/D converter is required, making it difficult to realize this. It was extremely difficult.

[Purpose of the invention]

The present invention was made in consideration of these circumstances, and its purpose is to provide a high-speed, high-bit, or high-bit A/D converter, for example, to a level control device, etc. An object of the present invention is to provide a highly practical digital control signal interpolation circuit that reduces click noise that causes discomfort and enables aurally smooth adjustment in an acoustic signal processing device.

[Summary of the invention]

The digital control signal interpolation circuit according to the present invention counts clock signals having a cycle shorter than the sampling period of the primary control signal for processing and calculating digital audio signals, and uses the counted value for the above-mentioned processing and calculations. A comparator that compares the primary control signal and the secondary control signal controls the counter output as a signal to up-count or down-count according to the magnitude relationship between the two signals, and when both signals match, the above-mentioned The counting operation of the counter is controlled to stop.

〔Effect of the invention〕

Therefore, according to the present invention, even if the primary control signal changes rapidly, the secondary control signal generated following it changes gradually, so that the digital sound that is processed and calculated using this change is gradual. It becomes possible to control the signal smoothly. Therefore, it is possible to prevent the occurrence of click nozzles, which has been a problem in the past, and to eliminate discomfort in dynamic auditory sensation. Moreover, since the above-mentioned secondary control signal can be obtained through simple control, it has extremely high practical advantages.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a schematic diagram of an amplitude control device for a digital audio signal, which is constructed by incorporating a digital control signal interpolation circuit according to the present invention. This device is characterized in that an interpolation circuit 6 is added to the device shown in FIG.

Therefore, the interpolation circuit 6 according to the embodiment has an up/down counter 11 as shown in FIG.
and a comparator 12. Now, A/D converter 2 outputs according to the setting value of variable resistor 1,
A signal for controlling the processing operation of the digital acoustic signal, specifically a signal for controlling the access address of the memory 4 is used as a primary control signal, and the address/access of the memory 4 is obtained by interpolating this primary control signal. The signal used for this is the secondary control signal. This interpolation circuit 6 is, for example, B in FIG.
The 9-bit primary control signal given as shown in FIG. It is used to obtain control signals.

That is, the counter 11 configuring the interpolation circuit 6 is
A clock signal with a period Δt is input to the clock terminal CK, and the clock signal is counted according to a control command given to the control terminal. The coefficient operation of this clock signal is controlled by up-counting, down-counting, or stop control. The count value obtained by counting the clock signal by the counter 6 is outputted as a 16-bit secondary control signal and given to the memory 4. On the other hand, this secondary control signal is applied as input Y to the comparator 12. This comparator 12
is the primary control signal of the secondary control signal.
The MSB bits are input to the input X in correspondence with each other, and a match comparison is performed. In addition, LSB side 7 of input Y
The input X corresponding to a bit is given as data "0", for example.

According to the interpolation circuit 6 thus configured, the comparator 12 mutually compares the inputs X and Y, and when the value of the input Y is small, the counter 11
Control the up count. As a result, the value of the secondary control signal output by the counter 11 is changed to the period Δt
The value gradually increases and approaches the value of the primary control signal. Further, when the value of input Y is large, the comparator 12 controls the counter 11 to count down. As a result, the value of the secondary control signal gradually decreases with the period Δt, and approaches the value of the primary control signal. Finally, the values of the temporary control signal and the secondary control signal become equal to each other, and the comparator 12 detects this and periodically controls the counting operation of the counter 11.

In this way, the interpolation circuit 6 interpolates sudden changes in the primary control signal and obtains a secondary control signal that exhibits smooth changes. The above static and dynamic characteristics can be significantly improved. Moreover, in order to solve problems in processing and controlling digital acoustic signals, no measures have been taken, such as reducing the sampling period of the A/D converter 2 or increasing the number of bits that change it, as previously thought. Since this is not necessary, it is possible to simplify the device configuration and reduce its cost. For practical purposes, such as making it possible to smoothly perform arithmetic processing of digital acoustic signals without causing any auditory inconvenience,
It has great effects.

FIG. 5 is a block diagram showing another embodiment of the interpolation circuit 6. In FIG. The interpolation circuit 6 shown here has the same number of bits for the primary control signal and the secondary control signal, and is designed to smooth only sudden changes in the primary control signal. . That is, the quantization step of the secondary control signal is set equal to the quantization step ΔT of the primary control signal,
When the primary control signal changes rapidly over several steps, the secondary control signal is changed by one quantization step to follow this.

Even if the interpolation circuit 6 is configured in this manner, it is possible to effectively prevent the occurrence of click nozzles and the like due to severe level changes that cause auditory problems when processing digital audio signals. Therefore,
It is possible to achieve substantially the same effect as the interpolation circuit 6 having the configuration shown in the previous embodiment.

Furthermore, when the interpolation circuit 6 is configured in this way, the address space required by the memory 4 is small, so the configuration of the device is simple and economical. Therefore, depending on the required use as a digital audio signal control device, the interpolation circuit 6 having the configuration shown in FIG. 5 may be more advantageous.

By the way, the interpolation circuit 6 according to the present invention has great effects when incorporated not only in the above-mentioned acoustic signal amplitude control device but also in a delay control device. FIG. 6 is a schematic diagram of a delay device for delay-controlling digital audio signals. This device delays the audio signal by writing a digital audio signal into the memory 7 by specifying a write address, and by reading out the write data from the memory 7 by specifying a read address. The delay time is given by subtracting predetermined time data from the write address data via the adder 8 and using this as read address data.

However, in the device configured in this way, the data sequentially written into the memory 7 with a designated write address is read out at the read address at a timing delayed by the amount of data subtracted by the adder 8. Therefore, for example, the acoustic signal as shown in FIG. 7a will be read out as shown in FIG. 7b after time _t0 .

Now, if the control signal is changed as shown in FIG. 7c so as to reduce the delay time, the acoustic signal read out from the memory 7 is
It shows a sudden change as shown in . If the delay time is increased sequentially as shown in FIG. 7e, the acoustic signal read out from the memory 7 becomes as shown in FIG. 7f. This is because the quantization step of the control signal is coarse.
This is because a stepwise change occurs in the delay control time, resulting in partial loss or partial overlap of signals.

In this regard, an interpolation circuit 6 having a configuration as shown in FIG. 4 is incorporated to perform interpolation processing on the delay time control signal.
If the change steps are made fine, it becomes possible to finely change the difference between the write address and the read address for the memory 7, and the sound read out from the memory 7 can be changed in response to the control signals shown in FIG. 7c and d. The signals can be made as shown in g and h of the figure, respectively. Therefore, since the acoustic signal only changes in a compressed or expanded state by varying the amount of delay, the audible smoothness is not lost and there is no risk of click nozzle or the like occurring. Moreover, even in this case, the device configuration can be simplified and economical efficiency can be sufficiently ensured. In addition, a great practical effect can be achieved in that a delay device with little signal quality deterioration can be easily realized.

As described above, according to the present invention, the interpolation circuit constituted by the counter 11 and the comparator 12 can extremely effectively interpolate the control signal for controlling the acoustic signal. And, without increasing the resolution of the control signal itself,
It exhibits tremendous effects, such as making it possible to process acoustic signals without causing dynamic deterioration.

Note that the present invention is not limited to the above embodiments. For example, the number of bits of the primary control signal and the number of bits of the secondary control signal may be determined according to the control specifications thereof. Furthermore, the means for generating the primary control signal is not limited at all; for example, it may be applied by switching a digital switch or by reading it from a magnetic recording device. Furthermore, the processing capability of digital audio signals is not limited at all. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an amplitude adjustment device for digital acoustic signals, and FIG. 2 is a diagram showing changes in control signals.
FIG. 3 is a schematic block diagram of an amplitude adjustment device incorporating an interpolation circuit according to the present invention, FIGS. 4 and 5 are block diagrams of interpolation circuits showing different embodiments of the present invention, and FIG. FIGS. 7a to 7h, which are block diagrams of a delay device incorporating a circuit, are diagrams for explaining delay processing of an acoustic signal. 1... Variable resistor, 2... A/D converter, 3...
...Addressing control device, 4...Memory, 5...
Digital multiplier, 6... interpolation circuit,
7...Memory, 8...Adder, 11...Counter, 12...Comparator.

Claims (1)

[Scope of Claims] 1. A clock signal having a cycle shorter than the sampling period of the primary control signal that controls the processing operation of the digital acoustic signal is input, the counted value is changed, and this counted value is used for the processing of the digital acoustic signal. A counter that outputs a secondary control signal used for calculation, and a comparator that compares the primary control signal and the secondary control signal and controls the counting operation of the counter until the values become equal. A digital control signal interpolation circuit characterized by: 2. The comparator causes the counter to perform a down-count operation when the secondary control signal is larger than the primary control signal, and causes the counter to perform an up-count operation when the secondary control signal is small, so that the primary control signal and the secondary control signal are 2. The digital control signal interpolation circuit according to claim 1, wherein the digital control signal interpolation circuit controls the counting operation of the counter to be stopped when the values are equal to each other. 3. The digital control signal as claimed in claim 1, wherein the secondary control signal has a number of bits equal to or greater than the number of bits of the primary control signal, with bits corresponding to the MSB. interpolation circuit.