JPS6258491A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To execute a stable reading action even when a part of the supplying voltage is reduced accompanying the miniaturizing operation by providing a variable capacity element in which one side electrode is connected to the second energizing electrode of the transistor and other side electrode is connected to the read only word line larger than the line where the amplitude of the supplying voltage is supplied to a bit line and a word line. CONSTITUTION:The threshold voltage of MOSFET 11 is 0.5V, a variable capacity element 12 shows the larger capacity value when the electric potential of a memory node 19 side is higher than the electric potential of a read only word line 16 side by 0.5V or above, and the element shows the very small capacity value at the time except for it. At the time of the reading action, the read only word line 16 is changed from 0V to 5V, and at such a time, the electric potential of the memory node 19 of a '1' storing memory cell rises from about 2V to at least about 5V by the linking of the capacity. On the other hand, the electric potential of the memory node 19 of the '0' storing memory cell at such a time is about 0V as it is and the capacity value of the variable capacity element 12 is small as it is.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memory cells.

[Conventional technology]

Memory cells (hereinafter referred to as ITIC cells) consisting of one transistor and one capacitor are widely used as memory cells for highly integrated semiconductor memories because they have few components and can easily miniaturize the memory cell area. .

In ITIC cells, it is common to directly read out the charge stored in a capacitor in each memory cell. For example, to set the storage node of a memory cell to OV during writing, write "°'0", and to set it to VS, write "°'0".
When 1'' is written, the difference in the amount of charge stored in the memory cell capacitor between 0'''11 l 11 is C8·VS, where C8 is the memory cell capacitance. in this case,
The difference between “O” and “1” of the output voltage to the sense amplifier is
If the stray capacitance of the bit line is CB, then C8・V S
/(CB+CS).

In general, higher integration of semiconductor memories is achieved by miniaturizing memory cells and peripheral circuits through microfabrication. In order to miniaturize memory cells and peripheral circuits, it is necessary to miniaturize transistors, but in this case, the power supply voltage has to be It is necessary to reduce the Therefore, when a semiconductor memory using ITIC cells is highly integrated, the output voltage to the sense amplifier becomes smaller by the reduction in the power supply voltage. For the above reasons, in memory using conventional ITIC cells,
It has been difficult to achieve both stable read operation and high integration.

(Objective of the Invention) An object of the present invention is to provide a highly integrated semiconductor memory cell that is capable of stable read operation even if part of the supply voltage is lowered due to miniaturization.

(Structure of the Invention) According to the present invention, there is provided a transistor having a first current-carrying electrode connected to a bit line, a gate electrode connected to a word line, and a second current-carrying electrode; A semiconductor memory cell is obtained, comprising: a variable capacitance element connected to two current-carrying electrodes, the other electrode being connected to a read-only word line in which the amplitude of the voltage supplied to the other electrode is greater than that supplied to the bit line and the word line; It will be done.

(Example) FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, 11 is an N-type channel MOSFET, 1
2 is a variable capacitance element, 13 is a parasitic capacitance connected to the storage node 19, 14 is a word line, 15 is a bit line, and 16 is a read-only word line.
Assuming that the threshold voltage of 3FETI 1 is 0.5■, the variable capacitance element 12 has a large capacitance value, for example, a parasitic capacitance, when the potential of the storage node IIFI is 0.5 V or more higher than the potential of the read-only word line 16 side. It is assumed that the capacitance value is about twice that of 13, and the capacitance value is very small at other times.

FIG. 2 is a diagram showing an example of the operating voltage waveform of the embodiment of FIG. 1. During a write operation, the word line is set to 2.5 V, and the bit line voltage is set to 2.5 V according to the information to be written, for example, for 1" information, and O for "0" information. At this time, M
Since O3FETI 1 is in the on state, the potential of the storage node 19 corresponds to the bit line voltage, which is approximately 2V when writing "°1" information, and approximately 2V when writing "o" information.
It will be about QV.

During a read operation, the bit line is precharged to, for example, 1■ and then connected to a sense amplifier, and the read-only word line voltage is first set to 5■. At this time, the memory cell
When "0" information is stored, the storage node 19 is about 0, so the capacitance of the variable capacitance element 12 is small, and the storage node 19 remains at about OV.When "1°" information is stored in the memory cell If the storage node 19 is approximately 2V, the capacitance of the variable capacitance element 12 is large, and the storage node 19 is approximately 2V.
The word line voltage rises to about 5V. Next, the word line voltage is increased to 2.5
Make it. At this time, if "0°" information is stored in the memory cell, the bit line voltage is CP/(CB + CP)
Only 0VllT! Changes to I. Here, CP is the capacitance value of the parasitic capacitance 13, and CB is the capacitance value of the bit line 15. When “1” information is stored in the memory cell, the bit line voltage is 4・(CP+C5)/(CB+CP+CS)
changes to the positive side. Here, C3 is a capacitance value when the capacitance of the variable capacitance element 12 is large. This “0”, 11
A read operation is performed by sensing and amplifying the difference in bit line voltage changes between bit line voltages with a sense amplifier.

In this way, in this memory cell, the word line 14 is 2.5cm
Since the voltage difference of the storage node 19 on the verge of rising to 1 is approximately 5.5 mm between when it is "0" and when it is "1", the signal voltage output to the bit line 15 is almost the same as when operating with a 5V power supply. Furthermore, since the operating voltage is 2.5V except for the read-only word line 16, the operating voltage of all other than the read-only word line 16 is 2.5V.
SFET is sufficient. Read-only word line 1
A potential difference of 4■ is applied between the source and drain of MO3FETI 1 for a short period of time from when 6 becomes 5■ until the word line 14 rises to 2.5V, but this period is extremely short, so there is no significant impact on this MOSFET II. There is no change over time; as soon as the word line 14 becomes 2.5■, the potential of the storage node 19 becomes 1+4・(CP+CS)/(C
B+CP+C3).

Note that this formula is 1.4 when CB/C3=10, for example.
Give about V.

In unselected memory cells that are neither read nor written, both word lines are kept at 0. Therefore, the memory cells do not affect the bit line voltage, and the information stored in the memory cells is not affected by the bit lines.

During a read/write operation, all MOSFETs connected to a selected word line are turned on, so there is a possibility that information stored in unselected memory cells connected to this word line may be destroyed. In order to avoid this, read and write operations are always performed as one cycle, and the stored information of all memory cells connected to the same word line as the selected memory cell is read out and temporarily stored, and the selected memory cell is read and temporarily stored. After reading and writing information for the memory cells stored in the memory cells into the temporary storage area, the temporarily stored information may be rewritten in these memory cells.

During a read operation, the read-only word line 16 is changed from 0V to 5V, and at this time, the potential of the storage node 19 of the ``1'' storage memory cell increases from about 2'' to at least about 5'' due to capacitive coupling. This is because while the read-only word line changes from QV to 4.5V, the storage node 19 changes from 2V to approximately 5V, but during this time the potential of the storage node 191pJ is always the read word line 16.
This is because the capacitance value of the variable capacitance element 12 always remains large because the capacitance value of the variable capacitance element 12 is higher by 0.5 V or more than the capacitance value of the variable capacitance element 12. On the other hand, at this time
The potential of the storage node 19 of the “0” storage memory cell is approximately OV
Therefore, the capacitance value of the variable capacitance element 12 remains small.

FIG. 3 is a sectional view of the embodiment shown in FIG. 1 actually realized using a semiconductor substrate. In Figure 3, 3
11 is a P-type silicon crystal substrate, 312.313.321
is an N-type region, 314 and 322 are MOSFETs or MO
315 and 323 are conductor films; 340 is a word line; 350 is a bit line; 360 is a gate insulating film forming an S capacitor;
Reference numeral 390 indicates a read-only word line, and 390 indicates an isolation insulating film. 311, 312, 313, and 31C315 constitute an N-type channel MO8FET corresponding to 11 in FIG. 1, and 321, 322, and 323 constitute a variable capacitance element corresponding to 12, respectively.

Let us consider a case where the P-type silicon crystal substrate 311 is maintained at O■, and the threshold voltage of the MOS capacitor composed of 321, 322, and 323 is 0.5■. Electrode 323
When the potential is 0.5 V or more higher than the potential of the electrode 321, an inversion layer is formed on the surface of the MO3, so the capacitance between the two electrodes becomes a large value determined by the area and thickness of the gate insulating film 322. On the other hand, when the potential of the electrode 323 is not higher than the potential of the electrode 321 by 0.5 V or more, no inversion layer is formed, and the capacitance between the two electrodes becomes a very small value created in the area where they overlap. Therefore, 321°322.32
The MOS capacitor composed of 3 satisfies the characteristics of the variable capacitance element described above.

For convenience of explanation, the circuit configurations, operating voltages, and structural examples shown in FIGS. 1, 2, and 3 have been used above, but the present invention is not limited thereto. The type, conductivity type, threshold voltage, and power supply voltage of the transistor may be any other suitable value or value.

(Effects of the Invention) As explained above, the semiconductor memory cell of the present invention can be configured with micro MOSFETs designed for low voltage operation without any problem, and can reduce the drop in read signal voltage. There is an effect.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an operating voltage waveform diagram of the embodiment of Fig. 1, and Fig. 3 is a cross section of the embodiment of Fig. 1 realized using a semiconductor. It is a diagram. 11...MOSFET, 12...variable capacitance element, 1
3... Parasitic capacitance, 14... Word line, 15... Bit line, 16... Read-only word line, 311...
・P-type silicon crystal substrate, 312, 313.321...
・N-type region, 314, 322...gate insulator film, 3
15°323...Conductor film, 340...Word line,
350... Bit line, 360... Read-only word line, 390... Insulator film. 1st $ 2 Illustration Jt Tojuyo L

Claims (1)

[Claims] A transistor having a first current-carrying electrode connected to a bit line, a gate electrode connected to a word line, and a second current-carrying electrode, one electrode connected to a second current-carrying electrode of the transistor and the other electrode being supplied with electricity. and a variable capacitance element connected to a read-only word line, the amplitude of which is greater than that supplied to the bit line and the word line.