JPS6256442B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern inspection apparatus for detecting defects in pattern line width of a sample to be inspected.

Generally, electronic circuit boards (printed circuit boards) and integrated circuits (ICs) are provided with conductive patterns, and these are formed by a photo process using a photomask, but the quality of such patterns is determined by electronic Because it has a large effect on the characteristics of the circuit,
Pattern inspection has become an important issue.

Conventionally, patterns on photomasks or formed circuits have been visually inspected using a microscope, etc., but since this requires a lot of manpower, automatic inspection equipment has been developed, and currently the most A suitable device is one that reads out the pattern shape using optical scanning or an ITV camera, converts it into a binary signal, reads it into a storage circuit, and detects the signal. However, the pattern shape of the sample to be inspected varies in size, and the direction of the line pattern is not constant. For example, a memory circuit is required to classify and store patterns according to pattern direction with different angles such as 0°, 45°, and 90° (Japanese Patent Application No. 1983-
24233 pattern inspection method, etc.), and four types of memory circuits (one for storing the original pattern and 0°, 45°, and 90° patterns) must be provided, which has the disadvantage of increasing the size of the memory circuit.

The present invention is an automatic detection device aimed at eliminating such drawbacks, and its features include a reading device that optically reads the patterned surface of the sample to be inspected and generates a video signal, and a binary system that generates the video signal. It consists of a binary circuit that converts the signal into a signal, a storage circuit that stores the binary signal information, and a detection circuit that reads the contents of the storage circuit and detects whether the pattern is good or bad. It has a gate circuit consisting of a bit cell, and the sensor has two partial sensors for reading the pattern dimension along the pattern line width measurement direction and one for reading the pattern dimension along the direction intersecting the direction to be measured. When the length measurement sensor scans the stored contents, the upper limit of the pattern to be inspected is determined based on the partial readout dimension information in one direction.
The present invention further includes a selection circuit that outputs lower limit allowable dimension information, and a comparison circuit that compares the sum of dimension information of the partial readout dimension information output in the cross direction and the above-mentioned allowable dimension information. This will be explained in more detail below.

FIG. 1 shows the configuration of a pattern inspection apparatus according to the present invention, in which the pattern surface of a sample to be inspected 1 is scanned by a television camera 2, the pattern state is read out, and a predetermined threshold value is applied to output the video signal. The binarization circuit 3 generates a 0, 1 signal pattern. The 0 and 1 signal patterns are read into the memory circuit 4 and taken out to the detection circuit 5 at an appropriate time to judge whether the pattern line width is good or bad.The present invention is characterized by the detection circuit, and other than that, for example, by the reading device. It is also conceivable to use laser light scanning in addition to a television camera.

The storage circuit is a two-dimensional memory composed of many shift registers, and when an arbitrary pattern of the test sample 1 is scanned from below in the direction A→A' with the television camera 2, as shown in the matrix diagram of FIG. Input is input sequentially from the leftmost bit cell of the first column in the B→B' direction to the shift register arranged in multiple columns.
When the input of the column ends, the bit cells at the left end of the second column are similarly input, and the patterns sequentially read out by the television camera 2 are binarized into 0 and 1 signals and read into the memory circuit.

In this case, the detection circuit according to the present invention has a length measurement sensor 10 as shown in FIGS. Consists of a circuit. Figure 2 shows one scanning position when the length measurement sensor scans the memory circuit, and as is clear from Figure 4, the size is selected to be able to detect the line width of the pattern to be inspected. A detection circuit including the length measurement sensor 10 is shown in FIG. In Figure 3,
The orthogonal length measurement sensors 10 are sensors a,
b, c, and d, each consisting of 10 to 20 bit cells. For example, a 0, 1 signal pattern as shown in Fig. 4 is input, and signal 1 is "pattern present" and signal 0 is "pattern present". "No pattern",
Assume that pattern information is transferred and stored so that the measurement sensor 10 is located at position P shown in FIG. Then, sensor a and sensor b of the length measurement sensor 10 output signal 1 for all bits, but for sensor c and sensor d, the bit near center point X outputs signal 1, and the bit far from center point Z outputs signal 1. Outputs signal O. At this time, the following operation occurs in the detection circuit shown in FIG. That is, the signals derived from sensor a and sensor b enter the selection circuit 11 which generates allowable size information, but when all the bits of these sensors a and b output signal 1, the upper limit bit output from the selection circuit 11 The number and lower limit bit number are predetermined, and the upper limit bit information and lower limit bit information are output. This upper and lower limit bit number information becomes allowable size information. On the other hand, the signals derived from sensor c and sensor d are added by adder 12 to output the number of signals 1, and addition information is input to comparator 13 and comparator 14.
The above upper limit bit information is input at the same time and compared, and if the added information is smaller than the upper limit bit information,
GO information “0” is output from the comparator 13. or,
The comparator 14 inputs and compares the addition information and the above lower limit bit information, and if the addition information of sensor c and sensor d is larger than the lower limit bit information, it passes through the inverter 15 and becomes GO information "0", and the above The GO information from the comparator 13 is simultaneously input to the OR circuit 16, and a good judgment "0" is output. But once upon a time,
When NO information is input from either of the comparators 13 and 14, the OR circuit 16 outputs a defect determination "1". The upper limit bit information and lower limit bit information described herein are the maximum and minimum line width reference values of the pattern line width of the sample to be inspected, and a good judgment indicates that the pattern line width is within the allowable range. in general,
In printed circuit boards and ICs, the conductive pattern width is constant depending on the type of sample to be inspected, and therefore detection is possible using the above-mentioned method.

The method for measuring the line width of a pattern in the direction parallel to the scanning direction has been described above, but the important point is to switch the allowable dimension information based on the pattern information from the sensors a and b. Assuming that the data of the line pattern part tilted at 45 degrees in the scanning direction is transferred and located at the Q position (see Figure 4) in the memory, the length measurement sensor 1
0 sensor a and sensor b and sensor c and sensor d
In both cases, bits close to the center point Z output a signal 1, and bits far from the center point Z output a signal O. At that time, in the detection circuit shown in Fig. 3,
It works as follows. That is, if the number of bits indicating signal 1 among the signals derived from sensor a and sensor b is within a certain range (which is between the above-mentioned upper limit number of bits x √2 and lower limit number of bits x √2). For example, the selection circuit 11 outputs the information of the upper limit number of bits x √2 and the information of the lower limit number of bits x √2. On the other hand, the signals derived from sensor c and sensor d are added by adder 12 and outputted, and the addition information of signal 1 is input to comparator 13 and comparator 14. The upper limit bit information is simultaneously inputted and compared, and if the addition information is smaller than the upper limit bit information, GO information "0" is output from the comparator 13. Further, the comparator 14 inputs and compares the addition information and the lower limit bit information, and if the addition information of sensor c and sensor d is larger than the lower limit bit information, GO information becomes "0" through the inverter 15. ,
The GO information from the comparator 13 is simultaneously input to the OR gate circuit, and a good judgment "0" is outputted, and if either one is NO information, a bad judgment "1" is outputted. In this case, the upper limit and lower limit bit information outputted from the selection circuit 11 are the √2 values of the maximum and minimum pattern line width reference values of the sample to be inspected.

Next, the length measurement sensor 10 is placed at the R position (see Fig. 4) in the pattern direction inclined at 90 degrees perpendicular to the scanning direction.
When the pattern information is transferred so that the position P is located, the sensor a and sensor b in the case of the above-mentioned P position are replaced with the sensor c and sensor d, so the connection between the selection circuit 11 and the adder 12 is is switched with a switch (not shown) and detected in the same way as in the case of the P position. That is, sensor c and sensor d
When all bits output a signal 1, it is detected by operating a switch.

Next, FIG. 5 shows another embodiment of the present invention, in which the length measurement sensor 20 has a sensor e and a sensor f that intersect with the sensor a and the sensor b at an inclination angle of 45 degrees.
A gate circuit is created by combining the sensor g and the sensor h. This improves the accuracy of detecting the line width of a pattern with an inclination of 45°, and although the detection circuit becomes somewhat complicated, it is effective when there are many inclination patterns.

As is clear from the above description, the present invention is based on the provision of the length measurement sensor 10, but it will be explained again that reference value data to the selection circuit that selects and outputs the upper and lower limit bit information is important. This is a matter of course, and the positions where reference bit information is not output, for example, sensor a and sensor b in FIG.
In the position where the signal 1 is small, the selection circuit 11
Since the upper and lower limit bit information is not output from the circuit, the detection circuit does not operate. However, GO and NO information is output only when the detection circuit is activated, and a blue-red lamp display, for example, may be used as an output device. In the above embodiment, a shift register is used as a storage circuit for pattern information, but
It goes without saying that even if the random access memory is replaced with a suitable address circuit, pattern information reading similar to that described above can be carried out.

As described above, the present invention is an automatic pattern line width inspection device that has the effect of reducing the capacity of the memory circuit for temporarily storing patterns, making the device inexpensive and easy to operate. , it can be said that it is worth making general use.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a device according to the present invention, FIG. 2 is a matrix diagram of a memory circuit, and FIG. 3 is a detection circuit diagram.
FIG. 4 is a positional relationship diagram between a pattern and a length measurement sensor for explaining the detection circuit, and FIG. 5 is a detection circuit diagram of another embodiment. In the figure, 1 is the sample to be inspected, 2 is the television camera (reading position), 3 is the binarization circuit, 4 is the storage circuit,
5 is a detection circuit, 10 and 20 are length measurement sensors (tentative name), 11 is an adder, 12 is a selection circuit, 13, 1
4 is a comparator, 15 is an inverter, and 16 is an OR circuit.

Claims (1)

[Claims] 1. A reading device that optically reads the patterned surface of the sample to be inspected and generates a video signal, a binarization circuit that converts the video signal into a binary signal, a storage circuit that stores the binary signal information, and It consists of a detection circuit that reads out the contents of the memory circuit and detects whether the pattern is good or bad.The detection circuit has a gate circuit made up of a plurality of bit cells as a length measurement sensor, and the sensor detects the pattern along the pattern line width measurement direction. two partial sensors for reading out the dimensions of;
Consisting of two partial sensors for reading pattern dimensions along a direction intersecting the direction to be measured, when the stored contents are scanned by the length measurement sensor, the pattern to be inspected is read out using the partial readout dimension information in one direction. A pattern inspection device further comprising: a selection circuit that outputs upper limit and lower limit allowable size information; and a comparison circuit that compares the above-mentioned allowable size information with size information of the sum of the output of partial readout size information in the cross direction. .