JPS6255952A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6255952A
JPS6255952A JP19490385A JP19490385A JPS6255952A JP S6255952 A JPS6255952 A JP S6255952A JP 19490385 A JP19490385 A JP 19490385A JP 19490385 A JP19490385 A JP 19490385A JP S6255952 A JPS6255952 A JP S6255952A
Authority
JP
Japan
Prior art keywords
burr
terminal
semiconductor device
remains
external terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19490385A
Other languages
Japanese (ja)
Inventor
Hiromichi Sawatani
沢谷 博道
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19490385A priority Critical patent/JPS6255952A/en
Publication of JPS6255952A publication Critical patent/JPS6255952A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent a semiconductor device from being improperly mounted by providing a crystalline tissue different from a bulk near a contact when connecting a terminal led out of sealing resin with a foillike terminal. CONSTITUTION:A burr 2 remains by pressing on an outer terminal 3. The terminal 3 is placed under a bearer 1, a punch 4 is elevationally moved upward and downward to collapse the burr 2. As a result, the portion of tissue different from that of a bulk remains on the end of the terminal 3, or the burr 2 is separated from the root to possibly cause a small recess 4 to occur. Even if the burr is chemically etched, some recess sometimes remains. The position of the terminal formed with the burr becomes different from the original crystalline tissue. Thus, the improper mounting ratio due to the burr occurred in the conventional one becomes 0%.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はリードフレー11を使用する半導体装置に係り
、特にその封止樹脂外に導出した外部端子と箔状の導電
パターンの接触状態を改善するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device using a lead flake 11, and particularly to improving the contact state between an external terminal led out of the sealing resin and a foil-like conductive pattern. It is something.

〔発明の技術的背景〕[Technical background of the invention]

従来から個別半導体素子や集積回路素子はいわゆるリー
ドフレームにダイボンディング後素子の電極と端子間を
ワイヤボンディングにより電気的な導通を図り、更に第
3図に示すようにこれらに樹脂(10)封止を行ってこ
の端子をこの封止樹脂外に導出して完成する手法が採ら
れており、この封止樹脂外に導出した端子(11)を所
望の回路に接続してそれぞれの機能を発揮することにな
る。
Conventionally, individual semiconductor elements and integrated circuit elements are die-bonded to a so-called lead frame, and then electrical continuity is achieved between the electrodes and terminals of the element by wire bonding, and then these are sealed with resin (10) as shown in Figure 3. The terminal (11) led out from the sealing resin is connected to the desired circuit to perform its respective function. It turns out.

この端子は直線状に延長したものや、場合によっては第
3図及びそのA部を拡大した第4図に示すように封止樹
脂から導出してから一旦下方に折り曲げ、更に段部を設
け、その先端部分を前述の所望の回路を構成する導電層
に半田等で固着する即ち機器へ実装するのが一般的であ
る。この導電層は通常プリント基板に設けた導電パター
ンを利用する頻度が圧倒的に多かったが、最近の実装技
術ではより高密度でしかも表面実装が求められる傾向に
あり、この観点からポリイミド樹脂にCu導電層を設け
た厚さ35μm程度の箔状パターンが利用されるように
なってきた。しかも、その厚さはより薄い方向に向って
おり、更に多層構造も模索されており、この多層構造で
はこのCu導電層も勢い細くならざるを得ない。
This terminal may be extended in a straight line, or in some cases, as shown in Fig. 3 and Fig. 4, which is an enlarged view of part A, the terminal is led out from the sealing resin, bent downward, and then provided with a step. Generally, the tip portion is fixed by solder or the like to a conductive layer constituting the desired circuit described above, that is, it is mounted on a device. This conductive layer has overwhelmingly often used a conductive pattern provided on a printed circuit board, but recent mounting technology tends to require higher density and surface mounting, and from this point of view, polyimide resin and Cu A foil pattern with a thickness of about 35 μm provided with a conductive layer has come to be used. Moreover, the thickness thereof is becoming thinner, and a multilayer structure is also being explored, and in this multilayer structure, the Cu conductive layer must also become thinner.

このような箔状パターンは必要に応じて小さく折りたた
むことが可能になるので、回路自体を小容積内に収納で
きカメラ等では極めて好都合となり、更にその利用範囲
はますます拡大するものと想定される。
Since such foil-like patterns can be folded into a small size as needed, the circuit itself can be stored in a small volume, making it extremely convenient for cameras, etc., and its range of use is expected to continue to expand. .

ところで、リードフレームの製造は食刻法に代り、プレ
スによる切断が主流であり、材質もFe−Ni合今に加
えてCuもしくはCu合金も使用されているのが現状で
ある。
Incidentally, in the production of lead frames, cutting by press is the mainstream method instead of etching, and currently Cu or Cu alloys are also used in addition to Fe--Ni alloys.

〔背景技術の問題点〕[Problems with background technology]

金属材料をプレス工程によって所望の形状に切断して得
られるリードフレームは、その端部に金属残り通称パリ
(今後このように記載する)が発生することは避けられ
ない。更に第3図に示すようにリードフレームの外部端
子(11)長を調整するために、第5図に示すようにポ
ンチ(12)及び受は台(15)とによって切断するの
で、第4図に示したパリ(13)が発生する。このよう
な外部端子をもつ樹脂封止型半導体装置を機器に実装す
ると、第5図に示すようにこのパリが厚さ35μm程度
と極めて薄い導電パターン(14)を切断する事故が発
生した。このパリは被切断材料の材質、厚さ等相関要因
はあるが、最大200μm程度まで発生する場合も知ら
れており、箔状のパターンを利用する場合その対策が強
く望まれている。
A lead frame obtained by cutting a metal material into a desired shape by a pressing process inevitably has metal residues (hereinafter referred to as "paris") at the ends thereof. Furthermore, in order to adjust the length of the external terminal (11) of the lead frame as shown in FIG. 3, the punch (12) and receiver are cut by the stand (15) as shown in FIG. Paris (13) shown in is generated. When a resin-sealed semiconductor device having such external terminals was mounted on a device, an accident occurred in which the conductive pattern (14), which was extremely thin with a thickness of about 35 μm, was cut by the pads, as shown in FIG. Although this paris depends on factors such as the material and thickness of the material to be cut, it is known that pars can occur up to a maximum of about 200 μm, and countermeasures against this are strongly desired when using foil patterns.

〔発明の目的〕[Purpose of the invention]

本発明は上記難点を除去した新規な半導体装置を提供す
るもので、特に箔状パターンとの良好な接続状態を得る
ものである。
The present invention provides a novel semiconductor device that eliminates the above-mentioned drawbacks, and particularly provides a good connection with a foil pattern.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明にあっては箔状パタ
ーンに接触する外部端子先端部分にバルク(bulk)
の結晶と異なる結晶組織をもつ領域を設け、ここからバ
ルクの結晶組織との間は徐々にその組織が変化して連続
した結晶組織とする手法を採用した。その具体的手段と
してはこのパリが形成されたリード端子を押し潰したり
、この押圧によりパリが根本から剥離することによって
窪みを生じたり、更に食刻法によって溶除する方法であ
る。
In order to achieve the above object, in the present invention, bulk is added to the tip portion of the external terminal that contacts the foil pattern.
A method was adopted in which a region with a crystal structure different from that of the bulk crystal was created, and the structure gradually changed between this region and the bulk crystal structure to form a continuous crystal structure. Specific means for this include crushing the lead terminal on which the burr is formed, causing the burr to peel off from the base to create a depression, and further dissolving the burr by etching.

この結果パリが生じていた部分にはバルクの結晶組織と
異なるものが形成され箔状パターンに損傷を与える頻度
は激減する。
As a result, a crystal structure different from that of the bulk is formed in the part where the flakes have occurred, and the frequency of damage to the foil pattern is drastically reduced.

〔発明の実施例〕[Embodiments of the invention]

第1図ならびに第2図により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS. 1 and 2.

前述のように、半導体素子の組立てに当ってはいわゆる
リードフレームを利用する方式が圧倒的に多くこれから
の実施例は集積回路素子を対象として記述する。
As mentioned above, when assembling semiconductor devices, there are overwhelmingly many methods that utilize so-called lead frames, and the following embodiments will be described with an eye toward integrated circuit devices.

外部端子数が多い集積回路素子はいわゆるDIP型のリ
ードフレームに組立てられるのが通例であり、このリー
ドフレームは周囲が枠体で作られた単位体を複数個連続
して設け、この枠体からは求心的に端子を形成し、その
求心位置には枠体に連続して設けた接続片に係止したベ
ッド部を位置させ、ここに集積回路素子をダイボンディ
ングする。この単位体の数は後述するワイヤボンダ等の
設備特性によっても左右されるが、通常は20個程度を
連続して設けたものが使用できる。
Integrated circuit devices with a large number of external terminals are usually assembled into a so-called DIP type lead frame. A terminal is formed in a centripetal manner, and at the centripetal position is located a bed portion which is engaged with a connecting piece provided continuously on the frame, and an integrated circuit element is die-bonded thereto. Although the number of units depends on the characteristics of the equipment such as a wire bonder, which will be described later, usually about 20 units can be used in series.

このようなリードフレームのベッド部には前述のように
半導体ウェーハから分割された集積回路素子をダイボン
ディング後、この集積回路素子に形成した電極と、この
リードフレーム端子間をワイヤボンディングによって電
気的に接続し、更に封止樹脂によってこの集積回路素子
を被覆して保護し、この封止樹脂外にリードフレームの
端子(今後外部端子と記載する)を導出させて組立工程
を終える。
After die-bonding the integrated circuit elements separated from the semiconductor wafer as described above, the bed portion of such a lead frame is electrically connected between the electrodes formed on the integrated circuit elements and the lead frame terminals by wire bonding. After the connections are made, the integrated circuit element is further covered and protected with a sealing resin, and the terminals of the lead frame (hereinafter referred to as external terminals) are led out of the sealing resin to complete the assembly process.

この封止樹脂外に導出した外部端子には通常メッキ工程
により保護被膜を被着し、更にこの外部゛端子を所定の
形状に成型する。と言うのは、この樹脂封止型集積回路
素子を機器へ実装するに当っては接着剤が塗布された所
定の回路パターンに固着される外部端子を折曲げ成型す
ることによってその作業が容易にできるようにする。こ
の回路パターンとしては通常はプリント基板が適用され
るが、本発明では箔状の導電パターンを使用し、具体的
には厚さ35μmのポリイミド樹脂にCuからなる導電
パターンを形成したもので、容易に折りたたむことがで
き、極めて小容積内に収容可能なものである。
A protective film is usually applied to the external terminal led out of the sealing resin by a plating process, and the external terminal is further molded into a predetermined shape. This is because when mounting this resin-sealed integrated circuit element on equipment, the process is made easier by bending and molding external terminals that are fixed to predetermined circuit patterns coated with adhesive. It can be so. Usually, a printed circuit board is used as this circuit pattern, but in the present invention, a foil-like conductive pattern is used. Specifically, a conductive pattern made of Cu is formed on a polyimide resin with a thickness of 35 μm. It can be folded up and stored in an extremely small volume.

一方、前記リードフレームは現在プレス工程によって所
定の形状が得られており、その端部には多少パリが残存
している。更に、その外部端子は前述のように成型工程
によってその長さ調整及び箔状パターンへの接触を確実
にするため、折曲げ部を形成する。この長さ調整は第5
図に示すように受は台(15)に外部端子(11)をの
せ、ここに切断ポンチ(12)を下降して行っているが
、この結果外部端子(11)先端にはパリ(13)が形
成する。
On the other hand, the lead frame is currently formed into a predetermined shape through a pressing process, and some cracks remain at the ends thereof. Further, as described above, the external terminal is formed with a bent portion in order to adjust its length and ensure contact with the foil pattern by the molding process. This length adjustment is the fifth
As shown in the figure, the receiver is made by placing the external terminal (11) on the stand (15) and lowering the cutting punch (12) there. As a result, the tip of the external terminal (11) has a paris (13) is formed.

このパリ(2)をもつ外部端子(3)は第1図に示すよ
うに受は台(1)の下におき、その先端に形成されたパ
リ(2)をポンチ(14)を上下動して押しつぶすが、
このパリは外部端子(11)の先端にバルクの組成と異
なる組成をもった部分(3)が残るか、又は抑圧により
そのパリ根元部分から剥離して多少の窪み(5)が形成
される場合もある。又このパリを化学的な食刻手段によ
って除去する手段も適用可能であるがこの際も多少窪み
を生じることになる。
As shown in Fig. 1, the external terminal (3) with this prong (2) is placed under the stand (1), and the prong (2) formed at the tip is moved up and down with the punch (14). I squeeze it, but
When this paris remains at the tip of the external terminal (11), a part (3) having a composition different from that of the bulk, or when the paris peels off from the root part due to compression and a slight depression (5) is formed. There is also. It is also possible to remove this paris by chemical etching, but this will also result in some dents.

しかし、これらの手段の結果パリが発生していた外部端
子の位置には元の結晶と異なる組織となる。この機械的
ならびに化学的手段によってパリ(2)を除去した外部
端子部分断面図を第2図(a)(b)に示した。
However, as a result of these measures, a structure different from that of the original crystal is formed at the position of the external terminal where paris has occurred. A partial cross-sectional view of the external terminal after removing the electrode (2) by this mechanical and chemical means is shown in FIGS. 2(a) and 2(b).

〔発明の効果〕〔Effect of the invention〕

表面自動実装が必要な機器に樹脂封圧型半導体装置を取
り着ける場合には特定の治具によって所要数のこの半導
体装置を取り出し、接着剤が被覆されている箔状の導電
パターンに固着するが、この封止樹脂外に導出された外
部端子にはこの場合押圧力が加わるため残存しているパ
リによって薄い導体パターンが切断されることは前述の
通りである。
When attaching resin-sealed semiconductor devices to equipment that requires automatic surface mounting, the required number of semiconductor devices are taken out using a specific jig and fixed to a foil-like conductive pattern coated with adhesive. As described above, since a pressing force is applied to the external terminal led out of the sealing resin, the thin conductor pattern is cut by the remaining pads.

このパリが生ずる外部端子の切断工程では30万回の使
用数で約100μmのパリが発生する。
In the process of cutting the external terminals, which causes this burr, a burr of approximately 100 μm is generated after 300,000 uses.

しかし、本発明に係る半導体装置即ち封止樹脂外に導出
された外部端子には元の結晶と相違する結晶組織が、そ
の先端部分に存在するため従来機器で発生していた実装
不良率5%乃至50%が殆んど無くなり、信頼性の高い
半導体装置ひいては、この半導体装置を使用する機器の
信頼性を向上することができる。
However, the semiconductor device according to the present invention, that is, the external terminal led out of the sealing resin, has a crystal structure different from the original crystal at its tip, so the mounting defect rate that occurs in conventional equipment is 5%. 50% is almost eliminated, making it possible to create a highly reliable semiconductor device and improve the reliability of equipment that uses this semiconductor device.

本発明に係る半導体装置では外部端子にパリが30μm
の高さで発生しても機器への実装不良率は0%であり、
50μmの際でも僅か5%に過ぎず、量産上の効果は極
ねめで大きい。
In the semiconductor device according to the present invention, the external terminal has a paris of 30 μm.
Even if it occurs at a height of
Even at 50 μm, it is only 5%, and the effect on mass production is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本実施の製造課程を示す断面図、第2図(a)
(b)はその結果前られる外部端子の断面図、第3図は
従来の樹脂封止型半導体素子断面図、第4図はその一部
を拡大し箔状導電パターンへの取り付は状態を示す斜視
図、第5図は外部端子の切断工程を示す断面図である。
Figure 1 is a sectional view showing the manufacturing process in this implementation, Figure 2 (a)
(b) is a sectional view of the resulting external terminal, FIG. 3 is a sectional view of a conventional resin-sealed semiconductor element, and FIG. 4 is a partially enlarged view showing the state of attachment to the foil conductive pattern. The perspective view shown in FIG. 5 is a cross-sectional view showing the process of cutting the external terminal.

Claims (1)

【特許請求の範囲】[Claims]  樹脂により封止した半導体素子の電極に導電的に接続
し、この樹脂外に導出した外部端子を箔状の導電パター
ンに接触固着するに当り、この接触部付近にバルクの結
晶と異なる結晶組織を具備することを特徴とする半導体
装置。
When connecting conductively to the electrodes of a semiconductor element sealed with resin and contacting and fixing external terminals led out of the resin to a foil-like conductive pattern, a crystal structure different from that of the bulk crystal is formed near this contact part. A semiconductor device comprising:
JP19490385A 1985-09-05 1985-09-05 Semiconductor device Pending JPS6255952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19490385A JPS6255952A (en) 1985-09-05 1985-09-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19490385A JPS6255952A (en) 1985-09-05 1985-09-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6255952A true JPS6255952A (en) 1987-03-11

Family

ID=16332250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19490385A Pending JPS6255952A (en) 1985-09-05 1985-09-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6255952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9272356B2 (en) 2007-03-29 2016-03-01 Daihen Corporation Feed control method for consumable electrode AC arc welding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9272356B2 (en) 2007-03-29 2016-03-01 Daihen Corporation Feed control method for consumable electrode AC arc welding

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