JPS6255926A - Forming method of electrode of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the removal of an unnecessary metal film and to improve the operability of manufacture by a method wherein the speed of vapor deposition of a metal film is kept high in the former stage and low in the latter stage when the metal film is formed on the region of a semiconductor substrate inside an opening of a photoresist film. CONSTITUTION:A collector region 2 is formed on the back side of an Si substrate 1, and a base region 4 is formed on the front side thereof, while an emitter region 5 is formed inside the region 4. Thereafter an Si oxide film 3 is formed, a photoresist film 7 is stuck thereon, and those portions of the films 3 and 7 corresponding to the regions 4 and 5 respectively are opened to form respective openings 8 and 9. Next, an Al film 10 is formed with vapor deposition on the surface of the film 7 and in the regions 4 and 5 inside the openings 8 and 9. Then, the film 7 is removed, and a base electrode 12 and an emitter electrode 11 are formed. When the film 10 is formed by vapor deposition in the above-stated process, the speed of vapor deposition is expedited in the initial stage of vapor deposition, and thereby it is made possible to impede the nucleation on the substrate 1 and thus to obtain a desired film thickness. The speed of vapor deposition is slowed down in the latter stage of vapor deposition. Thereby the unevenness of the surface of the film 10 is reduced, and thus wire bonding in a process of fabricating a semiconductor element is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming electrodes of semiconductor devices.

BACKGROUND OF THE INVENTION Conventionally, a window is opened in a semiconductor substrate after a predetermined diffusion process using a photoresist as a mask, and electrodes are formed on the semiconductor substrate inside the window by a lift-off technique while leaving the photoresist.

With conventional lift-off technology, when depositing AQ at a constant deposition speed (20 people/second) while leaving the photoresist, it is necessary to: ■ increase the resist film thickness, and ■ add ammonia and water after the deposition of Aρ is completed. The photoresist and unnecessary ρ film were easily removed by boiling the mixed solution at 70° C. and etching a portion of the formed /l film.

Problems to be Solved by the Invention However, in the method (2), it is necessary to make the photoresist thicker than necessary (>5μ or more), resulting in poor pattern accuracy and the need for finer patterns, higher integration, etc., which are required for semiconductor devices in recent years. had the disadvantage of not being available. In addition, in method (2), when a part of the Aρ film is etched, variations in etching occur, making it impossible to obtain a predetermined Aρ film thickness, or the etching solution oxidizes the Aρ surface, causing damage to the semiconductor element. In the assembly process, the AA wire was not properly bonded in the wire bonding process for drawing out to the external lead.

The present invention is intended to solve these problems, and aims to improve lift-off properties and improve manufacturing workability.

Means for Solving the Problem In order to solve this problem, the present invention forms a PN junction of a desired shape on a semiconductor substrate, then attaches a photoresist film to the surface of the semiconductor substrate, and then deposits a photoresist film on the surface of the semiconductor substrate. A hole is formed in a portion corresponding to each conductivity type region forming the PN junction, a metal film is deposited on the photoresist film surface and on the semiconductor substrate inside the hole, and then a metal film is deposited on the photoresist film surface and on the semiconductor substrate inside the hole. When removing the metal film by etching the photoresist film and forming a gold R film on the semiconductor substrate inside the opening, the metal V! Dividing the steaming process into two or more stages,
The black stone velocity of the i% film is increased in the budding stage and decreased in the later stage.

Function: With this configuration, it is possible to improve the workability of forming electrodes on a semiconductor substrate.

Embodiment An embodiment of the present invention will now be described based on the drawings.

FIG. 1 shows an example of a method for forming electrodes of an npn power transistor. First, as shown in FIG.
A collector region 2 is formed by diffusing an N'' layer from the back side of the substrate, a base region 4 is formed by diffusing a P'' layer from the front side, and an N'' layer is diffused into this base region 4 and into the silicon substrate 1. The layers are diffused to form emitter regions 5 and channel stop regions 6.

In this way, the PN required for an npn power transistor is
After forming the junction, a silicon oxide film 3 for protecting the PN junction is formed on the surface of the silicon substrate 1, a photoresist film 7 is attached thereon, and the silicon oxide film 3 is formed on the base region 4 and the emitter region 5, respectively. Then, a part of the photoresist v7 is opened. 8°9 is an opening. Next, as shown in FIG. 3B, a ρ film 10 is deposited on the photoresist film 7 and on the base region 4 and emitter region 5 inside the openings 8 and 9 by vacuum Kuroishi method. Next, as shown in FIG. A collector electrode 13 is formed by attaching a metal film to the back surface. - The negative program of the AΩΩ vapor deposition rate to form the base electrode 12 and the 1 Mitsuta electrode #111 described in F is in two stages as shown in Fig. 2(a), and therefore the 30,000 people The film thickness structure is also a two-layer structure of 28,000 and 2,000 layers, as shown in FIG. 2(b). That is, at the beginning of AQ deposition, by increasing the evaporation rate to 60 people/second,
Nucleation on the substrate is prevented to obtain the desired AQ film thickness. ToΩ
The latter stage of the evaporation process reduces the unevenness of the AU film surface by slowing down the heat deposition rate, making it easier to wire bond Aρ in the semiconductor device assembly process. In the early stage of Aρ vaporization, step coverage of the stepped portion between the silicon oxide film, photoresist and silicon substrate is deteriorated by preventing nucleation on the substrate, and lift-off technology (removal of photoresist and unnecessary AR images with nitric acid d = 1 .52 technology for simultaneous removal) becomes easier.

That is, in FIG. 4, which shows the step coverage section 14 shown in FIG. 1(b) in more detail, in the conventional method shown in FIG. 1(b), the edge of the photoresist WA7 is Because it is covered by 10,
The etching solution of the photoresist film 7 is difficult to penetrate and is difficult to lift off, whereas (a) (not shown in the figure) in the method of the present invention, a part of the edge of the photoresist film 7 becomes a ρ film due to poor step coverage characteristics. Since the photoresist film 7 is exposed without being covered with the photoresist film 10, the etching solution for the photoresist film 7 easily penetrates into the photoresist film 7, making it easy to lift off.

The deposition conditions necessary for the lift-off technique are shown in Figure 3. In other words, it is determined by the initial deposition rate, and Figure 3 shows the ease of lift-off and assembly-width bondability (10 people/second is taken as 100) against the deposition rate when forming an AΩ film thickness of 3 μl. . As can be seen from the figure, increasing the deposition rate improves lift-off properties, but deteriorates assembly wire bonding properties.

Therefore, by increasing the deposition rate at the initial stage of deposition, the lift-off technique is facilitated and a constant thickness can be achieved. Thereafter, in order to improve wire bonding properties in the assembly process, the deposition rate is reduced (10 people/sec) to obtain the desired film thickness of C1, which is a feature of the present invention. In the above-mentioned embodiment, the AΩΩ viewer was explained in two stages, but the same effect can be obtained by dividing the AΩΩ monitor into three or four stages, increasing the deposition rate in the first stage and decreasing the deposition rate in the latter stage.

According to the present invention, when applied to an NPN power transistor as shown in FIG. 1, the photoresist, silicon oxide film and silicon Step coverage between substrates is deteriorated, and lift-off performance is further improved. Also, this defense law and A
Figure 5 shows the reverse resistance ff distribution between the emitter and base of a power transistor formed by etching a part of the IQ to facilitate the 71-off technology, and it is clear from the figure. As described above, according to the method of the present invention, it is possible to easily eliminate unnecessary Ω taxes, improve manufacturing yield, and simplify the manufacturing process.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIGS.
(C) is a manufacturing process diagram of an npn power transistor according to the method of the present invention, FIGS. 2(a) and (b) are a program diagram of the Aρ deposition degree and a cross-sectional view of the deposited layer, and FIG. 3 is a diagram showing the ease of lift-off and A graph showing the relationship between wire bonding properties and steaming speed. Figures 4 (a) and (b) are shape comparison diagrams of the present invention and a conventional example when an Aρ steaming tube is formed at the stepped portion. Figure 5 is a graph showing the relationship between wire bonding properties and steaming speed. FIG. 3 is a comparison diagram of the reverse breakdown voltage distribution between the emitter and base of the present invention and a conventional example. 1... Silicon substrate, 2... Collector region, 3...
- silicon oxide film, 4... base region, 5... emitter region, 6... channel stopper region, 7...
Photoresist film, 8.9... Opening part, 10... Aρ
film, 11... emitter electrode, 12... base electrode,
13... Collector electrode, 14... Step coverage department representative Yoshihiro Morimoto II 1 Figure 2 Ctl-') (b) Figure 3 Figure 4 Figure S

Claims (1)

[Claims] 1. After forming a PN junction in a desired shape on a semiconductor substrate, a photoresist film is attached to the surface of the semiconductor substrate, and each conductivity type region of the photoresist film where the PN junction is formed is A hole is formed in a part of the corresponding portion, and a metal film is deposited on the surface of the photoresist film and on the semiconductor substrate inside the hole,
Thereafter, the metal film on the surface of the photoresist film is removed by etching the photoresist film, and when forming a metal film on the semiconductor substrate inside the opening, the metal film deposition process is divided into two or more stages, and the metal film is removed by etching the photoresist film. A method for forming electrodes for semiconductor devices in which the deposition rate is increased in the first step and decreased in the second step. 2. The method of forming an electrode for a semiconductor device according to claim 1, wherein the metal vapor deposition film is Al, and the Al vapor deposition rate in the previous step is 50 Å/sec or more.