JPS6255686B2 - - Google Patents
Info
- Publication number
- JPS6255686B2 JPS6255686B2 JP55098410A JP9841080A JPS6255686B2 JP S6255686 B2 JPS6255686 B2 JP S6255686B2 JP 55098410 A JP55098410 A JP 55098410A JP 9841080 A JP9841080 A JP 9841080A JP S6255686 B2 JPS6255686 B2 JP S6255686B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- recess
- writing
- protrusions
- numbers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 13
- 230000002093 peripheral effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 43
- 239000004065 semiconductor Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
Description
【発明の詳細な説明】
本発明は、半導体ウエハー面への認識符号記入
方法、より具体的には半導体ウエハーにロツト番
号の如き認識番号を記載する場所を形成する方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for writing an identification code on the surface of a semiconductor wafer, and more specifically to a method for forming a place on a semiconductor wafer for writing an identification number such as a lot number.
半導体装置の製造工程において、ウエハーはロ
ツトで製作され、各ロツトには通常数十から数百
のウエハーが含まれる。これらのウエハーは、ロ
ツト毎に管理と認識のため番号付けられることが
要求される。 In the manufacturing process of semiconductor devices, wafers are manufactured in lots, and each lot typically includes tens to hundreds of wafers. These wafers are required to be numbered by lot for management and identification.
従来の技術においては、ダイヤモンドペン先を
備えたペンまたはレーザーを用いてウエハーに認
識番号を記載した。そのとき、数字、文字、記号
などの記入によつて書かれた数字などのまわりに
突起が生じ、かかる突起はそれ以後の工程の装置
にウエハーを置いたとき、不均衡な位置ぎめの原
因となり例えば露光ずれのような障害を発生させ
た。この種の障害は半導体素子製造工程にとつて
重大な欠点であるから、前記した突起を除去する
ことが要求されている。 In the prior art, identification numbers were written on wafers using a pen with a diamond nib or a laser. At that time, protrusions are formed around the written numbers, letters, symbols, etc., and such protrusions cause uneven positioning when the wafer is placed in equipment for subsequent processes. For example, problems such as exposure deviation occurred. Since this type of obstruction is a serious drawback in the semiconductor device manufacturing process, it is required to eliminate the above-mentioned protrusions.
上記の問題点に加えて、半導体素子製造工程の
最後の直前の工程においてウエハーを所定の厚み
にまで研削する。そうすると、当初に記入した数
字などは消滅し、再度同じ数字などを記入する必
要がある。 In addition to the above-mentioned problems, the wafer is ground to a predetermined thickness in the last step of the semiconductor device manufacturing process. If you do so, the numbers you originally entered will disappear and you will have to enter the same numbers again.
本発明は以上に説明した従来技術における問題
点を解決するもので、半導体素子の基板となるウ
エハーの一部に凹部を形成し、その凹部内に製造
ロツト番号のような数字、文字、記号などを記入
しうるようにする。以下、添付図面を例に本発明
の方法を説明する。 The present invention solves the above-described problems in the prior art, and involves forming a recess in a part of a wafer that serves as a substrate for semiconductor devices, and inserting numbers, letters, and symbols such as manufacturing lot numbers into the recess. be able to fill in the information. Hereinafter, the method of the present invention will be explained using the accompanying drawings as an example.
既に説明したように、半導体装置の製造工程に
おいて、ロツト毎のウエハーにはロツト認識符号
を付けなければならず、それは、ウエハーに数
字、文字、記号などを、ダイヤモンドペン先をも
つたペンまたはレーザーを用いて記入する。(か
かる認識符号の記入に一般にナンバリングと呼称
される行為である。)例えば、ウエハーの裏面が
上記したようにナンバリングされると、記入され
た符号のまわりには、前記の如きペンを用いた場
合でもレーザーを用いた場合でも、突起が形成さ
れる。第1図にはウエハー1が、ウエハー支持プ
レート2の上に支持されたものが断面で示される
が、ウエハーの裏面に対してナンバリングがなさ
れると、符号のまわりに突起3が盛り上がつたよ
うに作られる。ウエハー1の上には露光用マスク
4が置かれ、矢印の方向に光が照射されるが、突
起3があるために、ウエハー1は図に見て右の部
分がより高くなり、露光用マスク4とウエハー1
の平行が保たれず、露光に際して誤照射の原因と
なる。しかも、後の工程において、ウエハーの裏
面の陰影を付した研削部分5は、エツチングまた
は機械的研削によつてウエハーが所定の厚みのも
のとなるよう研削されるので、ナンバリングされ
認識符号は必らず消去される。従つて、操作者
は、その記憶またはメモを頼りに認識符号を再記
入しなければならない。 As already explained, in the semiconductor device manufacturing process, each lot of wafers must be marked with a lot identification code, which means marking the wafers with numbers, letters, symbols, etc. using a pen with a diamond tip or a laser. Fill in using . (The act of writing such a recognition code is generally called numbering.) For example, when the back side of a wafer is numbered as described above, the area around the written code can be marked with a pen like the one described above. But even when using a laser, protrusions are formed. FIG. 1 shows a cross section of a wafer 1 supported on a wafer support plate 2. When numbering is done on the back side of the wafer, protrusions 3 are raised around the numbers. It is made like this. An exposure mask 4 is placed on top of the wafer 1, and light is irradiated in the direction of the arrow, but because of the protrusion 3, the right side of the wafer 1 is higher in the figure, and the exposure mask 4 and wafer 1
parallelism is not maintained, causing erroneous irradiation during exposure. Moreover, in the later process, the shaded ground portion 5 on the back side of the wafer is ground by etching or mechanical grinding so that the wafer has a predetermined thickness, so it is not necessary to number the wafer and provide identification codes. It will be deleted without any error. Therefore, the operator must re-enter the recognition code based on his or her memory or notes.
またウエハーの表面に対するナンバリングが提
案されたが、ウエハーの表面にはパターンが形成
されなければならないから、ナンバリングは場所
による制約を強く受ける。加えて、ウエハーの表
面に記入したとしても、前記した如き突起は必ら
ず形成され、ウエハーの上に露光用マスクが置か
れるのであるから、露光用マスクとウエハー表面
との間の不均衡は発生し、それは露光における誤
照射の原因となる。つまり、ウエハーの裏面に認
識符号を記入した場合と同じ問題がある。 Further, numbering on the surface of the wafer has been proposed, but since a pattern must be formed on the surface of the wafer, numbering is strongly restricted by location. In addition, even if the surface of the wafer is marked, protrusions such as those described above will necessarily be formed, and since the exposure mask is placed on the wafer, the imbalance between the exposure mask and the wafer surface will be reduced. This causes erroneous irradiation during exposure. In other words, there is the same problem as when an identification code is written on the back side of a wafer.
本発明にかかる半導体ウエハーナンバリング場
所形成方法は以上に説明した課題を解決する。第
2図を参照すると、ウエハー11の平面図と断面
図が示される。このウエハー11は、例えば一枚
のウエハー上にMOS型メモリチツプを約数百個
作るためのもので、その厚みは数百μmである。
陰影を付した研削部分15を研削すると、ウエハー
の厚みは完成ウエハーの寸法になる。本発明の方
法によると、ウエハー11の裏面の周辺部分また
は周辺近くにナンバリングのための凹部を形成す
るもので、第2図に示される例においては、ウエ
ハー11の裏面の周辺を、研削部分15よりもより
深く、例えば研削部分15を超えて100μ前後切欠
して凹部16を形成するものである。かかる切欠
による凹部形成は公知の研削装置またはエツチン
グを用いてなすことができる。かかる凹部にナン
バリングをなしても、第1図に示したような認識
符号記入によつて発生する突起の悪影響は発生せ
ず(支持プレート上には研削部分15が直接のるか
ら)、また研削部分15が研削され終つても、凹部
16上の認識符号はなんら影響を受けない。 The semiconductor wafer numbering location forming method according to the present invention solves the problems described above. Referring to FIG. 2, a top view and a cross-sectional view of wafer 11 are shown. This wafer 11 is used to fabricate, for example, about several hundred MOS type memory chips on one wafer, and its thickness is several hundred μm.
When the shaded grinding portion 15 is ground, the thickness of the wafer becomes the dimensions of the finished wafer. According to the method of the present invention, recesses for numbering are formed at or near the periphery of the back surface of the wafer 11. In the example shown in FIG. The recess 16 is formed by cutting deeper, for example, by about 100 μ beyond the ground portion 15. Formation of the recess by such a notch can be performed using a known grinding device or etching. Even if such recesses are numbered, there will be no adverse effect of the protrusions caused by marking the recognition code as shown in FIG. Even after the part 15 has been ground, the recognition mark on the recess 16 is not affected in any way.
第3図に示される例において、凹部16′は周
辺の近くにくぼみの如くに切欠される。凹部1
6′の深さは凹部16の深さと同じく切欠する。 In the example shown in FIG. 3, the recess 16' is cut out like a depression near the periphery. Recess 1
The depth of the notch 6' is the same as the depth of the recess 16.
以上に説明したように、本発明の方法による
と、特別の装置を用いることなく、ウエハー裏面
の周辺部分をまたは周辺近くに、研削またはエツ
チングによつて、ウエハー裏面の研削部分よりも
やや深めに切欠することによつてナンバリング場
所を形成し、それによつて、従来技術に経験され
た露光の際の誤照射の原因を除去するだけでな
く、従来技術における再ナンバリングの手間を省
くものである。なお、上記した例において、ウエ
ハー工程の歩留まりが5割とした場合、従来技術
によると、突起があることによつて10%のチツプ
が悪影響を受ける危険があつたのであるが、本発
明によるとこの危険が回避されるものである。 As explained above, according to the method of the present invention, the periphery of the back surface of the wafer or near the periphery can be etched to a depth slightly deeper than the ground portion of the back surface of the wafer by grinding or etching, without using any special equipment. The numbering locations are formed by notching, thereby not only eliminating the cause of erroneous exposure during exposure experienced in the prior art, but also eliminating the trouble of renumbering in the prior art. In the above example, if the yield rate of the wafer process is 50%, according to the conventional technology, there was a risk that 10% of the chips would be adversely affected by the presence of protrusions, but according to the present invention, this is possible. This danger is to be avoided.
第1図は従来技術に従い認識符号が裏面に記入
された半導体ウエハーが支持プレート上に支持さ
れた状態を示す断面図、第2図と第3図は本発明
の方法に従い裏面に凹部が形成された半導体ウエ
ハーの平面図と断面図をそれぞれ示す図、であ
る。
図において、1,11,11′は半導体ウエハ
ー、2はウエハーの支持プレート、3は認識符号
記入により生ずる突起、4は露光用マスク、5,
15,15′はウエハーの裏面の研削部分、1
6,16′は凹部、をそれぞれ示す。
FIG. 1 is a cross-sectional view showing a semiconductor wafer with an identification code written on its back surface supported on a support plate according to the prior art, and FIGS. 2 and 3 show a semiconductor wafer with a recess formed on its back surface according to the method of the invention FIG. 2 is a diagram showing a plan view and a cross-sectional view of a semiconductor wafer, respectively. In the figure, 1, 11, 11' are semiconductor wafers, 2 is a support plate for the wafer, 3 is a protrusion created by writing a recognition code, 4 is an exposure mask, 5,
15, 15' are the grinding parts on the back side of the wafer, 1
6 and 16' indicate recessed portions, respectively.
Claims (1)
おいて、該ウエハーの素子形成面の裏面の周辺部
分に、後の工程において該裏面が研削除去される
所定の厚さよりも深く凹部を形成し、該凹部に前
記所望の認識符号を記入する工程を含むことを特
徴とするウエハー面への認識符号記入方法。1. In a method of writing a desired recognition code on a wafer, a recess is formed in a peripheral portion of the back surface of the element forming surface of the wafer to a depth deeper than a predetermined thickness at which the back surface is polished away in a later step, and the recess is A method for writing a recognition code on a wafer surface, the method comprising the step of writing the desired recognition code on a wafer surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9841080A JPS5723214A (en) | 1980-07-18 | 1980-07-18 | Writing method for recognition mark on wafer surface |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9841080A JPS5723214A (en) | 1980-07-18 | 1980-07-18 | Writing method for recognition mark on wafer surface |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5723214A JPS5723214A (en) | 1982-02-06 |
JPS6255686B2 true JPS6255686B2 (en) | 1987-11-20 |
Family
ID=14219054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9841080A Granted JPS5723214A (en) | 1980-07-18 | 1980-07-18 | Writing method for recognition mark on wafer surface |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5723214A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58169924A (en) * | 1982-03-30 | 1983-10-06 | Fujitsu Ltd | Test device for ic wafer |
JPS60263841A (en) * | 1984-06-12 | 1985-12-27 | Rigaku Denki Kk | X-ray diffraction instrument for thin film sample |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5253668A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Production of semiconductor device |
JPS5311958B2 (en) * | 1974-02-08 | 1978-04-25 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5311958U (en) * | 1976-07-13 | 1978-01-31 |
-
1980
- 1980-07-18 JP JP9841080A patent/JPS5723214A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5311958B2 (en) * | 1974-02-08 | 1978-04-25 | ||
JPS5253668A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Production of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS5723214A (en) | 1982-02-06 |
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