經濟部中央標準局員工消費合作社印製 1 433lwf.d〇c/J jm niy/〇〇2 八7 --- B7 - ___ _ 五、發明説明（I ) 〜一' 本發明是有關於一種微影（Photolithography )製程 時光罩對準（Mask Aligned )的技術，且特別是有關於— f重適用於化學機械硏磨（Chemical Mechanic Polishing ) 白勺光罩整合結構及對準的方法。 在半導體元件愈趨縮小的情況下，如線寬大小已達 〇·18μπι的丨朵半次微米（Deep Sub-Half Micron )技術時， 以化學機械硏磨（CMP )法作爲平坦化的處理，已愈來愈 '重要。但是相繼而來，所須克服的困難之一，便是在CMP 硏磨後所造成對準標不失效（Alignment Mark Failed )的 問題’因爲在以CMP硏磨半導體元件的同時，也平坦化了 對準標示，如此將造成光罩對準不易，相對的圖案也可能 轉移不正確。 請同時參照第la〜le圖及第2圖，其分別繪示習知 —種利用鏡紋（Reticle ) R29及消除窗（Clear 〇mPrinted by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 1 433lwf.d〇c / J jm niy / 〇〇2 8 7 --- B7-___ _ V. Description of the invention (I) ~ I 'This invention is about a micro The technology of Mask Aligned during the process of photolithography, and in particular, it is related to the f-mask integration structure and alignment method suitable for chemical mechanic polishing. When semiconductor devices are shrinking, such as deep sub-half micron technology with a line width of 0.18 μm, a chemical mechanical honing (CMP) method is used as a planarization process. It has become more and more important. But one after another, one of the difficulties that must be overcome is the problem of Alignment Mark Failed after CMP honing. 'Because CMP honing semiconductor components, they are also flattened. Alignment marks. This will make the photomask difficult to align, and the relative patterns may not be transferred correctly. Please refer to Fig. 1a ~ le and Fig. 2 at the same time, which respectively show the conventional method—a kind of use of reticle R29 and a clear window (Clear 〇m).
Window )的對準標示區形成的方法的製造剖面流程圖， 以及所使用的鏡紋R29光罩的平面示意圖。此爲美商先進 微裝置公司（Advanced Micro Device，AMD )所申請之 本國專利案號第262565號的發明，名稱爲“ A METHOD FOR ELIMINATING WINDOW MASK PROCESS IN THE FABRICATION OF A SEMICONDUCTOR WAFER WHEN CHEMICAL-MECHANICAL POLISH PLANARIZATION IS USED”。是現今用於解決對準標示區在經CMP硏磨後， 因對準標示的消失，不能再以量測波程差的方式來對準， 而造成的對準標示失效的問題。 3 本紙張尺度適用中國國家標準（CNs7a4規格（210X297公釐Ί (請先閲讀背面之注意事項再填寫本頁)Window), a manufacturing cross-sectional flowchart of a method for forming an alignment mark area, and a schematic plan view of a mirror pattern R29 photomask used. This is the invention of National Patent Case No. 262565 filed by Advanced Micro Device (AMD), named "A METHOD FOR ELIMINATING WINDOW MASK PROCESS IN THE FABRICATION OF A SEMICONDUCTOR WAFER WHEN CHEMICAL-MECHANICAL POLISH" PLANARIZATION IS USED ". It is currently used to solve the problem that the alignment mark is ineffective due to the disappearance of the alignment mark after the CMP honing, and the alignment mark can no longer be measured by measuring the wave path difference. 3 This paper size applies to Chinese national standard (CNs7a4 specification (210X297 mmΊ) (Please read the precautions on the back before filling this page)
• —I— in In -i n-ί-r-SJ- - - ΐ— - I 1 4 3 31 w f. d o c / .1 i m m y / Ο Ο 2 A7 B7___ 五、發明説明（> ) (請先閱讀背面之注意事項再填寫本頁) 首先，如第la圖所示，提供一半導體基底10，且該 半導體基底1〇至少包括一對準標示區12。其中，每一個 .對準標示區12係由複數個凹槽，例如爲圖la中的二個凹 槽12a、12b，其深度約爲1200A，以構成對準標示。 其次，請參照第lb圖，在半導體基底10上陸續形成 半導體元件，例如矽基底層、源/汲極區、閘極、場氧化 層等等。由於，如何形成半導體元件不爲本發明的重點， 因此並未顯示於圖中，而僅於對準標示區12繪示所形成的 元件層，統稱爲一半導體元件層14。此半導體元件層14 會隨著對準標示12a、12b的輪廓，形成凹凸起伏的形狀， 因此仍保有對準標示12a ' 12b的特徵，不會造成對準標 示失效的問題產生。 接著，請參照第1 c圖，利甩一鏡紋R29光罩20定義 所塗覆一光阻層15的圖案。鏡紋R29光罩20的平面圖如 圖2所示，包括一鏡紋22以及二呈正方形之不透光圖案 24。利用蝕刻將未被光阻層15保護的半導體元件層14去 除，僅剩下半導體元件層14a。 經濟部中央標準局員工消費合作社印製 之後，請參照第Id圖，在半導體基底10上形成一介 電層16，並以CMP法將介電層16經過平坦化製程的處 理。 然後，請參照第le圖，利用一消除窗光罩（未繪示） 定義圖案，除去部份介電層16，而僅剩介電層16a，以形 成一窗口 17，使對準標示12a、12b露出。 - 最後，請參照第If圖，在上述的元件上形成一導線層 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1 433tvvi.doc/Jimmy/0 0 2 A 7 五、發明説明（彡） 18，如此在窗口 17上形成的導線層18便具有對準標示 12a 、 12b ° 然而，利用上述的方法雖可解決CMP製程後，產生的 對準標示失效問題，但是卻多了一個鏡紋R29的光罩20， 使製造的過程花費時間更長，也更加複雜化。因此，本發 明的主要目的，在提出一種不增加製程負擔的方法，同時 也能解決CMP製程所產生的對準標示失效的問題。 爲達上述的目的，提供一種適用於化學機械硏磨的光 罩整合及對準的方法，包括下列步驟： a. 提供一半導體基底，且半導體基底至少包括一對準 標示區，並在對準標示區上形成一對準標示； b. 提供一光罩，光罩包括一消除窗圖案以及多數個U 型圖案， c. 在半導體基底上形成一元件層； d. 利用光罩的此些U型圖案相結合來定義元件層，以 除去元件層未覆蓋對準標示區的部份； e. 在半導體基底上形成一介電層，並以化學機械硏磨 法平坦化介電層； 經濟部中央標準局員工消費合作社印製 (請先鬩讀背面之注意事項再填寫本頁) f. 利用光罩的消除窗圖案定義介電層，以形成一窗 口，露出保有對準標示的元件層；以及 g. 在半導體基底上形成一導線層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） I 4 3 31 w f. d 〇 c / J i m ni y / 〇 〇 2 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（4) 圖示之簡單說明： 第la〜If圖繪示習知一種利用鏡紋R29及消除窗光 罩’以解決CMP硏磨後產生的對準標示失效的製造剖面流 程圖； 第2圖繪示習知一種鏡紋R29光罩的平面示意圖； 第3圖繪示本發明之較佳實施例中，經整合後的第一 種光罩結構的示意圖；第如〜4e圖繪示本發明之較佳實 施例’一種適用於化學機械硏磨的光罩對準的製造剖面流 程圖； 第5圖繪示本發明之較佳實施例中，經整合後的第二 種光罩結構的示意圖； 第6圖繪示本發明之較佳實施例中，經整合後的第二 種光罩結構的示意圖。 實施例 請參照第3圖，其繪示本發明之較佳實施例中，經整 合後的一光罩結構不意圖。光罩30上包括一微電路圖案 (ExposureField ) 32、二個附加區（ExtraArea ) 34、 一淸除區圖案36以及一個以上的遮蔽區圖案，例如爲二個 .U型圖案38。經由將上述習知之鏡紋R29光罩20的不透 光圖案24,分成兩圖案相同，但互爲倒轉180°的U型圖 案38，並與淸除區圖案36及微電路圖案32整合在一起， 以減少整個製程的光罩數量。其中，微電路圖案32的大小 爲長寬各22mm的正方形面積’附加區34則位於微電路圖 案32的上下兩側，形成相互對稱，且高爲2_7mm的梯形 6 (請先閱讀背面之注意事項再填寫本頁)• —I— in In -i n-ί-r-SJ---ΐ—-I 1 4 3 31 w f. Doc / .1 immy / Ο Ο 2 A7 B7___ 5. Description of the invention (>) (Please (Read the precautions on the back before filling this page.) First, as shown in FIG. 1a, a semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes at least an alignment mark area 12. Among them, each .alignment mark area 12 is composed of a plurality of grooves, such as the two grooves 12a, 12b in FIG. 1a, and the depth is about 1200A to form an alignment mark. Secondly, referring to FIG. 1b, semiconductor elements such as a silicon substrate layer, a source / drain region, a gate electrode, a field oxide layer, and the like are successively formed on the semiconductor substrate 10. Since how to form a semiconductor element is not the focus of the present invention, it is not shown in the figure, but the formed element layer is only shown in the alignment mark area 12, which is collectively referred to as a semiconductor element layer 14. The semiconductor element layer 14 will form an uneven shape with the contours of the alignment marks 12a and 12b, so it still retains the characteristics of the alignment marks 12a'12b, and will not cause the problem of failure of the alignment marks. Next, referring to Fig. 1c, a mirror pattern R29 mask 20 is used to define the pattern of a photoresist layer 15 applied. The plan view of the mirror pattern R29 reticle 20 is shown in FIG. 2 and includes a mirror pattern 22 and two square opaque patterns 24. The semiconductor element layer 14 not protected by the photoresist layer 15 is removed by etching, leaving only the semiconductor element layer 14a. After printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, please refer to FIG. Id to form a dielectric layer 16 on the semiconductor substrate 10, and subject the dielectric layer 16 to a planarization process by the CMP method. Then, referring to the figure, a pattern is defined by using an erasing window mask (not shown), and a portion of the dielectric layer 16 is removed, and only the dielectric layer 16a is left to form a window 17 so that the alignment marks 12a, 12b is exposed. -Finally, please refer to the If figure to form a wire layer on the above components. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 1 433tvvi.doc / Jimmy / 0 0 2 A 7 V. Description of the invention (i) 18, so that the wire layer 18 formed on the window 17 has the alignment marks 12a, 12b ° However, although the above-mentioned method can solve the problem of alignment mark failure after the CMP process, there are many The mask 20 with a mirror pattern R29 makes the manufacturing process longer and more complicated. Therefore, the main purpose of the present invention is to propose a method that does not increase the burden on the process, and at the same time, it can also solve the problem of alignment mark failure caused by the CMP process. In order to achieve the above object, a method for integrating and aligning a photomask suitable for chemical mechanical honing is provided, which includes the following steps: a. A semiconductor substrate is provided, and the semiconductor substrate includes at least an alignment mark area, and is aligned. An alignment mark is formed on the marking area; b. A photomask is provided, the photomask includes an erasing window pattern and a plurality of U-shaped patterns, c. An element layer is formed on the semiconductor substrate; d. These U using the photomask The pattern is combined to define the element layer to remove the part of the element layer that does not cover the alignment mark area; e. Forming a dielectric layer on the semiconductor substrate and planarizing the dielectric layer by chemical mechanical honing; Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards (please read the precautions on the back before filling this page) f. Use the erasing window pattern of the photomask to define the dielectric layer to form a window, exposing the component layer holding the alignment mark; And g. Forming a wiring layer on the semiconductor substrate. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with the accompanying drawings. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) I 4 3 31 w f. D oc / J im ni y / 〇〇2 A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 2. Description of the invention (4) A brief description of the diagram: Figures la ~ If show conventional manufacturing cross-section flowcharts that use mirror pattern R29 and eliminate window masks to resolve alignment mark failures after CMP honing; FIG. 2 is a schematic plan view of a conventional mirror pattern R29 photomask; FIG. 3 is a schematic view of a first integrated photomask structure in a preferred embodiment of the present invention; Shows a preferred embodiment of the present invention 'a manufacturing cross-sectional flowchart of a photomask alignment suitable for chemical mechanical honing; FIG. 5 shows a second photomask after integration in the preferred embodiment of the present invention Schematic diagram of the structure; FIG. 6 is a schematic diagram of a second photomask structure after integration in a preferred embodiment of the present invention. Embodiments Please refer to FIG. 3, which illustrates a photomask structure after integration in a preferred embodiment of the present invention is not intended. The photomask 30 includes a microcircuit pattern (ExposureField) 32, two additional areas (ExtraArea) 34, an erasing area pattern 36, and more than one masking area pattern, such as two .U-shaped patterns 38. The opaque pattern 24 of the conventional mirror pattern R29 reticle 20 is divided into two patterns with the same pattern, but U-shaped patterns inverted 180 ° from each other, and integrated with the erasure area pattern 36 and the microcircuit pattern 32 In order to reduce the number of photomasks in the entire process. Among them, the size of the microcircuit pattern 32 is a square area of 22mm in length and width. The additional area 34 is located on the upper and lower sides of the microcircuit pattern 32, forming a trapezoid 6 that is symmetrical to each other and has a height of 2_7mm (please read the precautions on the back first) (Fill in this page again)
本紙張尺度適用中國國家標牟（CNS ) Λ4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 I 4 3 3 twf.doc/.lim my/002 A 7 B7 五、發明説明（$ ) . 面積。又，淸除區圖案36置於微電路圖案32頂側的附加 區34a內，而放置二U型圖案38於微電路圖案32底側的 附加區34b內，藉由兩U型圖案38的組合，可形成內部大 小爲1.6mm的正方形，外部大小爲3.6mm的正方形，且兩 正方形爲同心的回字形面積。 同理，上述的遮蔽區圖案可作不同的設計。請參照第 5、6圖，其繪示的便是另兩種整合的光罩結構圖。第5 圖中，遮蔽區圖案爲一長方形58a及一正方形58b圖所構 成，而第6圖中，遮蔽區圖案則爲兩L形圖案68所構成。 透過長方形58a與正方形58b的組合，及兩L形圖案68的 組合，也可達到如上述兩U型圖案38所形成的回字形面 積。 接著，請參照第4a〜4e圖，其繪示以本發明所整合 的光罩，應用於上述習知適用於化學機械硏磨的光罩對準 的方法。 首先，如第4a圖所示，提供一半導體基底40，且該 半導體基底40至少包括一對準標示區42。其中，每一個 對準標示區42係由複數個凹槽，例如爲圖4a中的二個凹 槽42a、42b，其深度約爲12〇〇Α，以構成對準標示。 其次，請參照第4b圖，在半導體基底40上陸續形成 半導體元件，例如矽基底層、源/汲極區、閘極、場氧化 層等等。由於，如何形成半導體元件不爲本發明的重點， 因此並未顯示於圖中，而僅於對準標示區42繪示所形成的 元件層，統稱爲一半導體元件層44。此半導體元件層44 7 本紙張尺度國家標準（CNS ) Λ4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁)This paper size applies to China National Standards (CNS) Λ4 specifications (210X297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs I 4 3 3 twf.doc / .lim my / 002 A 7 B7 V. Description of the invention ($ ). Area. In addition, the erasure area pattern 36 is placed in the additional area 34a on the top side of the microcircuit pattern 32, and two U-shaped patterns 38 are placed in the additional area 34b on the bottom side of the microcircuit pattern 32. By combining two U-shaped patterns 38 It can form a square with an inner size of 1.6mm and a square with an outer size of 3.6mm, and the two squares are concentric square shaped areas. In the same way, the above-mentioned masking area patterns can be designed differently. Please refer to Figures 5 and 6, which show the other two integrated photomask structure diagrams. In Fig. 5, the masked area pattern is composed of a rectangle 58a and a square 58b, and in Fig. 6, the masked area pattern is composed of two L-shaped patterns 68. Through the combination of the rectangle 58a and the square 58b, and the combination of the two L-shaped patterns 68, the square-shaped area formed by the above two U-shaped patterns 38 can also be achieved. Next, please refer to Figs. 4a to 4e, which illustrate a photomask integrated with the present invention and applied to the conventional method for aligning a photomask for chemical mechanical honing. First, as shown in FIG. 4a, a semiconductor substrate 40 is provided, and the semiconductor substrate 40 includes at least an alignment mark area 42. Wherein, each of the alignment mark areas 42 is formed by a plurality of grooves, for example, two grooves 42a and 42b in FIG. 4a, and the depth is about 12 00A to form an alignment mark. Secondly, referring to FIG. 4b, semiconductor elements such as a silicon base layer, a source / drain region, a gate electrode, a field oxide layer, and the like are successively formed on the semiconductor substrate 40. Since how to form a semiconductor element is not the focus of the present invention, it is not shown in the figure, and the formed element layer is only shown in the alignment mark area 42, which is collectively referred to as a semiconductor element layer 44. This semiconductor element layer 44 7 National Paper Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
I 4 3 3 t w f. d o c / J i m m y / 0 〇 2 A7 B7 五、發明説明（t) 會隨著對準標示42a、42b的輪廓，形成凹凸起伏的形狀’ 因此仍保有對準標示42a、42b，不會造成對準標示失效 的問題產生。 接著，請參照第4c圖，藉由控制一步進機（未繪示） 的作動，利用光罩3〇中兩U型圖案38相結合，來定義出 如習知製程中鏡紋R29光罩20所形成的圖案，以將未被保 護的部份半導體元件層44去除，僅剩下半導體元件層 44a。之後，再形成一介電層46，並以CMP法將介電層 46經過平坦化製程的處理。 然後，請參照第4d圖，利用一消除窗光罩（未繪示）， 例如利用淸除區圖案36或另換光罩來定義圖案，以形成一 窗口 47，藉由除去部份介電層46，而僅剩介電層46a， 使對準標示42a、42b露出。 最後’請參照第4e圖，在上述的元件上形成一導線層 48 ’如此在窗口 47上形成的導線層48便具有對準標示 42a、42b的特_徵。 經濟部中央標隼为負J1·消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，例如可將R29光 罩之不透光圖案24以別的方式分割，再倂入光罩3〇的周 邊，而淸除區圖案36及位置亦未必需爲圖3所示，甚至可 直接以分割圖案的一部份構成淸除區，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 8 本紙悵尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐〉I 4 3 3 tw f. Doc / J immy / 0 〇2 A7 B7 V. Description of the invention (t) The shape of the unevenness will be formed with the contours of the alignment marks 42a and 42b. Therefore, the alignment marks 42a, 42b, will not cause the problem of alignment mark failure. Next, referring to FIG. 4c, by controlling the operation of a stepper (not shown), the two U-shaped patterns 38 in the photomask 30 are combined to define the mirror pattern R29 photomask 20 in the conventional manufacturing process. The pattern is formed to remove an unprotected portion of the semiconductor element layer 44 and only the semiconductor element layer 44a remains. Thereafter, a dielectric layer 46 is formed, and the dielectric layer 46 is subjected to a planarization process by a CMP method. Then, referring to FIG. 4d, a erasing window mask (not shown) is used, for example, an erasing area pattern 36 or another mask is used to define the pattern to form a window 47 by removing a portion of the dielectric layer. 46, and only the dielectric layer 46a remains, exposing the alignment marks 42a, 42b. Finally, please refer to FIG. 4e. A wire layer 48 is formed on the above-mentioned element. The wire layer 48 thus formed on the window 47 has the characteristics of alignment marks 42a and 42b. Printed by the Central Ministry of Economic Affairs for the negative J1 · Consumer Cooperative (please read the notes on the back before filling out this page) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention ' Without departing from the spirit and scope of the present invention, the artist can make various modifications and retouches. For example, the opaque pattern 24 of the R29 mask can be divided in other ways, and then inserted into the mask 30. Peripheral, and the erasure area pattern 36 and position are not necessarily as shown in FIG. 3, and the erasure area can even be formed by a part of the divided pattern directly. Therefore, the protection scope of the present invention should be defined by the scope of the attached patent Whichever comes first. 8 The size of this paper stack is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297mm>