JPS6255348U - - Google Patents

Info

Publication number
JPS6255348U
JPS6255348U JP14774785U JP14774785U JPS6255348U JP S6255348 U JPS6255348 U JP S6255348U JP 14774785 U JP14774785 U JP 14774785U JP 14774785 U JP14774785 U JP 14774785U JP S6255348 U JPS6255348 U JP S6255348U
Authority
JP
Japan
Prior art keywords
electro
optical device
lsi chip
substrate
metal wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14774785U
Other languages
Japanese (ja)
Other versions
JPH0445244Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985147747U priority Critical patent/JPH0445244Y2/ja
Publication of JPS6255348U publication Critical patent/JPS6255348U/ja
Application granted granted Critical
Publication of JPH0445244Y2 publication Critical patent/JPH0445244Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の電気光学装置の基本構成で、
ａは上面図、ｂは側面断面図である。第２図ａ，
ｂ，ｃは従来技術の説明図である。 １……基板、２……電極端子、３……ＬＳＩチ
ツプ、４……接着剤、５……導電性粒子、６……
金属線、７……弾力性を有する板、８……ワイヤ
ー、９……半田。 Figure 1 shows the basic configuration of the electro-optical device of the present invention.
A is a top view, and b is a side sectional view. Figure 2a,
b and c are explanatory diagrams of the prior art. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Electrode terminal, 3... LSI chip, 4... Adhesive, 5... Conductive particles, 6...
Metal wire, 7... Elastic plate, 8... Wire, 9... Solder.

Claims (1)

【実用新案登録請求の範囲】 (1) 基板上に駆動用大規模集積回路チツプ（以
下ＬＳＩチツプと記す）を実装した電気光学装置
に於いて、ＬＳＩチツプと基板上の電気的接続に
導電性の粒子を用い、かつ、物理的固定に接着剤
を用いることを特徴とする電気光学装置。 (2) バンプに金属線を接続し、金属線の上部に
弾力性を有する板を取り付けたＬＳＩチツプを用
いることを特徴とする実用新案登録請求の範囲第
１項記載の電気光学装置。[Claims for Utility Model Registration] (1) In an electro-optical device in which a driving large-scale integrated circuit chip (hereinafter referred to as an LSI chip) is mounted on a substrate, the electrical connection between the LSI chip and the substrate must be electrically conductive. An electro-optical device characterized in that it uses particles of the same type and uses an adhesive for physical fixation. (2) The electro-optical device according to claim 1, which is a utility model, and uses an LSI chip in which a metal wire is connected to the bump and an elastic plate is attached to the top of the metal wire.
JP1985147747U 1985-09-27 1985-09-27 Expired JPH0445244Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985147747U JPH0445244Y2 (en) 1985-09-27 1985-09-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985147747U JPH0445244Y2 (en) 1985-09-27 1985-09-27

Publications (2)

Publication Number Publication Date
JPS6255348U true JPS6255348U (en) 1987-04-06
JPH0445244Y2 JPH0445244Y2 (en) 1992-10-23

Family

ID=31061393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985147747U Expired JPH0445244Y2 (en) 1985-09-27 1985-09-27

Country Status (1)

Country Link
JP (1) JPH0445244Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153751A (en) * 1994-08-31 1996-06-11 Nec Corp Electronic device assembly, and manufacture thereof
WO1998046811A1 (en) * 1997-04-17 1998-10-22 Sekisui Chemical Co., Ltd. Conductive particles and method and device for manufacturing the same, anisotropic conductive adhesive and conductive connection structure, and electronic circuit components and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120941A (en) * 1974-08-14 1976-02-19 Seikosha Kk DODENSEISETSUCHAKUZAI
JPS5431566A (en) * 1977-08-12 1979-03-08 Nippon Kokuen Kogyo Kk Way of connecting large scale integrated circuit to current carrying circuit portions on insulated substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120941A (en) * 1974-08-14 1976-02-19 Seikosha Kk DODENSEISETSUCHAKUZAI
JPS5431566A (en) * 1977-08-12 1979-03-08 Nippon Kokuen Kogyo Kk Way of connecting large scale integrated circuit to current carrying circuit portions on insulated substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08153751A (en) * 1994-08-31 1996-06-11 Nec Corp Electronic device assembly, and manufacture thereof
WO1998046811A1 (en) * 1997-04-17 1998-10-22 Sekisui Chemical Co., Ltd. Conductive particles and method and device for manufacturing the same, anisotropic conductive adhesive and conductive connection structure, and electronic circuit components and method of manufacturing the same
KR100574215B1 (en) * 1997-04-17 2006-04-27 세키스이가가쿠 고교가부시키가이샤 Conductive particles

Also Published As

Publication number Publication date
JPH0445244Y2 (en) 1992-10-23

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