JPS6254181A - Pattern generating device - Google Patents

Abstract

PURPOSE:To make generation of test waveform patterns easy by making update period of a clock generating circuit to each address counter progressively small. CONSTITUTION:If becomes possible to designate rise time and fall time of pattern data on a memory only by information of time by storing pattern data making access period accessing (n) address of a pattern data memory 12. Consequently, it becomes not necessary to deal with data and timing separately. Furthermore, as update period of a clock generating circuit is made progressively small as 18a, 18b, 18c, pattern data of relatively long period can be stored in the state of small storing capacity of the memory 12 by designating combining pattern data of different period of generation. Accordingly, generation of multifarious waveform patterns of relatively long period is made easy without enlarging memory capacity.

Description

[Detailed Description of the Invention] [Field of Application in Industry 1] The present invention relates to a pattern generator, and in particular, the present invention relates to a pattern generator that generates waveform patterns for each of a plurality of IC test pins, such as a test waveform pattern for an ICM. The present invention relates to a pattern generator.

[Prior Art] There are seven types of IC testing systems that automatically generate a multi-bit test waveform pattern necessary for performing a performance test of an IC according to a test pattern program or the like.

Conventionally, in such a test waveform pattern generator, it is necessary to generate data for each pin of an IC from among pattern data created by a pattern generator and a clock signal created by a timing generator. A predetermined waveform is generated by selecting and synthesizing the waveforms. Then, send this to the drive circuit, convert the output level,
A method is adopted in which the signal is supplied to a predetermined IC pin.

As an example, a specific circuit as shown in FIG. 5 can be cited.

Reference numeral 1 denotes a pattern generator, which is composed of, for example, a predetermined ROM, and which accesses a predetermined address to generate predetermined patterns such as pattern A and pattern B shown in FIG. 6(a) and (b). The data selector 2 selects the seven most recognized pattern data at a predetermined timing and sends them to the waveform formatter 3.

On the other hand, the timing waveforms (1) and (2) of (d) and (e) in FIG. 6 generated by the timing generation 'Ei4
) is selected by the timing selector 5 at a predetermined timing and sent to the waveform formatter 3.

Here, if, for example, pattern A and pattern B are selected, the waveform formatter 3 displays (C) in FIG.
The pattern data shown in FIG. 6 is generated as a composite pattern of AB, and, for example, timing waveforms (1) and (2) are selected respectively, and according to these, the waveform formatter outputs the test waveform pattern as shown in FIG. 6(f). occurs.

The output signal y7 of this waveform formatter 3 is sent to the driver 7 of the next stage drive circuit 6 as a test waveform pattern. Then, via the drive circuit 6, a corresponding waveform pattern of a predetermined voltage is applied to a specific pin of an IC to be tested inserted into a socket on the handler side, for example.

Note that 7a and 7b are base ring voltage regulator modules that supply the driver 7, and they provide a stable voltage VIH (
HIGH level setting voltage value).

VIL (low level set voltage value) is supplied to the driver 7.

[Problems to be Solved] As I' conductor integrated circuits become more sophisticated, the waveform patterns applied during testing tend to become more complex. Therefore, in the case where a predetermined waveform pattern is generated using a pattern generator and a timing generator as described above, the types of waveforms that can be generated are determined by the hardware configuration, and various test waveform patterns are generated. There are drawbacks that cannot be addressed.

In addition, in order to provide flexibility in test waveforms and 1Q logical values for each pin, the corresponding selection circuit is 7-block, and when the number of pins increases, the circuit scale increases and high speed is impaired. However, there is a problem in that the entire device becomes larger.

In order to solve these problems, the applicant set the access period for accessing address n (n is a positive integer) in the memory to be medium, and set the pattern data corresponding to the timing of the generated waveform pattern. A technology in which data is stored in a memory, a predetermined test 71U pattern is generated based on the pattern data obtained by sequentially accessing this memory, and the above-mentioned access is performed each time the address counter is updated in accordance with the clock cycle. has been proposed as prior art and has already been filed.

However, in this type of test pattern generator, it is necessary to prepare and store a wide variety of patterns corresponding to the pins of the IC, so a relatively large capacity memory is required. In particular, when a large number of waveform patterns with relatively long periods are stored, the memory capacity becomes extremely large, which poses a problem in terms of circuit miniaturization and cost.

[One aspect of the invention] The present invention solves the problems of the prior art and prior art, and provides a pattern generator that can generate various and complex test patterns with a simple configuration. For the purpose of koki.

[L stage for solving the problem] This invention does not determine the waveform of a logic signal based on logic data, the type of waveform, and its timing, as in the past, but instead ``I.

The difference point is measured 111 times from the reference point, and the timing is managed using the memory access cycle as t and 1 as the digit time.

Therefore, the means in the pattern generator of the present invention for achieving objective 1-1 is as follows:
The access period for accessing the address (n is an integer of iE) is set to medium, and there are multiple memories each storing pattern data corresponding to the timing of the generated waveform pattern, and each access address is stored in each of these memories. It has multiple address counters and a clock generation circuit that periodically updates each address value corresponding to these address counters, and generates a predetermined waveform pattern based on pattern data obtained by accessing multiple memories. In this method, a plurality of memories are sequentially accessed in stages, and the update period for each address counter of the clock generation circuit is sequentially decreased in accordance with the order in which the stages come later. .

[Operation] By storing the pattern data with the access period for accessing the address n of the memory as a medium value, it is possible to determine when the test waveform pattern -χchi1., increases and when Xrchido increases. memory 11 with only time information.
It is now possible to specify.

As a result, data and timing do not have to be handled separately. Moreover, since the update period of the clock generation circuit is gradually becoming smaller, by specifying a combination of pattern data with different generation periods, even pattern data with a relatively long period can be stored with a small memory storage capacity of 1u. .

Therefore, it is possible to generate various waveform patterns with relatively long cycles without increasing the memory capacity I14, making it easy to generate test waveform patterns, and simplifying their management and control.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of a pattern generator according to the present invention, FIG. 2(a) is a specific example of a waveform pattern to be generated, and FIG. 2(b) is a diagram showing the case in which FIG. 3 is an explanatory diagram showing the storage contents of the data memory section of the computer.

The pattern generator 10 is an I
This is test waveform pattern data for C inspection.
Pattern data memory 12. It includes a test sequence processor 14, an address counter/access circuit 16, a clock generation circuit 18, and the like.

Note that the same pattern generation device 10, which is composed of a pattern data memory 12, an address counter/access circuit 16, a clock generation circuit 18, a drive circuit 6, etc., with a common test sequence processor 14, corresponds to the pins of the IC to be tested. A plurality of them are provided in parallel. In the following description, the pattern generators 10 that are installed in parallel will not be described because they are the same.

The test sequence processor 14 stores microcommand programs necessary for generating various test waveform patterns in its internal memory, and by executing the microcommand programs, the start address for the pattern data memory 12 corresponding to a certain IC pin is determined. At the same time as generating information, the clock generation circuit 18 is activated.

The pattern data memory 12 is a device under test (IC).
The pattern data necessary for the performance 9 function test of the 1. The first page is accessed step by step in the order of second and third. A first data memory section 12a serves as a second and third memory.

Second data memory section 12b, third data memory section 1
It has three blocks of 2c, and is equipped with an AND circuit 13. The first page was accessed in stages. Second
．． Third data memory section 12at 12b, l2
The outputs from the three blocks of c are this ANI) circuit 1
3, A N +) is taken, and the AN1] condition is met.S7.
At this time, the output of the ANI) circuit 13 is sent to the waveform edge generation circuit 20.

1) As for the stepwise access described in item 11, for example, at the start time, access to the first data memory section 12a is first started. Then, when specific bi-soto data is read out, access to the second data memory section 12b is started, and at this time, access to the first data memory section 12a is stopped.

Next, when specific bit data is read in the access to the second data memory section 12b, access to the second data memory section 12c is started, and access to the second data memory section 12b is stopped.

Next, the third data memory section 12c is accessed, and
When specific bit data is read, this is the first bit data. Second data memory 12a.

The waveform edge generation circuit 2 is applied to the AND condition with the specific bit data (for example, flag bit) read from 12b.
0 to designate the rising, rising, or falling points of the waveform pattern.

At this point, access to the third data memory section 12c is stopped.1. Is it the first data memory? a< 1
The access of 2a is started a second time, similar processing is performed, and next, specific bit data on the rising edge is read out and the point in time when X''f minus is specified.

Now, the address counter/access circuit 16 similarly operates at the first . Second. Third address counter/access section 18
It is composed of three blocks: al l 6 be 16 c, which operate in stages, with the first . Second. Third data memory section 12 al
It corresponds to each of l 2 be 12 c.

Each of these stores the address information of the corresponding data memory section, and each time the given address information is updated, a read control signal is sent to the corresponding first . Second. Third data memory section 12 at
The primary data of the town is read from the specified address by sending it to l 2 be l 2 c.

Here, the first .
Second. Third each address/access circuit section lea, 18
The address values stored in the first . Second. Third data memory section 12 al
This indicates the respective start access address values of l 2 b and 12 c.

In addition, a second address counter/access circuit section 18b
When receiving specific bit data (flag bit) from the first data memory section 12a, it sends a control signal to the clock generation circuit 18. Similarly, the third address counter/access circuit section 16b is connected to the second data memory section 12.
When receiving specific bit data (flag bit) from b,
A control signal is sent to the clock generation circuit 18.

These control signals to the clock generation circuit 18 are for stopping the currently generated clock (1-) and generating a new lock.

The clock generation circuit 18 is activated by the test sequence processor 14, and first generates a first clock signal at the clock generation terminal 'f' 18a to read the address f1°l of the first address counter/access section 16a. Updates one address at a time.

Then, the clock generation circuit 18 receives the control signal Gino from the second address counter/access section 16b, stops the first clock signal, and starts the second clock signal I and i. The signal is generated at the clock terminal 18b. This second clock signal is input to the address counter/access section 18.
In response to this, the address counter/access unit 18b outputs one address at a time at a constant cycle, the address value of which is different from the above! J! I was made to pay 9fr.

Further, a clock generation circuit 18 receives a +lif control signal from a third address counter/access unit lee.
stops the second clock signal and generates a third clock signal at clock terminal j'18c, which likewise causes the third address counter/access? J< 16
The address value of e is updated one address at a time at a constant cycle different from the above.

Here, these first. Second. The period of the third clock is
1st. Second. For example, the first
The period is set to 84 ns, the second period is set to 8 ns, and the third period is set to 1 ns.

And the first. Second. Each of the third address/access circuit units 1 b a, 16 b + l 8 c is connected to the first . Second. Third data memory section 12 al l 2 b + l 2 c
A read control signal is sent to the update address corresponding to the update address. Therefore, data memory sections 12a, 12b+
The generation timing of the pattern data read from the address counter/access circuit 12c is determined by the first -
2nd t 3rd address/access circuit section l 8
a + l 6 b + 18 c are respectively determined by the combined sum of memory access speeds, which are determined by the first . Second. It will be determined by the period of the third clock.

Now, the waveform edge generation circuit 20 is constituted by, for example, a flip-flop circuit, and converts the waveform to a test waveform pattern by lowering or lowering the waveform in response to the data output from the pattern data memory 12, and converts it into a test waveform pattern. It outputs to the drive circuit 6 (its driver 7).

Next, the operation of generating a test waveform pattern will be explained.

150nsll from the reference point O as shown in Figure 2(a)
If we consider the case where a waveform pattern of 100 degrees Fahrenheit is to be generated, the start address at which this waveform pattern data is generated for the first data memory section 12a is set as shown in FIG. 2(b), for example. As you can see, if the address is 1000, then 10
Data from address 00 to "00100...fist" is stored in the second data memory section 12b.
For example, if the start address of is 500, then 500
If data "00100・Writing" is stored from address 1200 and the first address of the third data memory section 12c is, for example, address 1200, data of "000000100・Work" starting from address 1200 is stored in the same way. Remember. In addition, 1. Second. Each third data memory section 12
The respective start address values 1000, 500.1200 of a + l 2 b * 12 c are respectively stored from the test sequence processor 14 when the generated waveform pattern is selected.

Here, the reference point 0 in FIG. 2(a) corresponds to the access start time of the first address of the data memory section 12a, and the reference point 0 corresponds to the access start time of the first address of the data memory section 12a. The above waveform can be expressed by measuring the access cycle for accessing address 1 of the section. Note that the first flag bit "l" read from the data memory section 12c means q-low (or HIGH level state), and the next flag bit "1" means falling (or LOW level state). level). Then, the flag 0'' is used to maintain the previous state.

By the way, the access time of the pattern data memory 12 can be measured by the address update time of the address counter/access circuit 16, and it is determined by the address update time of the clock generation circuit 18 from the time when the first access or the next access is started. 1. Since it is determined by the total value of the second and third clock cycles, it can be expressed by the following equation.

64 Cn1-1)+8 (n2-1)+na-1[n
s] However, sfl/・n2. n3 is the flag “1”
This is the number of “0” bits until ” appears.

Note that each data memory section 12 at 12 be
It is assumed that the gradual access transition of 12c does not take much time. Therefore, the start address access between them is almost the same as the address access of the data memory section one stage before, and these are performed almost simultaneously.

In this way, the first rise time is the number of addresses from the first address position of the address counter/access circuit section 16a to the first read flag 1'' - 1 + the first rise time from the first address position of the address power counter/access circuit section 18b. It is determined by the total sum of the number of addresses up to the flag “1” read out in the first minus 1+the number of addresses up to the first flag “1” read out from the first address position of the address power counter/access circuit section 16c-1, The first . Second. The number of cycles of each third clock corresponds to the number of updates of each address,
There is a one-to-one correspondence between the number of address updates and the time.

In addition, the time required for γ to change to the next waveform is calculated in the same way from the next time access to the address of the first data memory section 12a is started, and this is added to the first access start time. By calculating these total values, 11
It is counted as 1.

Therefore, when the test waveform pattern rises to -L, each of the first . Second. Third data memo section 1
2 al l 2 t) + 12 Stand at address number of access cycle X addresses + 1 from the start address of c
- All you have to do is set a flag to indicate the difference.

Here, the first. Second. third data memory section 12a,
12 be 12 c each uses a bit memory, and FIG. 2(b) shows a specific example of the data memory K 12 a.
However, other things differ only in their memory data,
The configuration is similar. Therefore, the explanation of the same amount will be omitted.

FIG. 2(b) shows the storage state of the data memory section 12a in this 1-bit case, where 1-bit information is stored at the (2) address.

In such a case, the pattern data shown in FIG. 2(a) is 1000 in the first data memory section 12a.
Based on the address, a flag "0" is stored between addresses 1000 and 1001, and a flag "1" is stored at address 1002. Similarly, although not shown, the second data memory section 12b stores a flag 0" from address 500 to address 501, and stores a flag 1" at address 503, based on address 500. put.

Furthermore, although not shown, a third data memory section 12c
The flag is 0 between addresses 1200 and 1205.
, and store the flag “1” at address 1008 (
It is something.

As a result, when address 1006 of the data memory section 12c is accessed, the AND condition is satisfied in the AND circuit 13.
/, a rising pulse is generated, and a command signal is sent to the waveform edge generation circuit 20.

- On the other hand, as for the next \r difference point, access to the first data memory section 12a starts when the 1ooert= ground of the third data memory section 12c is accessed, so from this point on, the data is A time point 84X (m-
1) Write the flag 0'' until JF (m is a positive integer), and write the flag l'' corresponding to the rising edge at the time of 64Xm.

This is, for example, the data memory section 12a shown in FIG. 2(a).
The flag 1" is stored at the next address 1005. If the flag 1" is stored at the next address 1006, it means that the next \γ rise will occur in 84 ns or less.

If the above 1- is done, the first . Second. Each third data memory section 12a.

The flag storage location in memory 1 of 12b and 12c is the key to the rise of the pulse waveform (or the state of HIGH level!!
J) or stand-up (or LOW level state)
111. (
This waveform pattern can be set. Moreover, even if the period of the waveform is long, the total value of each memory access period corresponds to the period of the generated waveform pattern, so that the time can be reduced accordingly. As a result, the memory capacity 1i1 can be reduced.

By the way, by using a bit memory in the pattern data memory 12, if the same data memory section is provided corresponding to the pins of the IC and each pattern data corresponding to each IC bin is stored in this, the circuit The configuration is simplified and its control is also simple.

In the above case, the -γ rising flag and the -γ rising flag are separated by using 7 lags 1" for T, but the 1st, 2nd, and 3rd data memory sections 12
If a, l 2 b + 12 c are memories with a 2-via) configuration, then with "6, for example, 11")'Lchi! - Can be flagged, for example 10”
“01” can be used as a 17. difference flag.

In this way, ~y-difference and \gamma-difference can also be expressed using 2 bits or a plurality of bits more than 2 bits.

FIG. 3 shows another embodiment of the pattern data generating device of the present invention, and the same parts as those shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, the rising and falling positions of the test waveform pattern are stored as pattern data in separate memories, and instead of the pattern data memory 12, the data memory section 21 is used to detect the rising and falling positions of the test waveform pattern. The position is memorized as a flag ゛°1'', and the data memory section 2
2 is memorized as a 7 lag 1". Then, the waveform edge generation circuit 20 records the generated waveform at the timing when the flag lIs is read from each data memory section 21.22. )′1.chiI-ge, or \γ
Make a chilling motion. Note that, similar to the embodiment shown in FIG. 1, the pattern data memory 21 is accessed in stages. Second. Similarly, the pattern data memory 22 consists of a third memory section and an ANl) circuit, and the first... Second. 3rd memory part and ANl)
It consists of a circuit.

The operation includes, for example, storing a flag "1" at address 3 11 from the access position of the third memory section of the three memories n times in the pattern data memory 21, and storing the flag "1" in the pattern data memory 22. When the flag "l" is stored in 6 scattered locations 11 from the reference access position of the third memory section with a short period of A bit pattern of "0001" as shown in the figure is generated.

--Meanwhile, in the pattern data memory 22, the flag 1" is read out in the 7th cycle 1.1 of the third memory section at the final stage, and a focus pattern of "0000001" as shown in the figure is generated. Pattern data X″1. These are sequentially input to the waveform edge generation circuit 20 as rising, 1'/, and falling command signals, and the driver 7 of the drive circuit 6 (see FIG. 5) is activated at the time position corresponding to each cycle. It can be set to high or low level.

FIG. 4 shows still another embodiment of the pattern data generating device of the present invention, and parts similar to those shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, the first . Second. For example, the pattern data read from one address of each of the third data memory sections 23a, 23b, and 23c is taken as 1 byte, and it is read out in bit parallel.
Store in 15 b+ l 5 c.

Here, the shift register 15a includes the clock generation circuit 1
8a with a clock cycle of 64 ns, and the shift register 15b is shifted with a clock cycle of 64 ns by the clock generating circuit 18b.
The shift register 15 is shifted with a clock period of ns.
c is shifted by ins by the clock generation circuit 18b.

Then, when flag 1'' is read from each shift register 15a, 15b, 15c and the AND condition is satisfied, a command signal of 11 on the rising edge or 17 on the opposite side is generated from the AND circuit 13, and this is Corrugated work, Noji light production circuit 2
sent to 0.

The relationship between each data memory section 23a, 23b, 23C, starting and stopping 1., and operation are as follows:
a, l 2 b, 12 c, and corresponds to a data memory section 1 as a bit-configured memory.
The difference is that 2 all 2 b + 12 c is a byte-structured memory.

Similar to the embodiment shown in FIG.
The data “00100000” is stored in the first address of a, and the data “001000” is stored in the first address of the data memory section 23b.
The data "00" is stored, and the data "000oooio" is stored at the first address of the data memory section 23c.

The operation is as follows: First, the data memory section 23a is accessed, 1 byte of data is stored in the shift register 15a, and this is shifted every 64 ns.
The data is sent to the AND circuit 13, and when the flag "1" is detected, access to the data memory section 23a is stopped.

Then, based on this flag, access to the data memory section 23b is started and 1 byte of data is stored in the shift register 15b.

Next, while shifting this every 8 ns, A
When the flag 1'' is detected as a result of the shift in the shift register 15b, access to the data memory section 23a is stopped.Then, this flag is used to access the data memory section 23c and shift the data to the ND circuit 13. One byte of data is stored in the register 15C.Then, this is shifted every l·ns.As a result of this shifting, when a flag "1" is detected, it is sent to the AND circuit 13 and stored in the data memory section 23c. The access is stopped by 1-.As a result, a q rise command signal is sent to the waveform edge generation circuit 20.

Meanwhile, at the same time, the data memory section 23a is activated, the address is updated to the next, and the next 1 byte of data is stored in the shift register 15a.

The following operations are performed in the same manner, resulting in 11.<.

Incidentally, the execution operation of the microcommand program within the test sequence processor 14 itself is similar to the execution operation of a general microprogram. What is important here is that the test waveform pattern is stored in the pattern data memory.
- The time position of the falling state (or HIGH level) or falling (or falling 1'l falling state or LOW level) is stored as specific information, and the memory access cycle is the same as the time measurement. It is the foundation. Therefore, a series of test waveform patterns can be generated simply by setting the start address in each address counter/access circuit section using a microcommand.

As described above in 1., the data memory section in each embodiment has three blocks, but this is not limited to three blocks and may be any number of blocks.

In the embodiment, the data memory section reads out pattern data corresponding to a specific waveform pattern by specifying the start address, and the area of the data memory section is divided into one of the waveform generation patterns! It corresponds to the 114th length.

Different pattern data is stored in each area. Therefore, by storing the start address of another area in the address counter/access circuit, other waveform patterns can be generated.

In this case, when the same waveform pattern is repeatedly generated, the test sequence processor repeatedly stores the same start address in the address counter/access circuit using its microprogram.

Note that it is also possible to store pattern data corresponding to generated waveform patterns starting from address 0 without dividing the pattern data memory into areas in this manner. In this case, relatively long and complex pattern data can be stored. In this case, one pattern data memory becomes one waveform pattern generation circuit, and the area from address 0 to a specific final address corresponds to one waveform pattern.

Also, the flag is limited to the state of "1°", and the state of '0' is set to 1, 1, or 17. This is something that you can use without treating it as unique data.

Furthermore, in the embodiment, the timing of the generated waveform is measured using the access cycle of one address as the middle value, but this is not limited to the case where one bit of data is inserted into an address. For example, if you put 2 bits of data in 2 addresses, 'F is included, and 2 addresses rll (!:), the access cycle may be determined, and generally, ncn is an access cycle where 1 [an integer of :] is basically the 91st place. Of course, the timing may also be measured by using A as A.

Further, it goes without saying that the data memory section may be a RAM or a ROM.

[Effects of the Invention (1) As can be understood from the description, this invention has the following effects:
By storing pattern data in units of access cycles for accessing address n in memory, it is possible to determine whether the test waveform pattern goes up or down by 1"L using only time information. - is specified as i+J function.

As a result, data and timing do not have to be handled separately. Moreover, since the update period of the clock generation circuit is gradually becoming smaller, by specifying a combination of pattern data with different generation periods, even if the pattern data has a relatively long period, the storage capacity of the memory ld is small. You can memorize it with

Therefore, it is possible to generate various waveform patterns with relatively long cycles without consuming memory capacity, and test waveform patterns can be easily generated, and their management and control are simple. becomes.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of a pattern generator according to the present invention, FIG. 2(a) is an explanatory diagram of a specific example of a waveform pattern that should be generated, and FIG. FIG. 3 is a schematic block diagram of another embodiment of the pattern data generating device of the present invention, and FIG. 4 is a schematic block diagram of another embodiment of the pattern data generating device of the present invention. FIG. 5 is a block diagram of a conventional pattern data generator, and FIG. 6 is a waveform generation timing chart thereof. 1... Pattern generator, 2... Data selector, 3
... Waveform formatter, 4... Timing generator, 6... Next-stage drive circuit, 7... Driver, ?
a + 7 b...Reference voltage source module, lO...
・Pattern generator, 12a, 12b+ 12c, 23a, 23b, 23c
...Data memory section, 13...A N D circuit, 1
4...Test sequence processor, 15...Shift register, 16...Address counter/access circuit, 18A,
18b, IE3c...Address counter/access circuit section, 18...Clock generation circuit. 20... Waveform edge generation circuit.

Claims (4)

[Claims] (1) A plurality of memories each storing pattern data corresponding to the timing of a generated waveform pattern, each having an access cycle for accessing address n (n is a positive integer) of the memory, and each corresponding to each of these memories. It has a plurality of address counters that store access addresses of the memory, and a clock generation circuit that periodically updates the respective address values corresponding to these address counters, and generates data based on pattern data obtained by accessing the plurality of memories. A predetermined waveform pattern is generated, and the plurality of memories are sequentially accessed in stages, and the update period for each address counter of the clock generation circuit becomes sequentially smaller in accordance with the order in which the stages become later. A pattern generator characterized in that: (2) The generated waveform pattern is a test waveform pattern for testing an IC, and each of the plurality of memories is a bit memory, and each bit forms pattern data corresponding to one pin of the IC. , is provided corresponding to a drive circuit provided corresponding to one pin of the IC, and the pattern data is set to the HIGH level based on a predetermined address in response to the HIGH level or LOW level state of the test waveform pattern. Alternatively, the pattern generating device according to claim 1 is formed by recording information of a specific digital signal at an address position measured with an intermediate access cycle corresponding to the timing of the LOW level. . (3) The generated waveform pattern is a test waveform pattern for testing the IC, and each of the plurality of memories is a bit memory, and each bit unit forms pattern data corresponding to one pin of the IC. , is provided corresponding to the drive circuit provided corresponding to the IC pin, and the pattern data corresponds to the rising or falling timing of the test waveform pattern based on a predetermined address. 2. The pattern generating device according to claim 1, wherein the pattern generating device is formed by recording information of a specific digital signal at an address position measured in units of access cycles. (4) A patent claim characterized in that the pattern data is formed as information in which a rising state corresponds to one value of a binary signal and a falling state corresponds to the other state of the binary signal. The pattern generator according to item 3.