JPS6253514A - Pattern generator - Google Patents

Abstract

PURPOSE:To generate easily the generation of a test waveform pattern by storing respectively each pattern corresponding to plural generated waveform patterns in plural storage areas respectively. CONSTITUTION:An access period accessing an address (n) (where; n is a positive integer) of a memory is used as the unit, a pattern data corresponding to a generated waveform pattern is stored in a memory 12 and a prescribed waveform pattern is generated based on a pattern data obtained by accessing sequentially the memory. The memory has plural storage areas M1, M2, Mi, Mn, stores respectively each pattern data respectively corresponding to the plural generated waveform patterns in the plural storage areas and when the generated waveform pattern rises or descends is designated by the memory only with time information. Thus, the generation of the test waveform pattern is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry-L] This invention relates to a pattern generator, and in particular to a pattern generator that generates respective waveform patterns for a plurality of IC test pins, such as test waveform patterns for IC inspection. Regarding the generator.

[Conventional technology] In an IC testing system, it is necessary to automatically generate a multi-bit test waveform pattern necessary for performance and functional testing of an IC according to a test pattern program or the like.

Conventionally, in such test waveform pattern generators, the necessary data for each IC pin is selected from among the pattern data created by the pattern generator and the clock signal created by the timing generator. are selected and synthesized to generate a predetermined waveform. This is then sent to a drive circuit, its output is level-converted, and then supplied to a predetermined IC pin.

As an example, a specific circuit as shown in FIG. 6 can be cited.

1 is a pattern generator, which is composed of, for example, a predetermined ROM, and which accesses a predetermined address.
C Pattern A + seen in (a) and (b) of Figure 7
Predetermined pattern data such as Putter/B is generated, and the data selector 2 selects the necessary pattern data at a predetermined timing, and the waveform formatter 3
sent to.

On the other hand, (d) of FIG. 7 generated by the timing generator 4
), one of the various timing signals shown in timing waveforms (1) and (2) in (e) is selected by the timing selector 5 at a predetermined timing,
It is sent to the waveform formatter 3.

For example, if pattern data turn B is selected, the waveform formatter 3 generates the pattern data shown in FIG. 7(C) as a composite pattern of AB. 2) are selected, and in accordance with these, a waveform formatter output of a test waveform pattern as shown in FIG. 7(f) is generated.

The output signal of this waveform formatter 3 is sent to the driver 7 of the next stage drive circuit 6 as a test waveform pattern. Then, via the drive circuit 6, a corresponding waveform pattern of a predetermined voltage is applied to a specific pin of the IC to be tested inserted into a socket on the handler side, for example.

Note that 7a and 7b are reference voltage source modules that supply the driver 7, and these provide a stable voltage VIH (
HIGH level setting voltage value).

VIL (low level set voltage value) is supplied to the driver 7.

[Problem to be solved] Now >l/! As conductor integrated circuits become more sophisticated, the waveform patterns applied during testing tend to become more complex. Therefore, in the case where a predetermined waveform pattern is generated using a pattern generator and a timing generator as described above, the types of waveforms that can be generated are determined by the hardware configuration, and various test waveform patterns are generated. There are drawbacks that cannot be addressed.

In addition, in order to provide flexibility in test waveforms and logic values for each pin, a corresponding selection circuit is required, and when the number of bins increases, the circuit scale increases and speed is impaired. There is a problem that the entire device becomes larger.

[Object of the Invention] It is an object of the present invention to solve the problems of the prior art and to provide a pattern generation device that can generate various and complex test patterns with a simple configuration.

[Means for solving the problem] By the way, any logical waveform can be regarded as an NRZ waveform when viewed assuming a period shorter than the pulse width. This invention focuses on this point, and instead of determining the waveform of a logic signal based on logic data, the type of waveform, and its timing, as in the past, the waveform of a logic signal is determined by the... In this method, the point in time when \r is different is measured from the reference point, and the timing time is managed using the memory access cycle as the intermediate time.

Therefore, the means in the pattern generation device of the present invention for achieving the objective 1 is to address n address (n
is a positive integer), the access cycle is set to medium, pattern data corresponding to the generated waveform pattern is stored in memory, and a predetermined waveform pattern is generated based on the pattern data obtained by sequentially accessing this memory. 1. The memory has a plurality of storage areas, and each pattern data set corresponding to a plurality of generated waveform patterns is stored in each of the plurality of storage areas.

[Operation] By configuring in this way, the generated waveform pattern is
It becomes possible to specify in the memory when to stand up and down and when to stand up and down, using only time information, and there is no need to handle data and timing separately. As a result, test waveform patterns can be easily generated, and their management and control become simple.

Furthermore, since pattern data corresponding to test waveform patterns is stored in a plurality of areas, various waveform patterns can be easily generated by simply selecting an area.

In addition, by storing basic waveform pattern data in several areas each with a fixed cycle length, complex waveform patterns can be easily created by combining these data and sequentially accessing them. can be generated.

Therefore, the degree of freedom is large and the hardware configuration is simple. Further, the circuits of each bin of the test IC can be realized as the same circuit (meaning that the same memory is used).

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of a pattern generator according to the present invention, FIG. 2(a) is a specific example of a waveform pattern to be generated, and FIG. 2(b) is a diagram showing the case in which FIG. 2 is an explanatory diagram showing the stored contents of a pattern data memory of FIG.

The pattern generator 10 is an I
It generates a test waveform pattern for CJj3, and includes a pattern data memory 12, a test sequence processor 14, an address counter/access circuit 16, a clock generation circuit 18, and the like.

The test sequence processor 14 stores microcommand programs necessary for generating various test waveform patterns in its internal memory, and by executing the microcommand programs, it generates start address information a for the pattern data memory 12 as well as , starts up the clock generation circuit 18.

The pattern data memory 12 is a device under test (IC).
A plurality of pattern data are stored in the internal memory corresponding to various waveform patterns required for performance 9 functional tests, and each pattern data is stored in the storage area M/M which is divided into equal areas with equal length. , M2. ”..., Mj, e are respectively stored in the fist Mn.

Each of these storage areas is specified by address information (and read control signal) given from the address counter/access circuit 16, and data is sequentially transferred from each address based on the start address of the storage area to the pattern data h.
and output it as bit data/waveform conversion circuit 20.
Send to.

The bit data/waveform conversion circuit 20 converts the bit pattern data output from the pattern data memory 12 into a test waveform pattern and outputs it to the drive circuit 6 (its driver 7).

Here, the address counter/access circuit 16 stores the start address value of the pattern data memory 12 from the test sequence processor 14. This address value is then updated by a clock signal from clock generator circuit 18 activated by test sequence processor 14 .

Each time the at.l/s is updated, the address counter/access circuit 16 reads data from the pattern data memory 12 and sends out a control signal.

Therefore, the generation timing of pattern data read from the pattern data memory 12 is determined by the speed at which the address counter/access circuit 16 accesses the memory, which in turn is determined by the period of the basic clock of the clock generation circuit 18. .

The first bit of the first address value stored in the address counter/access circuit 16 from the test sequence processor 14, for example, the upper two bits (2) specifies one of the divided areas of the pattern data memory 12.

and its lower bits.

For example, the lower 8 bits L8 become the access address of the data pattern in that area.

Note that, as mentioned above, if the upper bits are 2 bits and the -higher bits are 8 bits, the pattern data memory 1
2 is divided into four areas and stores four pattern data, and the length of each pattern data is 256 bits since the upper part is 8 bits. The address updated by the clock signal from the clock generation circuit 18 is done within the range of only the upper 8 bits L8.

Next, the operation of generating a test waveform pattern will be explained.

Considering the case of generating a waveform pattern as shown in Fig. 2 (a), this waveform rises after 50 ns from reference point 0, falls after 150 ns from reference point O, and then starts from reference point O. It can be understood as a waveform pattern in which q changes after 850 ns and rises to F after 750 ns.

Therefore, when trying to generate a waveform like this,
If you manage the rise time from the reference point O and the γ difference time, 1. It can be expressed regardless of the period of the waveform.

If this reference point O corresponds to the access start time of the first address of the pattern data memory 12, and each rising time and falling time are measured in the access cycle of accessing memory address 1, the above waveform can be expressed. .

Here, the access time of the pattern data memory 12 can be measured by the address light refresh time of the address counter/access circuit 16, which is determined by the clock cycle of the clock generation circuit 18. That is, the number of clocks generated by the clock generation circuit 18 from the first address position corresponds to the number of address updates, and the number of address accesses and time are determined on a one-to-one basis.

Therefore, when the test waveform pattern rises, a flag indicating the rise is set at the access period X address number+1 from the start address of the pattern data memory 12. If this flag is made up of 2 bits,
The data flag is "for example 11".
It can be stiffened. If the voltage falls in the same way, it is sufficient to set a falling flag at the access cycle X number of addresses +1. The rising edge data flag can be set to .gamma. difference, for example, by .degree.'30'' or .degree.'01''.

In this way, it is also possible to express rising, rising and falling with multiple bits, but if the flag is one bit, flag 1'' can be expressed as rising, rising and falling (or HIG).
When the flag 0" is set to high level (H level state), the flag is set to
Alternatively, it can also be expressed as a LOW lz bevel state).

FIG. 2(b) shows the storage state of the pattern data memory 12 in this j-bit case, and this memory is a bit memory that stores 1-bit information at the 1,1 address. Assume now that the address update time of the clock generation circuit 18 is 1 on 8 cycle, and that pattern data corresponding to the waveform pattern of FIG. 2 is stored in the storage area M3 of the third L1. In this third area II, the 1st-order 2 bits H2 are specified by "10" and start from address 512.

Therefore, address 512 is the standard address for access (first location).
Considering the test waveform pattern in Fig. 2 (21), after 50 r1s, the address will be 517, and it will be 150 ns.
After 52727, after 650 ns, 577
address, and after 750 ns, address 58787 will be accessed.

In such a case, as shown in FIG. 2(b), when address 51212 of the pattern data memory 12 is accessed sequentially, the flag "0" is stored between addresses 512 and 518, and Flag 1'' is stored between addresses 517 and 526, flag ``0'' is stored between addresses 527 and 576, and flag ``0'' is stored between addresses 577 and 586.
Flag 1" is stored until the address. By this,
If access to the pattern data memory 12 is started from the 512 location, a bit pattern corresponding to FIG. 2(a) is obtained.

The output pattern of the pattern data memory 12 is then sent to the bit data/waveform conversion circuit 20, converted into the putter data shown in FIG. 2(a), and sent to the driver 7 of the drive circuit 8.

Note that the bit data/waveform conversion circuit 20 in this case is as follows:
This is a circuit that converts bit data encoded by so-called NRZ into a pulse waveform. Note that if the address update time of the clock generation circuit 18 is 100 ns, then 51
If you sequentially access address 212, 1
After μs, address 10 will be accessed.

By doing so, the flag storage position in memory L of the pattern data memory 12 will indicate the rising edge (or HIGH level state) or falling edge (or LOW level state) of the pulse waveform.

By the way, in this embodiment, the area of the pattern data memory is equally divided into areas, but the method of division is not necessarily equal (or may be).If multiple pieces of pattern data are stored in multiple areas, In this case, the length of pattern data stored in each area is often not equal.The start address of each area is managed by the test sequence processor 14.In addition, if the pattern data is divided evenly, Since the length of pattern data stored in each area is equal, it is easy to access the next area in combination so that the next area can be accessed continuously after the previous area has been accessed under the control of the test sequence process. These pattern data can be easily used in combination.As a result, complex waveform patterns can be easily generated.

Furthermore, here, an example is given in which the area is divided into four areas, but it is sufficient if the area is divided into a plurality of areas.

Now, FIG. 3 shows another embodiment of the pattern data generating device of the present invention, and the same parts as those shown in FIG. 1 are designated by the same symbols.

In this embodiment, the positions of the rising edge and rising edge of the test waveform pattern are stored as pattern data in separate memories, and instead of the pattern data memory 12, the pattern data memory 12a is used as pattern data. The position of the trailing edge is stored as a flag 1'', and the pattern data memory 12b stores the position of the trailing edge as a flag 1''. Note that these pattern data memories 12
Similarly to the pattern data memory 12, the storage areas of the pattern data memory a and 12b are divided.

Then, the waveform generation circuit 13 increases or decreases the generated waveform by Nγ1] at the timing when the flag 1'' is read from the respective pattern data memories 12a and 12b.

For example, assuming that the first divided area is selected in each of the pattern data memories 12a and 12b, flag 1'' is stored at address 3 of the pattern data memory 12a, and flag 1'' is stored at address 3 of the pattern data memory 12b.
When flag 1" is stored at the address, the address counter/access circuit 16 counts sequentially from address 0, the memory address increases sequentially, and in the pattern data memory 12a, the flag "1" is stored in the fourth cycle. The data is read out, and a bit pattern of "ooooiooo" as shown in the figure is generated.

- On the other hand, in the pattern data memory 12b, flag 1 is read out in the 7th cycle, and as shown in the figure, "ooooo" is read out.
A bit pattern of "ooio" is generated. These are sequentially input to the waveform generation circuit 13 as command signals for the rising and falling edges of the pattern data, and are input to the drive circuit 6 at time positions corresponding to each cycle. The dry z<7 (see FIG. 8) is set to a high level or a low level.

FIG. 4 shows still another embodiment of the pattern data generating device of the present invention, and the same parts as those shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, the pattern data read from one address of the pattern data memory 12c similarly divided into areas is, for example, one byte, which is read out in bit parallel and temporarily stored in the shift register 15. Then, pattern data is serially read out from the shift register 15 and sent to the bit data/waveform conversion circuit 20.

Note that when the waveform rises (or HIGH level state) or falls (or LOW level state), as in the case of FIG. 1, first set the flag "1" to -
As a bittern, if the flag ``0'' is expressed as a rising edge, the position where bit ``1'' of the 8 bits is set is the point at which the rising edge occurs, as shown in Figure 5. . This timing is further added to the time when the address of the pattern data memory 12c is accessed.

The time at which this addition is performed is determined by the time when the shift register 15 shifts bits.
By setting a value shorter than the access cycle of c, more precise timing can be set.

In this way, by reading data in parallel using a shift register, it is possible to generate high-speed pattern data, and fine timing control can be realized.

Incidentally, the execution operation of the microcommand program within the test sequence processor 14 itself is similar to the actual operation of a general microprogram. What is important here is that the test waveform pattern is stored in the pattern data memory.
The time position of the falling state (or falling state, or HIGH level) or falling state (or falling state, or LOW level) is stored as specific information, and the access cycle of the memory is used as the reference for time measurement.

Therefore, a series of test waveform patterns can be generated simply by setting the start address in the address counter/access circuit using a microcommand.

As described above, in each embodiment, a plurality of address counter/access circuits and pattern data memories are provided corresponding to the pins of the test IC. In this case, the test sequence processor, clock generation circuit, etc. can be used in common for each address counter/access circuit and pattern data memory.

Furthermore, in this example, the pattern data memory is for reading pattern data corresponding to a specific waveform pattern by specifying the start address, and the area of the pattern data memory is divided into one unit length of the waveform generation pattern. It corresponds to Different pattern data is stored in each area. Therefore, by storing the start address of another area in the address counter/access circuit, other waveform patterns can be generated.

In this case, when the same waveform pattern is repeatedly generated, the strike sequence processor repeatedly stores the same start address in the address counter/access circuit using its microprogram.

Further, in the embodiment, in the case of 1 bit or 2 bits, each focus represents the rising or falling edge. However, this may be expressed as 1-byte data, and furthermore, in the case of rising pattern data, the first flag 1'' causes the flag to rise.
Set the intersection 1j so as to indicate the y difference position with the next flag "1 pa", and use only 1 bit flag to indicate the waveform's 17', difference or 11 [- difference]. Of course, the position may also be expressed.

Furthermore, the flag is not limited to the "1" state, but the "0" state can be used as \y minus one or -r falling data.

Furthermore, in the embodiment, the timing of the generated waveform is measured using the access period of one address as a unit, but this is not limited to writing one bit of data to one address; You can write 2-bit data and determine the access cycle in units of 2 addresses.Generally, the timing is calculated based on the access cycle with n (n is a positive integer) as the basic unit.
Of course, it is also possible to do this.

Furthermore, even if the pattern data memory is RAM, R
Of course, it may be OM.

Although the test waveform pattern generating device has been described as an embodiment of the present invention in 1-6, it goes without saying that the present invention can be applied to other similar pattern data generating devices.

[Effects of the Invention (1) As can be understood from the description, this invention has the following effects:
The access period for accessing address n (n is a positive integer) of the memory is used as a unit, pattern data corresponding to the generated waveform pattern is stored in the memory, and a predetermined value is determined based on the pattern data obtained by sequentially accessing this memory. The memory has a plurality of storage areas, and each pattern data corresponding to the plurality of generated waveform patterns is stored in the plurality of storage areas. When does the waveform pattern start?
Make a memo with just the time information of when the L will go down and when it will go down.
, Th, and there is no need to handle data and timing separately. As a result, test waveform patterns can be easily generated, and their management and control become extremely simple. Moreover, since the pattern data corresponding to the test waveform patterns are stored in a plurality of areas, various waveform patterns can be generated in mi simply by selecting an area.

In addition, if you store tree-like waveform pattern data in several areas, each with a fixed period length, you can create complex waveform patterns by combining them and sequentially accessing them. Therefore, it can be generated in 41 seconds.

Therefore, the degree of freedom is large, and the hardware configuration is pure f11. Further, the circuits for each pin of the test IC can be realized as the same circuit (meaning that the same memory is used).

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the pattern generator according to the present invention, FIG. 2(a) is an explanatory diagram of a specific example of a waveform pattern to be generated, and FIG. , an explanatory diagram showing the storage contents of the pattern data memory in that case, Part 3
FIG. 4 is a schematic block diagram of another embodiment of the pattern data generating device of the present invention, FIG. 4 is a schematic block diagram of still another embodiment of the pattern data generating device of the present invention,
FIG. 5 is an explanatory diagram of a specific example of pattern data stored in one address of the pattern data memory, FIG. 6 is a block diagram of a conventional pattern data generator, and FIG. 7 is a waveform generation timing chart thereof. It is. ■...Pattern generator, 2...Data selector, 3
... Waveform formatter, 4... Timing generator, 6... Next stage drive circuit, 7... Driver, 7
a + 7 b...Reference voltage source module, 10.
...Pattern generator, 12+12 a, 12 b, 12 c.=pattern data memory, 13... Waveform generation circuit, 14... Test sequence processor, 15... Shift register, 16... Address counter /Access circuit, 18...
・Clock generation circuit. 20...Bit data/waveform conversion circuit. M/9M21Ml, Mn--Storage area. Figure 1 Figure 2 (0-) Figure 2 (b) Figure 4 Figure 3 Figure 5 Figure 6 Figure 7

Claims (4)

[Claims] (1) The pattern data corresponding to the generated waveform pattern is stored in the memory, and the pattern obtained by sequentially accessing this memory is determined by the access period in which the address n (n is a positive integer) of the memory is accessed. A predetermined waveform pattern is generated based on data, and the memory has a plurality of storage areas, and each pattern data corresponding to the plurality of generated waveform patterns is stored in each of the plurality of storage areas. A pattern generator characterized by being memorized. (2) The generated waveform pattern is a test waveform pattern,
The memory is a bit memory, and its access is performed every time the address counter is updated in accordance with the clock cycle, and the access cycle is determined by this clock cycle, and the pattern data is the HI of the generated waveform pattern.
By recording information on a specific digital signal at an address position measured in units of access cycles in response to the timing of the HIGH level or LOW level with a predetermined address as a reference in response to the state of the GH level or LOW level. Claim 1 characterized in that:
The pattern generator described in Section 1. (3) The generated waveform pattern is a test waveform pattern,
The memory is a bit memory, and its access is performed every time the address counter is updated in accordance with the clock cycle.The access cycle is determined by this clock cycle, and the pattern data is based on the generated waveform pattern. Formed by recording information of a specific digital signal at an address position that is measured in units of access cycles corresponding to the timing of the rising or falling edge based on a predetermined address in response to the rising edge or falling edge. A pattern generating device according to claim 1, characterized in that: (4) The pattern data is formed as information in which the rising edge corresponds to one value of the binary signal and the falling edge corresponds to the other state of the binary signal, and the generated waveform pattern is
4. The pattern generating device according to claim 3, wherein NRZ data is reproduced from this pattern data.