JPS6254179A - Pattern generating device - Google Patents

Abstract

PURPOSE:To generate multifarious and complicated test patterns using simple constitution by measuring rise time and fall time from a reference point and controlling time of timing making access period of a memory a unit time. CONSTITUTION:When a reference point is made to correspond to access start time of the first address of a pattern data memory 12 and rise time and fall time from the reference point is controlled, waveform expression is made possible regardless of waveform period. Access time unit of the memory 12 can be measured by address update time of an address counter/address circuit 16, and determined by clock period of a clock generating circuit 18. Accordingly, when the test waveform pattern rises of falls, it is enough to put up a flag of rise or fall at a place access period X number of addresses + 1 from the first address of the memory 12. Thus, time of rise or fall can be designated on the memory only by time information, and it becomes unnecessary to deal with data and timing separately, and accordingly, generation of test waveform patterns is made easy.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pattern generator, and in particular to a pattern generator that generates respective waveform patterns for a plurality of IC test pins, such as a test waveform pattern for IC inspection. Regarding the generator.

[Prior Art] In IC testing/systems, it is necessary to automatically generate a multi-bit test pattern required for performance 9 functional testing in accordance with a test pattern program or the like.

Conventionally, in such a test waveform pattern generator, each pin of c is extracted from each of the pattern data created by the pattern generator and the clock signal "I" created by the timing generator. A method is adopted in which the required waveforms are selected and synthesized to generate a predetermined waveform, which is then sent to a drive circuit, whose output is level-converted and supplied to a predetermined IC pin.

As an example, a specific circuit as shown in FIG. 6 can be cited.

7 is a pattern generator, which is composed of, for example, a predetermined ROM, and which accesses a predetermined address to generate predetermined patterns such as pattern A and pattern B shown in FIG. 7(a) and (b). The data selector 2 selects necessary pattern data at a predetermined timing and sends it to the waveform formatter 3.

On the other hand, (d) of FIG. 7 generated by the timing generator 4
), (e) timing waveform H), one of the various timing signals shown in (2) is selected by the timing selector 5 at a predetermined timing and sent to the waveform formatter 3.

Here, if, for example, pattern A and pattern B are selected, the waveform formatter 3 displays (C) in FIG.
The pattern data shown in is generated as a composite pattern of AB, for example, timing waveforms (1) and (2) are selected respectively, and according to these, the waveform formatter of the test waveform pattern as shown in <r> of FIG. Generate output.

The output signal of this waveform formatter 3 is sent to the driver 7 of the next stage drive circuit 6 as a test waveform pattern. Then, via the drive circuit 6, a corresponding waveform pattern of a predetermined voltage is applied to a specific pin of the IC to be tested inserted into a socket on the handler side, for example.

Note that 7a and 7b are reference voltage dual-source modules that supply the driver 7, and these provide a stable voltage VIH.
(HIGH level setting voltage value).

VIL (low level set voltage value) is supplied to the driver 7.

[Problems to be Solved] As conductor integrated circuits become more sophisticated, the waveform patterns applied during testing tend to become more complex. Therefore, in the case where a predetermined waveform pattern is generated using a pattern generator and a timing generator as described above, the types of waveforms that can be generated are determined by the hardware configuration, and various test waveform patterns are generated. There are drawbacks that cannot be addressed.

In addition, in order to provide flexibility in test waveforms and logic values for each pin, a corresponding selection circuit is required, and when the number of bins increases, the circuit scale becomes unwieldy (and speed is reduced). However, there is a problem in that the entire device becomes larger.

[Object of the Invention] The present invention aims to solve the problems of the prior art and to provide a pattern generator capable of generating various and complex test patterns with a simple configuration. shall be.

[Means for Solving the Problem] By the way, any logical waveform can be regarded as an NRZ waveform when viewed assuming a period shorter than the pulse width. This invention focuses on this point, and instead of determining the waveform of a logic signal based on the logic data, the type of waveform, and its timing, as in the past, the waveform of the logic signal is determined by 1'/ of the pulse.

Chi-1-kari, X7. This method measures the deviation point from the reference point, and manages the timing using the memory access cycle as a unit of time.

Therefore, the first stage in the pattern generator of the present invention for achieving the above objects is a memory! No. 1 (
n is a positive integer), the pattern data corresponding to the generated waveform pattern is stored in a memory, and a predetermined waveform pattern 7 is created based on the pattern data obtained by sequentially accessing this memory. It is said that it occurs.

[Operation] With this configuration, the generated waveform pattern is
It becomes possible to specify when to rise and when to fall in memory 1- using only time information, and data and timing do not have to be handled separately.As a result, , it becomes easy to generate a test waveform pattern, and its management and control become simple.

Moreover, it is possible to generate a test waveform pattern in one unit, which provides a large degree of freedom and simplifies the hardware configuration. Furthermore, the circuits for each pin of the test IC can be realized as the same circuit (meaning that the same memory is used).

[Embodiment Code] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of a pattern generator according to the present invention, FIG. 2(a) is a specific example of a waveform pattern to be generated, and FIG. 2(b) is a diagram showing the case in which FIG. 2 is an explanatory diagram showing the memory contents of the pattern generator of FIG.

The pattern generator IO is used as a pattern generator IO in the IC inspection system.
Generates a test waveform pattern for C inspection.
pattern data memory 12, test sequence processor 14. It includes an address counter/access circuit 16, a clock generation circuit 18, and the like.

The test sequence processor 14 stores microcommand programs necessary for generating various test waveform patterns in its internal memory, and by executing the microcommand programs, it generates start address information +jIJa for the pattern data memory 12 and , starts up the clock generation circuit 18.

The pattern data memory 12 is a device under test (IC).
The pattern data necessary for the performance and Ia performance tests is stored in the internal memory, and the address information and readout given from the address counter/access circuit 16;
It sequentially outputs data as pattern data h from the address specified by the +, f, and sends it to the bit data/waveform conversion circuit 20.

The bit data/waveform conversion circuit 20 converts the bit pattern data output from the pattern data memory 12 into a test waveform pattern and outputs it to the drive circuit 6 (its driver 7).

Here, the address counter/access circuit 16 stores the start address value of the pattern data memory 12 from the test sequence processor 14. Thereafter, this address value is applied to the clock signal 5j- from the clock generation circuit 18 activated by the test sequence processor 14.
Updated by.

Each time the address is updated, the address counter/access circuit 16 sends a read control signal to the pattern data memory 12.

Therefore, the generation timing of pattern data read from the pattern data memory 12 is determined by the speed at which the address counter/access circuit 16 accesses the memory, which in turn is determined by the period of the basic clock of the clock generation circuit 18. .

Next, the operation of generating a test waveform pattern will be explained.

Considering the case where a waveform pattern as shown in Fig. 2(a) is generated, the waveform rises to L after 50 ns from the reference point 0, and this waveform changes to -y and F after 150 ns from the reference point O. Furthermore, it can be understood as a waveform pattern that changes from point O to q in 850 ns, and then changes by q in 750 ns.

Therefore, when trying to generate a waveform like this,
By managing the \γ difference time and the ~1 difference time from the reference point O, it can be expressed as (,) related to the period of the waveform.

this), 1. '/' point O is pattern data memory 1
Corresponding to the access start time of the first address of 2,
Memory 1 for each 1'I difference time and -r difference time
The above waveform can be expressed by measuring the access cycle for accessing the address.

Here, the access time of the pattern data memory 12!
The 11th place can be measured by the address update time of the address counter/access circuit 16, which is determined by the clock cycle of the clock generation circuit 18. That is, the number of clocks generated by the clock generation circuit 18 from the first address position corresponds to the number of address updates, and the number of address accesses and time are determined on a one-to-one basis.

Therefore, when the test waveform pattern is increased by ~7 degrees, a flag indicating a difference of s7 degrees by -1- is set to X'1. Out. If this flag were to have a 2-bit configuration, the data flag would be "for example 11".
” can be set to ~7 chi-1]. Similarly, if ~χ is a difference, the 1γ difference flag can be set by 1γ at the access period x number of addresses + 1. The 1y difference data flag can be set to -χ difference by, for example, "IO" or "Ol".

In this way, it is possible to use multiple bits to express q 1 - or rising edge, but if the flag is 1 bit, then flag 1'' is q 1 - 1 (the younger bit < is HIGH).
The flag 0'' can also be expressed as a rising flag (or a LOW level state).

FIG. 2(b) shows the storage 4J state of the pattern data memory 12 in this 1-bit case, and this memory stores 1-bit information at 1 address. Now, suppose that the address update time of the clock generation circuit 18 is Io
Considering the test waveform pattern in Fig. 2(a) with a period of ns and address 1000 as the reference address (first address) for access, after 5 On s, the address becomes 1005,
After 15 On S, the totSi address is accessed, after 650 ns, address 1065 is accessed, and after 750 ns, address 1075 is accessed.

In such a case, as shown in FIG. 2(b), if the pattern data memory 12 is accessed sequentially from address 1000 to i4/',
Flag 0'' is stored up to address 04, and from address 1005 onwards.
The flag “1” is stored until address 1014, and
The flag 0'' is stored between addresses 1064 and 1064.
A flag "1" is stored between addresses 65 and 1074.

As a result, if access to the pattern data memory 12 is started from address 100, a bit pattern corresponding to FIG. 2 (21) can be obtained.

The output bit pattern of the pattern data memory 12 is then sent to the bit data/waveform conversion circuit 20, converted into the putter data shown in FIG. 2(a), and sent to the driver 7 of the drive circuit 6.

Note that the bit data/waveform conversion circuit 20 in this case is as follows:
This is a circuit that converts bit data encoded by so-called NRZ into a pulse waveform. Note that if the address update time of the clock generation circuit 18 is 100 ns, then 10
If access is performed sequentially with address 00 as a reference, address 10 will be accessed after 1 μs.

By doing the following i-, the flag storage position in memory 1- of the pattern data memory 12 will indicate the rising edge (or HIGH level state) or falling edge (or LOW level state) of the pulse waveform. Become.

FIG. 3 shows another example of the pattern data generator of the present invention.
Components showing an embodiment and similar to those shown in FIG. 1 are designated by the same reference numerals.

In this embodiment, the positions of ~γ 1 and \y of the test waveform pattern are stored as pattern data in separate memories, and the pattern data memory 12a is replaced by the pattern data memory 12a. but~
7. The position of the difference is stored as a flag l'', and the pattern data memory 121) stores the position of the difference as a flag 'l'. And waveform generation circuit 1
3 operates to increment the generated waveform by s'f or -y at the timing when the flag "l11" is read out from the respective pattern data memories 12a and 12b.

For example, if a flag l" is stored at address 3 of the pattern data memory 12a and a 7 lag l" is stored at address 6 of the pattern data memory 12b, the address counter/access circuit 16 counts sequentially from address 0. , the memory address increases sequentially, and the pattern data memory 12
In a, flag 1'' is read out in the 4th cycle 11, and a bi-soto pattern of ``oootooooo'' as shown in the figure is generated.On the other hand, in the pattern data memory 12b,
At 7 cycles [1], the flag "l" is read out, and a bit pattern of "'ooooooio" as shown in the figure is generated.
These are sequentially input to the waveform generation circuit 13 as falling commands 5 and 5, and the driver 7 of the drive circuit 6 (see Fig. 6) is set to high or low level at the time position corresponding to each cycle. It is something to set.

FIG. 4 shows still another embodiment of the pattern data generating device of the present invention, and the same parts as 71 in FIG. 1 are designated by the same reference numerals.

In this embodiment, the pattern data read from one address of the pattern data memory 12c is, for example, one byte, which is read in bit parallel and stored in the ten shift register 15.

Then, pattern data is serially read out from the shift register 15 and sent to the bit data/waveform conversion circuit 20.

In addition, the rising edge of the waveform (or HIGH level state) or) γ difference (or LOW level state)
As in the case of FIG.
If the flag 0 is expressed as q falling, then the rising point will be at the position where bit ``l'' of the 8 bits is set as q, as shown in Figure 5. This timing is further added to the time at which the appeal area in the pattern data memory 12c is accessed.

The time at which this addition is performed is determined by the time during which the shift register I5 shifts bits.
By setting a value shorter than the access period of c, m
You can set the timing.

In this way, by reading data in parallel using a shift register, it is possible to generate high-speed pattern data, and fine timing control can be realized.

Incidentally, the execution operation of the microcommand program within the test sequence processor 14 itself is similar to the execution operation of a general microprogram. What is important here is that the test waveform pattern is stored in the pattern data memory as a rising edge (or rising edge state, or HIGH level condition) or The time 1111 position (state) is stored as specific information, and the memory access cycle is the reference for the time 1u1 measurement.

Therefore, a series of test waveform patterns can be generated simply by sending the start address to the address counter/access circuit using a microcommand.

As explained above, the address counter/access circuit and pattern data memory in each embodiment are inspected by inspection I.
A plurality of them will be provided corresponding to the C pins. In this case, the test sequence processor, clock generation circuit, etc. can be used in common for each address counter/access circuit and pattern data memory.

Furthermore, in this example, the pattern data memory is for reading pattern data corresponding to a specific waveform pattern by specifying the start address, and the area of the pattern data memory is divided into one unit length of the waveform generation pattern. It corresponds to Different pattern data is stored in each area. Therefore, by storing the start address of another area in the address counter/access circuit, other waveform patterns can be generated.

In this case, when the same waveform pattern is repeatedly generated, the strike sequence processor repeatedly stores the same start address in the address counter/access circuit using its microprogram.

Note that it is also possible to store pattern data corresponding to generated waveform patterns starting from address 0 without dividing the pattern data memory into areas in this manner. In this case, relatively long and complex pattern data can be stored. In this case, one pattern data memory becomes one waveform pattern generation circuit, and the area from address O to a specific final address corresponds to one waveform pattern.

In the embodiment, in the case of 1 bit or 2 bits, each bit has its 1'1. [chi] expresses nigari or \ydifference. However, this is 1
It may also be expressed as byte data (in addition, in the case of pattern data, the first flag is "1")'f,chi1,,gari, and the next It goes without saying that the flag 1'' may be set alternately to indicate the \f offset position, and only the 1-focus flag may represent the waveform's rising edge or σ offset L position.

Further, the flag is not limited to the ``1'' state, but the ``0'' state can be used as a redata for Nγchi1, , or \ychido.

Furthermore, in the embodiment, what is the access cycle of l address? 1
The timing of the generated waveform is measured as %1, but
This is not limited to 1-bit data being allocated to 1 address; for example, 2-bit data may be allocated to 2 addresses, and the access cycle may be determined at 2 addresses. , the timing is generally measured based on the access cycle with n (n is a positive integer) as the basic unit1.
Of course you can.

Furthermore, even if the pattern data memory is RAM, R
Of course, it may be OM.

Although the test waveform pattern generating device has been described as an embodiment of the present invention, the present invention can of course be applied to other similar pattern data generating devices.

[Effects of the Invention] 1. As can be understood from the explanation, in this invention, the access period for accessing address n (n is an integer of +E) in the memory is taken as a unit, and the access period corresponding to the generated waveform pattern is Since the pattern data is stored in memory and a predetermined waveform pattern is generated based on the pattern data obtained by sequentially accessing this memory, the generated waveform pattern can be X7. It is now possible to specify the timing in memory 1 using only time information, and data and timing can be fetched separately.)
There will be no need for it. As a result, test waveform patterns can be easily generated, and their management and control become simple.

Moreover, it is possible to generate a test waveform pattern in one unit, which provides a large degree of freedom, and the hardware configuration is in the middle. Furthermore, the circuits for each pin of the test IC can be realized as the same circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of a pattern generator according to the present invention, FIG. 2(a) is an explanatory diagram of a specific example of a waveform pattern to be generated, and FIG. 2(b) is FIG. 3 is a schematic block diagram of another embodiment of the pattern data generation device of the present invention, and FIG. 4 is an explanatory diagram showing the storage contents of the pattern data generation device of the present invention in that case. FIG. 5 is an explanatory diagram of a specific example of pattern data stored in one address of the pattern data memory, and FIG. 6 is a block diagram of a conventional pattern data generator. , and FIG. 7 are respective waveform generation timing charts. 1... Pattern generator, 2... Data selector, 3
... Waveform formatter, 4... Timing generator, 6... Next stage drive circuit, 7... Driver, 7a
, 7b... group is a voltage source module, 10... pattern generator, 12* 12 al l 2 b+ 12 c.
"Pattern data memory, 13... Waveform generation circuit, 14... Test sequence processor, 15... Shift register, 16... Address counter/access circuit, 18...
・Clock generation circuit. 20...Bit data/waveform conversion circuit.

Claims (4)

[Claims] (1) The pattern data corresponding to the generated waveform pattern is stored in the memory, and the pattern obtained by sequentially accessing this memory is determined by the access period in which the address n (n is a positive integer) of the memory is accessed. A pattern generator characterized in that it generates a predetermined waveform pattern based on data. (2) The generated waveform pattern is a test waveform pattern,
Memory access is performed every time the address counter is updated in accordance with the clock cycle, and the access cycle is determined by this clock cycle, and the pattern data is based on the HIGH level or LOW level state of the generated waveform pattern. corresponding to the HIGH level based on a predetermined address.
The pattern generation device according to claim 1, characterized in that the pattern generation device is formed by recording information of a specific digital signal at an address position measured in units of access cycles corresponding to the timing of the level or LOW level. . (3) The generated waveform pattern is a test waveform pattern,
Memory access is performed each time the address counter is updated in accordance with the clock cycle, and the access cycle is determined by this clock cycle, and the pattern data corresponds to the rising or falling edge of the generated waveform pattern. The digital signal is formed by recording information of a specific digital signal at an address position measured in units of access cycles corresponding to the rise or fall timing with respect to a predetermined address as a reference. The pattern generator according to scope 1. (4) The pattern data is formed as information in which the rising edge corresponds to one value of the binary signal and the falling edge corresponds to the other state of the binary signal, and the generated waveform pattern is
4. The pattern generating device according to claim 3, wherein NRZ data is reproduced from this pattern data.