JPS6253967B2 - - Google Patents
Info
- Publication number
- JPS6253967B2 JPS6253967B2 JP2636778A JP2636778A JPS6253967B2 JP S6253967 B2 JPS6253967 B2 JP S6253967B2 JP 2636778 A JP2636778 A JP 2636778A JP 2636778 A JP2636778 A JP 2636778A JP S6253967 B2 JPS6253967 B2 JP S6253967B2
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- signal
- voltage
- inverting input
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 230000001052 transient effect Effects 0.000 claims description 7
- 238000013459 approach Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
- H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Television Systems (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
本発明はデータ信号に含まれる低周波成分の影
響による比較基準値のずれを補償した比較回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit that compensates for deviations in comparison reference values due to the influence of low frequency components contained in data signals.
一般にデータ信号の送受信系においては、伝送
路にトランスやカツプリングコンデンサなどが挿
入されているため、データ信号の直流成分または
低周波数成分を忠実に伝送することは困難であ
る。一方、この種の伝送系の受信側においては、
データ信号の“1”“0”判定用の比較器の判定
しきい値(以下比較基準値という)として、低域
通過フイルタにより得られるデータ信号の平均電
圧を用いている。このため、例えばデータ信号と
して“1”が連続した場合に比較基準値がずれて
誤判定をすることがある。 Generally, in a data signal transmission/reception system, a transformer, a coupling capacitor, etc. are inserted in the transmission path, so it is difficult to faithfully transmit the DC component or low frequency component of the data signal. On the other hand, on the receiving side of this type of transmission system,
The average voltage of the data signal obtained by the low-pass filter is used as the determination threshold (hereinafter referred to as comparison reference value) of the comparator for determining whether the data signal is "1" or "0". For this reason, for example, when "1" continues as a data signal, the comparison reference value may deviate, resulting in an erroneous determination.
従来はこれを避けるために低域通過フイルタの
コンデンサの容量を大きくして出来るだけ低い周
波成分まで通過させるか、あるいはデータ信号自
身に処理を加えて低周波成分を除いた信号パター
ンを用いる必要があつた。 Conventionally, to avoid this, it was necessary to increase the capacitance of the low-pass filter capacitor to pass as many low frequency components as possible, or to use a signal pattern that removed low frequency components by processing the data signal itself. It was hot.
本発明の目的は、受信データ信号に含まれる低
周波成分の変動による比較基準値のずれを除去し
た比較回路を提供することにある。 An object of the present invention is to provide a comparison circuit that eliminates deviations in comparison reference values due to fluctuations in low frequency components contained in received data signals.
本発明によれば、非反転入力端子と反転入力端
子とを有しこれら非反転および反転入力端子への
入力信号を電圧比較する比較器と、前記非反転入
力端子に接続した信号入力端子と、この信号入力
端子と前記反転入力端子と間に接続した低域通過
フイルタと、前記比較器の出力と前記反転入力端
子との間に挿入した負帰還手段とを含む比較回路
が得られる。 According to the present invention, a comparator has a non-inverting input terminal and an inverting input terminal and compares voltages of input signals to the non-inverting and inverting input terminals, and a signal input terminal connected to the non-inverting input terminal; A comparison circuit is obtained that includes a low-pass filter connected between the signal input terminal and the inverting input terminal, and negative feedback means inserted between the output of the comparator and the inverting input terminal.
以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.
第1図は従来の比較回路の概略回路図であり、
第2図a,bはその動作タイムチヤートである。
例えばFM受信機の場合には、信号電界が入力さ
れると送信側中心周波数pに対して受信機の受
信中心周波数がある値Δだけずれているため、
周波数弁別回路出力ではそのΔに相当する直流
電圧が発生してその直流電圧が信号に加算されて
来る。このような場合、第1図の従来回路ではコ
ンデンサ18(容量値C1)、抵抗器19(抵抗値
R1より成る低域通過フイルタ1により比較基準
値V1は信号の平均電圧Vcに近づく。ここでフイ
ルタ1の時定数R1C1を大きくすると、比較基準
値x1が信号の平均電圧Vcに近づく時間が遅くな
り、比較回路2により正常な比較が出来るまでに
時間がかかる。また、逆に時定数R1C1を小さく
すると、第2図aの区間T1のように信号として
高レベルが連続した場合に、比較基準値x1は回路
1が低域通過フイルタであるため入力信号の高レ
ベルに近づいてしまう。このことは信号x0(電圧
V0)中に含まれる雑音に対して誤比較を起こす原
因ともなる。以上のように、従来の回路では信号
形式として高レベル、または低レベルが長く続く
ような信号パターンは使えない欠点がある。 FIG. 1 is a schematic circuit diagram of a conventional comparison circuit.
Figures 2a and 2b are operation time charts.
For example, in the case of an FM receiver, when a signal electric field is input, the receiving center frequency of the receiver deviates by a certain value Δ from the center frequency p of the transmitting side.
At the output of the frequency discrimination circuit, a DC voltage corresponding to Δ is generated, and the DC voltage is added to the signal. In such a case, in the conventional circuit shown in Fig. 1, capacitor 18 (capacitance value C 1 ), resistor 19 (resistance value
A low-pass filter 1 consisting of R 1 brings the comparison reference value V 1 close to the average voltage V c of the signal. If the time constant R 1 C 1 of the filter 1 is increased here, the time for the comparison reference value x 1 to approach the average voltage V c of the signal is delayed, and it takes time for the comparison circuit 2 to perform a normal comparison. Conversely, if the time constant R 1 C 1 is made smaller, when the signal continues to have a high level as shown in section T 1 in Figure 2a, the comparison reference value x 1 indicates that circuit 1 is a low-pass filter. Therefore, it approaches the high level of the input signal. This means that the signal x 0 (voltage
This can also cause erroneous comparisons due to noise contained in V 0 ). As described above, conventional circuits have the disadvantage that they cannot use signal patterns in which high or low levels continue for long periods of time.
第3図は本発明の一実施例である。第4図a〜
cはその動作タイムチヤートである、第3図にお
いて、比較基準値V3は入力x6(電圧V6)をコンデ
ンサ20(容量値C2)、抵抗器21(抵抗値R2)
から成る低域通過フイルタ3に通したものと、反
転器5の出力x5(電圧V5)を抵抗器22(抵抗値
R3)を通したものとの和になる。すなわち信号が
受信されて定常状態に達した後には、基策準値
V3は(V6P3+V5R2)/(R2+R3)となる。ここで
第4図aに示すように、理想比較基準値をVc、
データ信号の振幅をVsとする。今、第4図aの
区間T1のように信号が高レベルで続いてしばら
く時間が系過したとする。このときには入力信号
x6の電圧V6はVc+Vsだから基準値V3は{Vc
R3/(R2+R3)}+{(VsR3+V5R2)/(R2+
R3)}となる。ここでR2≪R3,V5=−VsR3/R2
と選べばV3Vcと与えられて、高レベル信号が
連続しても基準値V3は理想比較値Vcからはずれ
ることはない。以上は信号が高レベルで続いた場
合であるが、低レベルで連続する場合も同様であ
る。 FIG. 3 shows an embodiment of the present invention. Figure 4 a~
c is the operation time chart. In Fig. 3, the comparison reference value V 3 is the input x 6 (voltage V 6 ), the capacitor 20 (capacitance value C 2 ), and the resistor 21 (resistance value R 2 ).
The output x 5 (voltage V 5 ) of the inverter 5 is passed through a low-pass filter 3 consisting of a resistor 22 (resistance value
R 3 ). That is, after the signal is received and a steady state is reached, the reference reference value
V 3 becomes (V 6 P 3 +V 5 R 2 )/(R 2 +R 3 ). Here, as shown in FIG. 4a, the ideal comparison reference value is V c ,
Let the amplitude of the data signal be Vs. Suppose now that the signal continues to be at a high level for some time, as shown in section T1 in FIG. 4a. In this case, the input signal
Since the voltage V 6 of x 6 is V c +V s , the reference value V 3 is {V c
R 3 / (R 2 + R 3 )} + {(V s R 3 + V 5 R 2 ) / (R 2 +
R 3 )}. Here, R 2 ≪ R 3 , V 5 = −V s R 3 /R 2
If V 3 V c is selected, the reference value V 3 will not deviate from the ideal comparison value V c even if high level signals continue. The above is a case where the signal continues to be at a high level, but the same applies to a case where the signal continues to be at a low level.
次に過渡応答について説明する。入力信号x6か
ら信号x3に対する伝達関数は次のようになる。 Next, the transient response will be explained. The transfer function from input signal x 6 to signal x 3 is as follows.
但し、s=jω(ωは信号の角周波数)であ
る。 However, s=jω (ω is the angular frequency of the signal).
同様に、出力信号x5から信号x3に対する伝達関
数は以下のようになる。 Similarly, the transfer function from output signal x 5 to signal x 3 is as follows.
つまり、いずれも1次の低域通過フイルタの応
答特性を示し、同じ時定数C2R2R3/(R2+R3)を
有する。すなわち、第3図の回路の場合、入力信
号x6から信号x3に対して充電する時定数と、出力
信号x5から信号x3に対して放電する時定数が等し
いため、第4図aの区間T1の初期の過渡的状態
についてもV3Vcが成立することを意味してい
る。 In other words, both exhibit the response characteristics of a first-order low-pass filter and have the same time constant C 2 R 2 R 3 /(R 2 +R 3 ). In other words, in the case of the circuit shown in Figure 3, the time constant for charging from the input signal x 6 to the signal x 3 is equal to the time constant for discharging from the output signal x 5 to the signal x 3 , so the circuit shown in Figure 4 a This means that V 3 V c also holds true for the initial transient state of interval T 1 .
以上説明して来た様に、信号を受信しある時間
経過後には、入力信号が高レベルあるいは低レベ
ルと続いても、比較基準値x3は理想比較基準値を
保てるので、時定数R2C2は小さく選べる。ま
た、このことは信号受信の初めに基準値x3が理想
比較基準値Vcへ達する時間も早くなることを意
味する。 As explained above, after a certain period of time has passed after receiving a signal, the comparison reference value x 3 can maintain the ideal comparison reference value even if the input signal continues to be at a high or low level, so the time constant R 2 C 2 can be chosen small. This also means that the time required for the reference value x 3 to reach the ideal comparison reference value V c at the beginning of signal reception also becomes faster.
第5図は本発明の第2の実施例である。入力信
号x7(電圧V7)は低域通過フイルタ9(増幅器1
2、抵抗器24,25(抵抗値R4,R5)およびコ
ンデンサ23(容量値C4)で構成される。)に供
給される。また、比較器8の出力は利得が負の低
域通過フイルタ10(増幅器11、抵抗器27〜
29(抵抗値R6〜R8)およびコンデンサ26(容
量値C3)で構成される。)に供給される。比較基
準値V9は低域通過フイルタ9および10のそれ
ぞれの出力電圧を合成したものである。従つて、
第5図の増幅器11,12のそれぞれの出力
x11,x12の電圧V11,V12に対して基準値V9はV9=
(V11R5+V12R6)/(R5+R6)と表わされる。そこ
で、第4図aの区間T1のように一定電圧が続い
たときは定常状態に達すると、V12=Vc+Vsが
成立するため、このとき基準値V9は、V9={Vc
R6/(R5+R6)}+{(V11R5+VsR6)/(R5+
R6)}
と表わされる。従つて、V11=−VsR6/R5が成立
するように抵抗R5,R6および電圧V11を選び、R5
≪R6とすると、V9Vcが成立して、定常状態で
は理想比較値を保つことが可能である。 FIG. 5 shows a second embodiment of the invention. The input signal x 7 (voltage V 7 ) is passed through the low-pass filter 9 (amplifier 1
2. It is composed of resistors 24 and 25 (resistance values R 4 and R 5 ) and a capacitor 23 (capacitance value C 4 ). ). In addition, the output of the comparator 8 is passed through a low-pass filter 10 (amplifier 11, resistor 27 to
29 (resistance values R 6 to R 8 ) and a capacitor 26 (capacitance value C 3 ). ). The comparison reference value V 9 is a combination of the respective output voltages of the low-pass filters 9 and 10 . Therefore,
The respective outputs of amplifiers 11 and 12 in FIG.
For the voltages V 11 and V 12 of x 11 and x 12 , the reference value V 9 is V 9 =
It is expressed as (V 11 R 5 +V 12 R 6 )/(R 5 +R 6 ). Therefore, when a constant voltage continues as in section T 1 in Figure 4a, when a steady state is reached, V 12 = V c + V s holds, so the reference value V 9 at this time is V 9 = { V c
R 6 / (R 5 + R 6 )} + {(V 11 R 5 + V s R 6 ) / (R 5 +
R 6 )}. Therefore, resistors R 5 and R 6 and voltage V 11 are selected so that V 11 = −V s R 6 /R 5 is established, and R 5
If <<R 6 , then V 9 V c holds true and it is possible to maintain the ideal comparison value in a steady state.
次に過渡応答について説明する。入力信号x7の
電圧V7が変化したときのx12の電圧V12の応答は、
と表わされ、時定数はC4R4である。 Next, the transient response will be explained. The response of the voltage V 12 of x 12 when the voltage V 7 of input signal x 7 changes is: It is expressed as , and the time constant is C 4 R 4 .
次に、出力信号x8の電圧V8が変化したときの
x11の電圧V11の応答は、
−増幅器11の帰還インピーダンス/X3より増幅器11の反転入力までのインピーダンス=−1/R8−{R7
1/sC3/R7+1/sC3}=R7/R8 −1/1+sC3R7
と表わされて、時定数はC3R7である。 Next, when the voltage V 8 of the output signal x 8 changes
The response of the voltage V 11 of x 11 is - Feedback impedance of amplifier 11 /
1/ sC3 / R7 +1/ sC3 }= R7 / R8-1 /1+ sC3R7 , and the time constant is C3R7 .
定常状態でV9Vcが成立する場合、両時定数
C4R4とC3R7が等しければ、信号x9の電圧は低域
通過フイルタ9を通して立上ろうとする電圧と低
域通過フイルタ10を通して立下げようとする電
圧が等しく均合うため、入力信号の過渡状態にお
いても理想比較値を保つことが可能である。この
場合においても時定数R4C4は小さく選ぶことが
出来るので、信号受信の初めに比較基準値V9が
理想比較値へ達するのを早くすることが出来る。 If V 9 V c holds in steady state, both time constants
If C 4 R 4 and C 3 R 7 are equal, the voltage of the signal It is possible to maintain the ideal comparison value even in a transient state of the signal. Even in this case, the time constant R 4 C 4 can be selected to be small, so that the comparison reference value V 9 can quickly reach the ideal comparison value at the beginning of signal reception.
第6図は本発明の第3の実施例で、第3図にさ
らにダイオードD1,D2を追加したものである。
ダイオードD1,D2の飽和電圧は入力信号の振幅
電圧Vsよりわずかだけ高めに選ばれる。このと
きには、信号を受信ししばらくたつた後には本発
明第3図の場合と同様の特性を有するが、信号受
信の初めに入力信号x13の振幅が電圧Vs以上に立
ち上がるが、または立ち下がるかすると、ダイオ
ードD1,D2のいずれかが導通する。このため比
較基準信号x15の電圧V15は非常に短かい時間で理
想基準比較値Vcに達することが出来る。なお、
第3図および第6図において、比較器4および1
6の極性を逆にして用いれば、反転器5および1
7は不要となる。 FIG. 6 shows a third embodiment of the present invention, in which diodes D 1 and D 2 are further added to FIG. 3.
The saturation voltage of the diodes D 1 and D 2 is chosen to be only slightly higher than the amplitude voltage V s of the input signal. In this case, after a while after receiving the signal, the characteristics are similar to those in the case shown in FIG. 3 of the present invention, but at the beginning of signal reception, the amplitude of the input signal When this occurs, either diode D 1 or D 2 becomes conductive. Therefore, the voltage V 15 of the comparison reference signal x 15 can reach the ideal reference comparison value V c in a very short time. In addition,
In FIGS. 3 and 6, comparators 4 and 1
If the polarity of 6 is reversed, inverters 5 and 1
7 becomes unnecessary.
以上説明したように、本発明の比較回路を用い
れば、信号パターンとして高レベルまたは低レベ
ルが連続する信号も理想基準値で比較が可能であ
り、また信号に直流レベルが同時に加わつて受信
される場合にも理想比較状態に達するのが早い。 As explained above, by using the comparison circuit of the present invention, it is possible to compare signals with continuous high or low levels as a signal pattern using an ideal reference value, and also to receive signals with a DC level added to them at the same time. In some cases, the ideal comparison state is reached quickly.
第1図は従来の比較回路の概略回路図、第2図
a,bは第1図の比較回路の動作タイムチヤー
ト、第3図は本発明の第1の実施例、第4図a〜
cは第3図の回路の動作タイムチヤート、第5図
は本発明の第2の実施例、第6図は本発明の第3
の実施例、第7図a〜cは第6図の回路の動作タ
イムチヤート、なお図において1,3,9,1
0,15……低域通過フイルタ、2,4,8,1
1,12,16……比較器、5,17……反転
器、である。
FIG. 1 is a schematic circuit diagram of a conventional comparison circuit, FIGS. 2a and 2b are operation time charts of the comparison circuit in FIG. 1, FIG. 3 is a first embodiment of the present invention, and FIGS.
c is an operation time chart of the circuit in FIG. 3, FIG. 5 is a second embodiment of the present invention, and FIG. 6 is a third embodiment of the present invention.
FIGS. 7a to 7c are operation time charts of the circuit in FIG.
0,15...Low pass filter, 2,4,8,1
1, 12, 16...comparators, 5, 17...inverters.
Claims (1)
ら非反転および反転入力端子間の電圧を比較する
比較器と、直流成分に信号成分が重量した入力信
号を受けかつ前記非反転入力端子に接続された信
号入力端子と、前記信号成分の変化する時間に比
べて十分大きな時定数を持ち、前記信号入力端子
と前記反転入力端子との間に接続された第1の低
域通過フイルタと、前記比較器の出力と前記反転
入力端子との間に挿入された負帰還手段とを含
み、定常状態で前記反転入力端子への入力電圧が
前記信号成分の中央電圧となり、かつ前記信号入
力端子の電圧が変化したときに前記第1の低域通
過フイルタを通して前記反転入力端子に得られる
電圧の過渡応答と、前記比較器出力の電圧が変化
したときに前記負帰還手段を通して前記反転入力
端子に得られる電圧の過渡応答とが等しくなるよ
うに、前記第1の低域通過フイルタ及び負帰還手
段の応答特性を設定したことを特徴とする比較回
路。 2 前記負帰還手段を信号極性反転手段および抵
抗器で構成したことを特徴とする特許請求の範囲
第1項記載の比較回路。 3 前記負帰還手段を第2の低域通過フイルタで
構成したことを特徴とする特許請求の範囲第1項
記載の比較回路。 4 前記第1の低域通過フイルタをコンデンサと
抵抗器とで構成したことを特徴とする特許請求の
範囲第1項記載の比較回路。 5 前記第1の低域通過フイルタをコンデンサと
抵抗器と、この抵抗器に並列にかつ互いに逆極性
となるよう接続された1対のダイオードとで構成
したことを特徴とする特許請求の範囲第1項記載
の比較回路。[Scope of Claims] 1. A comparator that has a non-inverting input terminal and an inverting input terminal and compares voltages between the non-inverting and inverting input terminals, and a comparator that receives an input signal in which the signal component is heavy on the DC component, and a signal input terminal connected to the non-inverting input terminal; and a first low voltage terminal connected between the signal input terminal and the inverting input terminal and having a sufficiently large time constant compared to the time at which the signal component changes. a pass filter, and negative feedback means inserted between the output of the comparator and the inverting input terminal, the input voltage to the inverting input terminal being the center voltage of the signal component in a steady state, and The transient response of the voltage obtained at the inverting input terminal through the first low-pass filter when the voltage at the signal input terminal changes, and the voltage transient response obtained at the inverting input terminal through the first low-pass filter when the voltage at the comparator output changes, A comparison circuit characterized in that the response characteristics of the first low-pass filter and the negative feedback means are set so that the transient response of the voltage obtained at the inverting input terminal is equal. 2. The comparison circuit according to claim 1, wherein the negative feedback means is comprised of a signal polarity inversion means and a resistor. 3. The comparison circuit according to claim 1, wherein the negative feedback means is constituted by a second low-pass filter. 4. The comparison circuit according to claim 1, wherein the first low-pass filter is composed of a capacitor and a resistor. 5. Claim 5, characterized in that the first low-pass filter is constituted by a capacitor, a resistor, and a pair of diodes connected to the resistor in parallel and with opposite polarities. Comparison circuit described in item 1.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2636778A JPS54118148A (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
US06/018,396 US4339727A (en) | 1978-03-07 | 1979-03-07 | Waveform converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2636778A JPS54118148A (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54118148A JPS54118148A (en) | 1979-09-13 |
JPS6253967B2 true JPS6253967B2 (en) | 1987-11-12 |
Family
ID=12191520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2636778A Granted JPS54118148A (en) | 1978-03-07 | 1978-03-07 | Comparator circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54118148A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125175U (en) * | 1988-02-19 | 1989-08-25 | ||
JP2010057014A (en) * | 2008-08-29 | 2010-03-11 | Sumitomo Electric Device Innovations Inc | Electronic circuit |
JP2010185770A (en) * | 2009-02-12 | 2010-08-26 | Seiko Instruments Inc | Apparatus for detection of moving direction |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57208780A (en) * | 1981-06-18 | 1982-12-21 | Pioneer Electronic Corp | Wave shaping circuit |
JPS59137639U (en) * | 1983-03-02 | 1984-09-13 | 竹中エンジニアリング工業株式会社 | Comparator circuit |
JP2571683B2 (en) * | 1986-06-12 | 1997-01-16 | アルプス電気株式会社 | Signal amplification circuit of code reader |
JPS6418311A (en) * | 1987-07-14 | 1989-01-23 | Komatsu Mfg Co Ltd | Optical reception circuit |
JPH07118726B2 (en) * | 1987-08-31 | 1995-12-18 | 株式会社小松製作所 | Comparison device |
JPH01156819A (en) * | 1987-12-15 | 1989-06-20 | Matsushita Electric Ind Co Ltd | Bar code detector |
JP5718596B2 (en) | 2010-08-05 | 2015-05-13 | ジーブイビービー ホールディングス エス.エイ.アール.エル. | Reception circuit, signal transmission circuit, and signal reception method |
-
1978
- 1978-03-07 JP JP2636778A patent/JPS54118148A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125175U (en) * | 1988-02-19 | 1989-08-25 | ||
JP2010057014A (en) * | 2008-08-29 | 2010-03-11 | Sumitomo Electric Device Innovations Inc | Electronic circuit |
JP2010185770A (en) * | 2009-02-12 | 2010-08-26 | Seiko Instruments Inc | Apparatus for detection of moving direction |
Also Published As
Publication number | Publication date |
---|---|
JPS54118148A (en) | 1979-09-13 |
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