JPS6152021A - Squelch circuit - Google Patents

Abstract

PURPOSE:To prevent mis-output due to noise by applying a DC voltage to a differential comparator when no digital signal arrives between input terminals. CONSTITUTION:A digital signal arriving between input terminals 1, 2 from a 2- wire transmission line (not shown) is inputted to a differential comparator 4 via a pulse transformer 3 and resistors 11, 12. Then a digital signal subjected to waveform shaping is outputted between output terminals 9, 10. When no digital arrives, a transistor (TR) 16 connected between an input terminal 5 of the comparator 4 and a power supply VEE is conductive and a DC voltage is fed to the comparator 4. When the digital signal arrives, the level of a comparator 18 goes to high one and a TR17 is conducted, then the TR16 is nonconductive and only the digital signal is inputted to the comparator 4. When no digital signal arrives, mis-output due to noise is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a squelch circuit provided in a circuit for waveform shaping a digital signal arriving from a two-wire transmission line.

When a digital signal that serially transmits binary information using two types of signal levels is transmitted via a long two-wire transmission line, the amplitude of the digital signal is attenuated and the waveform is also distorted. In order to faithfully extract binary information from such digital signals, a waveform shaping circuit is provided on the receiving side. However, this type of waveform shaping circuit must not erroneously shape and output line noise etc. when no digital signal arrives from the two-wire transmission line.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional waveform shaping circuit of this kind.

In FIG. 4, a digital signal arriving between input terminals 1 and 2 from a two-wire transmission line (not shown) is transmitted to an inverting input terminal 5 and a non-inverting input terminal 6 of a differential comparator 4 via a pulse transformer 3. is input.

The resistors 7 and 8 terminate the pulse transformer 3 with a resistance value equal to the characteristic impedance of the two-wire transmission line, and provide a dark value voltage V from the midpoint to the inverting input terminal 5 and the non-inverting input terminal 6. supply.

In such a state, when a digital signal arrives between input terminals 1 and 2, the differential comparator 4 converts the digital signal input between the inverting input terminal 5 and the non-inverting input terminal 6 with the dark value voltage VIIB as the center voltage into a waveform. The waveform-shaped digital signal is output between output terminals 9 and 10.

Note that if a digital signal does not arrive between input terminals 1 and 2, the voltage level output from differential comparator 4 between output terminals 9 and 10 will be undefined. This may amplify the noise voltage and cause the voltage level between output terminals 9 and 10 to fluctuate.

[Problem to be Solved by the Invention 3] As is clear from the above explanation, in a conventional waveform shaping circuit, when a digital signal does not arrive between the input terminals, the voltage level output from the output terminal becomes unstable. , for example, may vary due to line noise, etc.

[Means for solving problems]

The problem is that in a circuit that inputs a serial binary digital signal arriving from a two-wire transmission line to a differential comparator and shapes the waveform, the resistor inserted in series with both input terminals of the differential comparator and a first means for supplying a DC bias current to one of the resistors via a current switching element, detecting a digital signal arriving at the differential comparator, and switching the current switching while the digital signal continues. and second means for setting the element to a cut-off state.

[Effect]

That is, according to the present invention, when a digital signal does not arrive, a DC bias current is supplied from the first means to the one resistor, and the DC bias current is applied to the resistor between both input terminals of the differential comparator. The DC voltage generated at both ends is constantly applied, and the voltage level output from the differential comparator is maintained at a constant value. When a digital signal arrives at the differential comparator in this state, the digital signal and the DC voltage are superimposed and input to the differential comparator, causing distortion to the waveform shaping of the differential comparator. Become.

In order to eliminate this influence, the second means detects the arriving digital signal and blocks the current switching element of the first means to block the DC bias current while the digital signal continues.

As a result, no DC voltage is generated across the resistor, and only the arriving digital signal is input to the differential comparator, and the differential comparator performs normal waveform shaping.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a receiving circuit according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, in addition to the receiving circuit shown in FIG.
Resistors 11 to 14, capacitor 15, transistor 15
and 17, a squelch circuit composed of an emitter output differential comparator and a diode 19. Resistors 11 and 12 are resistors inserted in series with the inverting input terminal 5 and non-inverting input terminal 6 of the differential comparator 4, and the resistor 13 and the transistor 16, which is a current switching element, constitute the first means. , the emitter output J differential comparator 18, the resistor 14, the capacitor 15, the transistor 17 and the diode 19 constitute the second means.

In FIG. 1, when a voltage close to the dark value voltage V0 is applied to the base of the transistor 16 and the transistor 16 is in a conductive state, a negative voltage ■ is applied. A DC bias current I flows from the resistor 13 through the resistor 13, the transistor 16, the resistor 11.7.8, and the pulse transformer 3, and a DC voltage (hereinafter referred to as bias voltage 8) is generated across the resistor 11. If no digital signal has arrived between input terminals 1 and 2, a dark value voltage ■ appears at the inverting input terminal 20 of the emitter output differential comparator 18 via the resistors 8 and 12. (Resistors 7 and 8 are set sufficiently small compared to resistors 11 and 12), but the non-inverting input terminal 2
1 is applied with a dark value voltage ■, and a DC voltage lowered by approximately bias voltage ■8. That is, the bias voltage (2) is applied between the inverting input terminal 20 and the non-inverting input terminal 21. As a result, the emitter output differential comparator 18
is a negative voltage■. Voltage level close to (hereinafter referred to as low voltage level ■L)
Since the base current is not supplied to the transistor 17, the transistor 17 is cut off, and the transistor 16 remains conductive. In this state, the bias voltage ■ is also input between the inverting input terminal 5 and the non-inverting input terminal 6 of the differential comparator 4, and the voltage level output between the output terminals 9 and 10 is also maintained at a predetermined value. be done. Even if line noise etc. arrives between input terminals 1 and 2 in a biased state, the voltage level output from the differential comparator 4 will not fluctuate unless the noise voltage cancels the bias voltage 8. .

When a digital signal arrives between input terminals 1 and 2 in this state, the digital signal is input between the inverting input terminal 20 and the non-inverting input terminal 21 of the emitter output differential comparator 18, superimposed on the bias voltage ■1. be done. The digital signal has a signal level with the same polarity as the bias voltage vII (
The voltage level output by the emitter output differential comparator 18 does not change when the digital signal indicates a signal level (hereinafter referred to as the first signal level) with the opposite polarity to the bias voltage ■8 (hereinafter referred to as the second signal level). When the signal level is high (hereinafter referred to as high voltage level VH), the emitter output differential comparator 18 outputs a voltage level close to the threshold voltage Vla (hereinafter referred to as high voltage level VH). The emitter output differential comparator 18 exhibits low output impedance when changing from low voltage level ■ to high voltage level VH, and conversely when changing from high voltage level ■8 to low voltage level ■L. indicates high output impedance. Therefore, when the emitter output differential comparator 18 changes from the low voltage level V to the high voltage level Vl+, the capacitor 15 is rapidly charged by the difference voltage between the low voltage level 2 and the high voltage level VH. The base current is supplied to the transistor 17 via the diode 19, and the transistor 17 is in a 4-way state, and from the negative voltage 1, the resistor 1
3 and transistor 17, a direct current approximately equal to the direct current bias current I flows. As a result, the transistor 16 is set to a cutoff state, and the DC bias current I is no longer supplied to the resistor 11. As a result, differential comparator 4 (
Only digital signals are input to the emitter output differential comparator 18), maintaining the same waveform shaping function as in FIG. Note that the digital signal is
When the signal level changes from the first signal level to the first signal level and the emitter output differential comparator 18 changes from the high voltage level ■8 to the low voltage level VL, the emitter output differential comparator 18 exhibits a high output impedance. , the electric charge stored in the capacitor 15 is discharged through the resistor 14. If the time constant of the time constant circuit consisting of the resistor 14i8 and the capacitor 15 is set to be long enough, the digital signal changes from the first signal level to the second signal level again.
Until the emitter output differential comparator 18 again outputs the high voltage level 8, the base current is supplied to the transistor 17 from the time constant circuit, the transistor 17 maintains the conducting state, and the transistor 16 remains in the cut-off state. maintain.

As a result, while the digital signal is arriving, the DC bias current I is not supplied to the resistor 11, and the differential comparator 4 performs waveform shaping similar to that shown in FIG.

However, in FIG. 1, immediately after the power is turned on, and before the DC bias current I starts flowing, the inverting input terminal 20 and the non-inverting input terminal 21 of the emitter output differential comparator 18
A noise voltage is input between the differential comparators 18 and 18.
When outputs the high voltage level V11, the transistor 1 is activated in the above process for a period determined by the time constant of the time constant circuit.
7 becomes conductive, and the DC bias current {circle around (2)} is no longer supplied to the resistor 11. During this period, the output voltage level of the differential comparator 4 may fluctuate due to human input line noise, etc., as in FIG.

FIG. 2 is a diagram showing a receiving circuit according to another embodiment of the present invention, which solves the above-mentioned problems in FIG. 1. In FIG. 2, resistors 22 to 25 are added to the squelch circuit in FIG. 1.

In Figure 2, when the power is turned on, the positive voltage VCC
Dark value voltage through resistor 22.23.12 and 8 from ■
. DC current flows through the resistor 7 from the dark value voltage V11B.
．． A direct current flows through 11.25 and 24 to the negative voltage VEE. As a result, a DC voltage due to the DC current is input between the inverting input terminal 20 and the non-inverting input terminal 21 of the emitter output differential comparator 18, and the emitter output differential comparator 18 is at low voltage level (1), Outputs
The capacitor 15 is in a discharged state, no base current is supplied to the transistor 17, the transistor 17 is maintained in a cut-off state, and the transistor 16 is set in a conductive state, so that a DC bias current ■ always flows, as shown in FIG. The fear that the DC bias current I will stop flowing is eliminated.

Similar to FIG. 2, FIG. 3 is a diagram showing a receiving circuit according to another embodiment of the present invention, which solves the problems described in FIG. 1. In FIG. 3, in addition to the squelch circuit in FIG. 1, resistors 26 to 29 and capacitors 30 and 3
1 is added.

Also in Figure 3, positive voltage ■. C to resistors 26 and 2
A direct current flows through 7, and a negative voltage v! Resistance 28 to E
A direct current flows through and 29.

As a result, as in FIG. 2, as soon as the power is turned on, a DC voltage is input between the inverting input terminal 20 and the non-inverting input terminal 21 of the emitter output differential comparator 18, the transistor 17 is in the cut-off state, and the transistor 16 is in the cut-off state. A conductive state is established, and the DC bias current I is always supplied to the resistor 11.

As is clear from the above description, according to this embodiment, when a digital signal does not arrive, the DC bias current I is supplied to the resistor 11, and the bias voltage
8 is input between the inverting input terminal 5 and the non-inverting input terminal 6 of the differential comparator 4, and maintains the voltage level output between the output terminals 9 and 10 at a predetermined value, and prevents fluctuations in the voltage level due to line noise, etc. This makes it possible to prevent

〔Effect of the invention〕

As described above, according to the present invention, in the receiving circuit, when a digital signal does not arrive from the two-wire transmission line, the voltage level output from the differential comparator is prevented from fluctuating due to line noise, etc., and the voltage level output from the differential comparator is stabilized. Waveform shaping becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a waveform shaping circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing a waveform shaping circuit according to another embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 4 is a diagram showing an example of a conventional waveform shaping circuit. In the figure, 1 and 2 are input terminals, 3 is a pulse transformer, 4 is a differential comparator, 5 and 20 are inverting input terminals, 6 and 21 are non-inverting input terminals, 7.11 to 14 and 2
2 to 29 are resistors, 9 and 10 are output terminals, 15
．． 30 and 31 are capacitors, 16 and 17 are transistors, 19 is a diode, ■ is a DC bias current,
(2) 8 represents a bias voltage, VBB represents a threshold voltage, VCC represents a positive voltage, and VEE represents a negative voltage. Question 4

Claims (2)

[Claims] (1) In a circuit that inputs a serial binary digital signal arriving from a two-wire transmission line to a differential comparator and performs waveform shaping, a resistor inserted in series to both input terminals of the differential comparator; a first means for supplying a DC bias current to one of the resistors via a current switching element; detecting a digital signal arriving at the differential comparator; and detecting a digital signal arriving at the differential comparator; and second means for setting the squelch circuit to a cutoff state. (2) The second means connects both input terminals in parallel to both input terminals of the differential comparator, and the digital signal arriving at the two input terminals changes from a first signal level to a second signal level. Low output impedance, when the level changes, the second
an emitter output differential comparator that exhibits high output impedance when the signal level changes from the signal level to the first signal level; and a period during which the emitter output differential comparator is connected to the output of the emitter output differential comparator and the digital signal is input. a time constant circuit that holds the voltage level output by the emitter output differential comparator; and while the time constant circuit holds the voltage level, it is supplied with a base current from the time constant circuit and becomes conductive; 2. The squelch circuit according to claim 1, further comprising a transistor for setting the switching element to a cutoff state.