JPS6224966B2 - - Google Patents

Info

Publication number
JPS6224966B2
JPS6224966B2 JP53026368A JP2636878A JPS6224966B2 JP S6224966 B2 JPS6224966 B2 JP S6224966B2 JP 53026368 A JP53026368 A JP 53026368A JP 2636878 A JP2636878 A JP 2636878A JP S6224966 B2 JPS6224966 B2 JP S6224966B2
Authority
JP
Japan
Prior art keywords
voltage
signal
input terminal
comparator
comparison
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53026368A
Other languages
Japanese (ja)
Other versions
JPS54118149A (en
Inventor
Ikuo Yoshida
Gozo Kage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2636878A priority Critical patent/JPS54118149A/en
Priority to US06/018,396 priority patent/US4339727A/en
Publication of JPS54118149A publication Critical patent/JPS54118149A/en
Publication of JPS6224966B2 publication Critical patent/JPS6224966B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H03K5/086Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003Changing the DC level
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)

Description

【発明の詳細な説明】 本発明はデータ信号の再生に用いる比較回路に
関し、特にデータ信号に含まれる低周波成分の影
響による比較基準値のずれを補償した比較回路に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit used for reproducing data signals, and more particularly to a comparison circuit that compensates for deviations in comparison reference values due to the influence of low frequency components contained in data signals.

従来、データ通信における受信系では比較回路
でのデータ信号の再生に際し、基準電圧とデータ
信号電圧との電圧比較をするのに、何らかの方法
により直流成分を除去している。この直流成分の
除去には通常コンデンサ等の過渡応答素子を用い
ている。このため、データ信号としてNRZ(Non
―Return to Zero)方式を用いた場合、データ
信号が高レベルで連続すると、コンデンサの過渡
応答によつて比較器へのデータ信号入力がゼロレ
ベルへ落ちてしまい、比較不能となりデータ再生
ができなくなる。この対応策として従来は、大容
量のコンデンサを用いてデータ信号中の低い周波
数成分まで通過させるとか、データ信号自体に低
周波成分を持たないよう何らかの処理を施す等の
策を構じている。これらの処置は十分正確なデー
タ信号の再生ができない。また装置の構造が複雑
になる等の欠点を含んでいる。
BACKGROUND ART Conventionally, in a data communication receiving system, when a comparison circuit reproduces a data signal, a DC component is removed by some method when comparing a reference voltage and a data signal voltage. A transient response element such as a capacitor is usually used to remove this DC component. Therefore, NRZ (Non
-Return to Zero) method, if the data signal continues to be at a high level, the data signal input to the comparator will drop to zero level due to the transient response of the capacitor, making comparison impossible and data reproduction impossible. . Conventionally, countermeasures for this problem include using a large-capacity capacitor to pass even low-frequency components in the data signal, or performing some kind of processing so that the data signal itself does not contain low-frequency components. These procedures do not allow sufficiently accurate reproduction of the data signal. It also has drawbacks such as a complicated structure of the device.

本発明の目的はこれらの欠点を除去した比較回
路を提供するものである。
An object of the present invention is to provide a comparator circuit that eliminates these drawbacks.

本発明によれば、高域通過フイルタ(以下
HPFという)と、比較信号入力端子と基準電圧
信号入力端子とを有しこれら2端子への入力信号
の電圧比較をする比較器と、HPFの出力と比較
信号入力端子との間に接続したリミツタと、比較
器の出力と比較信号あるいは基準電圧信号入力端
子との間に挿入した帰還手段とを含む比較回路が
得られる。
According to the invention, a high-pass filter (hereinafter referred to as
HPF), a comparator that has a comparison signal input terminal and a reference voltage signal input terminal and compares the voltages of the input signals to these two terminals, and a limiter connected between the output of the HPF and the comparison signal input terminal. and feedback means inserted between the output of the comparator and the comparison signal or reference voltage signal input terminal.

以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.

第1図は従来のデータ信号再生用の比較回路の
概略回路図であり、第2図a,bはその動作タイ
ムチヤートである。この比較回路をFM受信機に
用いた場合、信号電界が受信機に入力されると、
送信側周波数pに対して受信機の受信中心周波
数はある周波数分(Δ)だけずれるため、比較
回路前段にある周波数弁別回路で周波数Δに相
当する直流成分が発生する。この直流成分がデー
タ信号に加算される。例えば、第2図aのxp
ような波形となる。但し、ここで第2図は時間t
pに信号を受信した場合を示している。コンデン
サ10(容量値C1)、抵抗器11(抵抗値R1)か
らなるHPF1を通過した入力データ信号xp(電
圧Vp)は、瞬間的にデータ信号の平均電圧Vc
達するが、しだいに減少してゼロレベルに戻る。
ここでの時定数C1R1は、直流電圧Vcを除去する
と同時にデータ信号の低周波成分は通過させなけ
ればならないので、ある程度大きくせざるを得な
い。このことにより、データ信号が比較基準値ゼ
ロレベルに再び戻る間(第2図aの区間Tp)、比
較器2は正しい比較をしない。また、データ信号
が高レベルで連続する区間(第2図aの区間
T1)では、比較器2への入力信号は第2図aの信
号x1(電圧V1)のごとく低レベルへ落ちてしま
い、正しいデータ再生がなされない。誤つたデー
タ再生の様子は第2図bに示されている。
FIG. 1 is a schematic circuit diagram of a conventional comparison circuit for reproducing data signals, and FIGS. 2a and 2b are operation time charts thereof. When this comparison circuit is used in an FM receiver, when the signal electric field is input to the receiver,
Since the receiving center frequency of the receiver deviates by a certain frequency (Δ) with respect to the transmitting side frequency p , a DC component corresponding to the frequency Δ is generated in the frequency discrimination circuit located before the comparison circuit. This DC component is added to the data signal. For example, the waveform becomes x p in FIG. 2a. However, here in Figure 2, time t
This shows the case where a signal is received at p . The input data signal x p (voltage V p ) that has passed through the HPF 1 consisting of the capacitor 10 (capacitance value C 1 ) and the resistor 11 (resistance value R 1 ) momentarily reaches the average voltage V c of the data signal, but It gradually decreases and returns to zero level.
The time constant C 1 R 1 here has to be increased to some extent because it is necessary to remove the DC voltage V c and at the same time pass the low frequency component of the data signal. As a result, the comparator 2 does not perform a correct comparison while the data signal returns to the zero level of the comparison reference value (section T p in FIG. 2a). In addition, a section in which the data signal continues at a high level (section a in Figure 2)
At T 1 ), the input signal to the comparator 2 falls to a low level like the signal x 1 (voltage V 1 ) in FIG. 2a, and correct data reproduction cannot be performed. The situation of erroneous data reproduction is shown in FIG. 2b.

第3図は本発明による比較回路の一実施例であ
り、第4図a,bはその動作タイムチヤートであ
る。振幅電圧VDの入力データ信号x6(電圧V6
は、コンデンサ12(容量値C2)、抵抗器13
(抵抗値R2)よりなるHPF3を通過し直流成分を
カツトされる。HPF3の出力はリミツタ(ダイ
オードX1,X2よりなる)4により、ダイオード
の順方向電圧VD以上とならないように制限され
る。リミツタ4を通過した信号は比較器5により
比較基準電圧(ゼロレベル)と比較される。比較
器5は、x5>0ではx4=+Vccを出力し、x5<0
ではx4=―Vccを出力するものとする。いま、の
出力x4の電圧をVccとすれば、電圧Vccで比較器
の出力は抵抗器14(抵抗値R3を介して非反転
入力端子へ帰還される。
FIG. 3 shows an embodiment of the comparator circuit according to the present invention, and FIGS. 4a and 4b are operation time charts thereof. Input data signal x 6 with amplitude voltage V D (voltage V 6 )
are capacitor 12 (capacitance value C 2 ), resistor 13
(resistance value R 2 ), and the DC component is cut off. The output of the HPF 3 is limited by a limiter 4 (consisting of diodes X 1 and X 2 ) so that it does not exceed the forward voltage V D of the diodes. The signal passing through the limiter 4 is compared with a comparison reference voltage (zero level) by a comparator 5. Comparator 5 outputs x 4 =+V cc when x 5 >0, and outputs x 4 =+V cc when x 5 <0.
Now, assume that x 4 =-V cc is output. Now, if the voltage of the output x 4 is Vcc , the output of the comparator at the voltage Vcc is fed back to the non-inverting input terminal via the resistor 14 (resistance value R3 ) .

このときの応答は次のようになる。 The response in this case is as follows.

ここで、s=jω(ωは信号の角周波数)であ
る。
Here, s=jω (ω is the angular frequency of the signal).

これは1次の低域通過フイルタの応答特性を示
し、時定数はC2R2R3/(R2+R3)となる。但し、
計算を容易にするため、比較回路の入力点から見
た比較回路の前段回路の抵抗値はR00とし
た。
This shows the response characteristic of a first-order low-pass filter, and the time constant is C 2 R 2 R 3 /(R 2 +R 3 ). however,
To facilitate calculation, the resistance value of the preceding stage circuit of the comparison circuit as seen from the input point of the comparison circuit was set to R 0 0.

また、入力信号x6の電圧の変化による信号x5
電圧の応答は次のようになる。
Furthermore, the response of the voltage of the signal x 5 due to the change in the voltage of the input signal x 6 is as follows.

/(R+R)/1/sC+R/(
+R) =sC/(R+R)/1+sC
/(R+R) これは1次の高域通過フイルタの応答特性を示
し、時定数はC2R2R3/(R2+R3)となる。
R 2 R 3 /(R 2 +R 3 )/1/sC 2 +R 2 R 3 /(
R 2 +R 3 ) =sC 2 R 2 R 3 /(R 2 +R 3 )/1+sC 2 R 2
R 3 /(R 2 +R 3 ) This shows the response characteristic of a first-order high-pass filter, and the time constant is C 2 R 2 R 3 /(R 2 +R 3 ).

従つて、比較器出力から非反転入力端子へ帰還
する時定数と高域通過フイルタの入出力間の応答
による時定数は同じ値になる。すなわち、第4図
aの区間T1のごとく、入力信号x6が高レベルで
続いた時に、コンデンサ12を通過したデータ信
号の電圧の減少する時定数と、比較器5の出力x4
を抵抗器14を介して帰還した信号の電圧の増加
する時定数とが等しい。この現象は、信号が負の
方向で一定状態が続く場合も全く同様であり、こ
のときは信号x4から信号x5への帰還と、信号x6
対する信号x5の応答は同じ応答特性で変化し、信
号x5の電圧はV5=―VccR2/(R2+R3)に達す
る。従つて、信号の正方向、負方向いずれの場合
も、従来の比較回路が有していた比較器のデータ
信号入力部での電圧のゼロレベル落下を防止でき
る。また、この比較回路はリミツタ4のダイオー
ドX1,X2によつてデータ信号の直流成分Vcをカ
ツトし、信号入力時の過渡応答による誤比較を防
止している。例えば、正方向電圧Vcが信号に加
わると、ダイオードX1が導通し比較器5の入力
電圧V5は電圧VD以上には上がらない。このとき
ダイオードの導通時の抵抗値と、コンデンサ12
の容量値の積で決まる時定数が非常に小さいた
め、比較器5の入力電圧V5は電圧VD以内に急速
に引き込まれる。信号に負方向の電圧が加わつた
場合も、ダイオードX2が導通となり同様の結果
となる。
Therefore, the time constant fed back from the comparator output to the non-inverting input terminal and the time constant due to the response between the input and output of the high-pass filter have the same value. That is, when the input signal x 6 continues to be at a high level, as in section T 1 of FIG .
is equal to the increasing time constant of the voltage of the signal fed back through the resistor 14. This phenomenon is exactly the same when the signal remains constant in the negative direction; in this case, the feedback from signal x 4 to signal x 5 and the response of signal x 5 to signal x 6 have the same response characteristics. The voltage of the signal x 5 reaches V 5 =−V cc R 2 /(R 2 +R 3 ). Therefore, in both the positive direction and the negative direction of the signal, it is possible to prevent the voltage from dropping to zero level at the data signal input section of the comparator, which conventional comparison circuits have. Further, this comparator circuit cuts off the DC component Vc of the data signal by the diodes X 1 and X 2 of the limiter 4, thereby preventing erroneous comparison due to a transient response when the signal is input. For example, when a positive voltage V c is applied to the signal, the diode X 1 becomes conductive and the input voltage V 5 of the comparator 5 does not rise above the voltage V D. At this time, the resistance value when the diode is conductive and the capacitor 12
Since the time constant determined by the product of the capacitance values of is very small, the input voltage V5 of the comparator 5 is rapidly pulled within the voltage VD . When a negative voltage is applied to the signal, diode X2 becomes conductive and the same result occurs.

第5図は本発明による比較回路の他の実施例で
あり、第6図a,bはその動作タイムチヤートで
ある。入力信号x7はコンデンサ15(容量他
C6)、抵抗器16(抵抗値R6)よりなるHPFと、
ダイオードX3,X4よりなるリミツタとの回路6
で直流成分Vcをカツトされる。比較器7の入力
信号x8は第6図aのようになる。ここまでは、従
来と同様データ信号が高レベルまたは低レベルで
続くとHPFによつて、信号x8はゼロレベルに戻
つてしまう。この動作に対し、比較器7の出力x9
を符号反転器8、低域通過フイルタ(LPF)(コ
ンデンサ17、抵抗器18,19よりなる)9を
介して、反転入力端子へ負帰還させて補償してい
る。すなわち、HPFの出力x8がゼロレベルに近
づくにしたがつて、帰還信号x10の比較基準電圧
はHPFの出力x8と一定の電位差を保つように過
渡応答していく(第6図aに示す)。リミツタは
前述第3図の回路と同様の役割を果たす。
FIG. 5 shows another embodiment of the comparison circuit according to the present invention, and FIGS. 6a and 6b are operation time charts thereof. Input signal x 7 is capacitor 15 (capacitance etc.
C 6 ), a HPF consisting of a resistor 16 (resistance value R 6 ),
Circuit 6 with limiter consisting of diodes X 3 and X 4
The DC component V c is cut off. The input signal x8 of the comparator 7 is as shown in FIG. 6a. Up to this point, as in the conventional case, if the data signal continues to be at high or low level, the signal x8 returns to zero level by the HPF. For this operation, the output of comparator 7 x 9
is compensated by negative feedback to the inverting input terminal via a sign inverter 8 and a low-pass filter (LPF) 9 (consisting of a capacitor 17 and resistors 18 and 19). That is, as the HPF output x 8 approaches the zero level, the comparison reference voltage of the feedback signal x 10 responds transiently so as to maintain a constant potential difference with the HPF output x 8 (see Figure 6 a). show). The limiter plays the same role as the circuit shown in FIG. 3 above.

第5図において、反転器8を取り去り比較器7
の極性を逆にしても同様の動作をすることは明ら
かである。
In FIG. 5, the inverter 8 is removed and the comparator 7 is
It is clear that the same operation will occur even if the polarity of is reversed.

以上説明したように本発明によれば、直流成分
を含むデータ信号が入力されても過度応答による
誤比較を発生せず、またデータ信号が高レベルま
たは低レベルで連続しても誤比較を発生せず正し
いデータ再生可能な比較回路が得られる。
As explained above, according to the present invention, even if a data signal containing a DC component is input, erroneous comparison due to transient response does not occur, and even if the data signal is continuously at high or low level, erroneous comparison does not occur. Therefore, a comparator circuit that can reproduce correct data can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の比較回路の概略回路図、第2図
は第1図の回路の動作タイムチヤート、第3図は
本発明による比較回路の一実施例、第4図は第3
図の回路の動作タイムチヤート、第5図は本発明
による比較回路の他の実施例、第6図は第5図の
回路の動作タイムチヤートである。なお図におい
て、1,9……低域通過フイルタ、2,5,7…
…比較器、3……高域通過フイルタ、4……リミ
ツタ、6……高域通過フイルタおよびリミツタを
含む回路、8……符号反転器である。
FIG. 1 is a schematic circuit diagram of a conventional comparison circuit, FIG. 2 is an operation time chart of the circuit in FIG. 1, FIG. 3 is an embodiment of a comparison circuit according to the present invention, and FIG.
FIG. 5 is an operation time chart of the circuit shown in FIG. 5, another embodiment of the comparison circuit according to the present invention, and FIG. 6 is an operation time chart of the circuit shown in FIG. In the figure, 1, 9... low pass filter, 2, 5, 7...
. . comparator, 3 . . . high pass filter, 4 . . . limiter, 6 . . . circuit including a high pass filter and limiter, 8 . . . sign inverter.

Claims (1)

【特許請求の範囲】 1 直流成分に信号成分が重畳した入力信号を受
け前記直流成分をカツトする高域通過フイルタ
と、比較信号入力端子と基準電圧信号入力端子と
を有しこれら比較信号と基準電圧信号とを電圧比
較する比較器と、前記高域通過フイルタの出力と
前記比較信号入力端子との間に接続され第1の所
定電圧以下及びこの第1の所定電圧よりも高い第
2の所定電圧以上の電圧を制限するリミツタと、
前記比較器の出力と前記比較信号入力端子との間
に挿入された正帰還手段とを含み、前記高域通過
フイルタの入力電圧が変化したときに前記比較信
号入力端子に得られる電圧の過渡応答と、前記比
較器出力の電圧が変化したときに前記正帰還手段
を通して前記比較信号入力端子に得られる電圧の
過渡応答とが等しくなるように、前記高域通過フ
イルタ及び正帰還手段の応答特性を設定したこと
を特徴とする比較回路。 2 前記正帰還手段を抵抗器で構成したことを特
徴とする特許請求の範囲第1項記載の比較回路。 3 前記比較器の比較信号及び基準信号入力端子
がそれぞれ非反転及び反転入力端子であり、前記
正帰還手段を低域通過フイルタで構成したことを
特徴とする特許請求の範囲第1項記載の比較回
路。 4 直流成分に信号成分が重畳した入力信号を受
け前記直流成分をカツトする高域通過フイルタ
と、非反転入力端子と反転入力端子とを有しこれ
ら非反転および反転入力端子への入力信号を電圧
比較する比較器と、前記高域通過フイルタの出力
と前記非反転入力端子との間に接続され第1の所
定電圧以下及びこの第1の所定電圧より高い第2
の所定電圧以上の電圧を制限するリミツタと、前
記比較器の出力と前記反転入力端子との間に挿入
された負帰還手段とを含み、前記高域通過フイル
タの入力電圧が変化したときに前記非反転入力端
子に得られる電圧の過渡応答と、前記比較器出力
の電圧が変化したときに前記負帰還手段を通して
前記反転入力端子に得られる電圧の過渡応答とが
等しくなるように、前記高域通過フイルタ及び負
帰還手段の応答特性を設定したことを特徴とする
比較回路。 5 前記負帰還手段を信号極性反転手段および低
域通過フイルタとで構成したことを特徴とする特
許請求の範囲第4項記載の比較回路。 6 前記リミツタを互いに逆極性にかつ並列に接
続した1対のダイオードで構成したことを特徴と
する特許請求の範囲第1項又は第4項記載の比較
回路。
[Scope of Claims] 1. A high-pass filter that receives an input signal in which a signal component is superimposed on a DC component and cuts out the DC component, a comparison signal input terminal and a reference voltage signal input terminal, and includes a comparison signal input terminal and a reference voltage signal input terminal. a comparator that compares the voltage signal with a voltage signal; and a second predetermined voltage that is connected between the output of the high-pass filter and the comparison signal input terminal and is lower than or equal to a first predetermined voltage and higher than the first predetermined voltage. A limiter that limits the voltage above the voltage,
positive feedback means inserted between the output of the comparator and the comparison signal input terminal, the transient response of the voltage obtained at the comparison signal input terminal when the input voltage of the high-pass filter changes; The response characteristics of the high-pass filter and the positive feedback means are adjusted so that when the voltage of the comparator output changes, the transient response of the voltage obtained through the positive feedback means and the comparison signal input terminal are equal. A comparison circuit characterized by the following settings. 2. The comparison circuit according to claim 1, wherein the positive feedback means is constituted by a resistor. 3. The comparison according to claim 1, wherein the comparison signal and reference signal input terminals of the comparator are non-inverting and inverting input terminals, respectively, and the positive feedback means is constituted by a low-pass filter. circuit. 4 A high-pass filter that receives an input signal in which a signal component is superimposed on a DC component and cuts out the DC component, and has a non-inverting input terminal and an inverting input terminal, and inputs the input signal to the non-inverting and inverting input terminals to a voltage. a comparator for comparison, and a second predetermined voltage, which is connected between the output of the high-pass filter and the non-inverting input terminal, and which is lower than or equal to a first predetermined voltage and higher than the first predetermined voltage.
a limiter that limits a voltage above a predetermined voltage; and negative feedback means inserted between the output of the comparator and the inverting input terminal; the high frequency range so that the transient response of the voltage obtained at the non-inverting input terminal is equal to the transient response of the voltage obtained at the inverting input terminal through the negative feedback means when the voltage of the comparator output changes; A comparison circuit characterized in that response characteristics of a pass filter and a negative feedback means are set. 5. The comparator circuit according to claim 4, wherein the negative feedback means comprises signal polarity inversion means and a low-pass filter. 6. The comparator circuit according to claim 1 or 4, wherein the limiter is constituted by a pair of diodes connected in parallel with opposite polarities.
JP2636878A 1978-03-07 1978-03-07 Comparator circuit Granted JPS54118149A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2636878A JPS54118149A (en) 1978-03-07 1978-03-07 Comparator circuit
US06/018,396 US4339727A (en) 1978-03-07 1979-03-07 Waveform converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2636878A JPS54118149A (en) 1978-03-07 1978-03-07 Comparator circuit

Publications (2)

Publication Number Publication Date
JPS54118149A JPS54118149A (en) 1979-09-13
JPS6224966B2 true JPS6224966B2 (en) 1987-06-01

Family

ID=12191549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2636878A Granted JPS54118149A (en) 1978-03-07 1978-03-07 Comparator circuit

Country Status (1)

Country Link
JP (1) JPS54118149A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126318A (en) * 1983-01-08 1984-07-20 Fujitsu Ltd Clock regenerating circuit
JPS6118636U (en) * 1984-07-06 1986-02-03 アルプス電気株式会社 Waveform shaping circuit device
JPH0831783B2 (en) * 1987-06-12 1996-03-27 松下電器産業株式会社 Wave shaping circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5082963A (en) * 1973-11-05 1975-07-04
JPS5172253A (en) * 1974-12-20 1976-06-22 Hitachi Ltd SADENATSUHIKAKUKAIRO

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51128444U (en) * 1975-04-15 1976-10-16

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5082963A (en) * 1973-11-05 1975-07-04
JPS5172253A (en) * 1974-12-20 1976-06-22 Hitachi Ltd SADENATSUHIKAKUKAIRO

Also Published As

Publication number Publication date
JPS54118149A (en) 1979-09-13

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