JPS6253754U - - Google Patents
Info
- Publication number
- JPS6253754U JPS6253754U JP14462185U JP14462185U JPS6253754U JP S6253754 U JPS6253754 U JP S6253754U JP 14462185 U JP14462185 U JP 14462185U JP 14462185 U JP14462185 U JP 14462185U JP S6253754 U JPS6253754 U JP S6253754U
- Authority
- JP
- Japan
- Prior art keywords
- data
- output signal
- signal
- difference
- differential output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Image Processing (AREA)
- Picture Signal Circuits (AREA)
- Character Input (AREA)
Description
第１図は本考案による輪郭補正回路の一実施例
を示す回路図、第２図はそのメモリ内に予め格納
されるデータ値を表わす図、第３図は上記実施例
の各部の信号のデータ値を表わす図である。
６：２階差分回路、８：メモリ、９：加減算回
路、１０：遅延回路。
FIG. 1 is a circuit diagram showing an embodiment of the contour correction circuit according to the present invention, FIG. 2 is a diagram showing data values stored in advance in its memory, and FIG. 3 is data of signals of each part of the above embodiment. It is a figure showing a value. 6 : second-order differential circuit, 8: memory, 9: addition/subtraction circuit, 10: delay circuit.
Claims (1)
ツク分相当の遅延回路と非遅延路と減算回路から
なる差分回路によつて２階差分し、その差分出力
信号を入力信号レベルと所定の関係の値を表わす
補正用のデータが予め格納されたメモリに印加し
、それによつて該メモリから上記差分出力信号の
各サンプル点に対応するデータ信号を順次出力さ
せ、このデータ信号と前記映像信号を少なくとも
１サンプルクロツク遅延させた信号間で、前記差
分出力信号の正、負極性に応じて加算または減算
を行なうように構成した輪郭補正回路。 A digital video signal is subjected to a second difference using a difference circuit consisting of a delay circuit equivalent to at least one sample clock, a non-delay path, and a subtraction circuit, and the difference output signal is corrected to represent a value in a predetermined relationship with the input signal level. data for the differential output signal is applied to a memory in which data is stored in advance, thereby sequentially outputting a data signal corresponding to each sample point of the differential output signal from the memory, and the data signal and the video signal are synchronized at least one sample clock. A contour correction circuit configured to perform addition or subtraction between the delayed signals depending on the positive or negative polarity of the differential output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14462185U JPS6253754U (en) | 1985-09-20 | 1985-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14462185U JPS6253754U (en) | 1985-09-20 | 1985-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6253754U true JPS6253754U (en) | 1987-04-03 |
Family
ID=31055393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14462185U Pending JPS6253754U (en) | 1985-09-20 | 1985-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6253754U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877375A (en) * | 1981-11-02 | 1983-05-10 | Oki Electric Ind Co Ltd | Profile compesating system |
-
1985
- 1985-09-20 JP JP14462185U patent/JPS6253754U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877375A (en) * | 1981-11-02 | 1983-05-10 | Oki Electric Ind Co Ltd | Profile compesating system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6253754U (en) | ||
| JPH0441530B2 (en) | ||
| JPS6442625U (en) | ||
| JPH0398532U (en) | ||
| JPS63129333U (en) | ||
| JPH01100583U (en) | ||
| JPH02120942U (en) | ||
| JPS61192349U (en) | ||
| JPS63310216A (en) | Counting circuit | |
| JPH0370424U (en) | ||
| JPS63163028U (en) | ||
| JPS58114598U (en) | CCD input/output circuit | |
| JPH0256853B2 (en) | ||
| JPS62127122U (en) | ||
| JPH01162942U (en) | ||
| JPS60158294U (en) | Gas leak detection system repeater | |
| JPS63156158U (en) | ||
| JPH0375699U (en) | ||
| JPH0370425U (en) | ||
| JPS6316727U (en) | ||
| JPH0466818U (en) | ||
| JPS5928734U (en) | signal input device | |
| JPS62127115U (en) | ||
| JPS5871843U (en) | BCD signal reading device | |
| JPS5823432U (en) | noise suppression circuit |