JPS6253738U - - Google Patents
Info
- Publication number
- JPS6253738U JPS6253738U JP14429485U JP14429485U JPS6253738U JP S6253738 U JPS6253738 U JP S6253738U JP 14429485 U JP14429485 U JP 14429485U JP 14429485 U JP14429485 U JP 14429485U JP S6253738 U JPS6253738 U JP S6253738U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- protection circuit
- immediately before
- write permission
- data protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001052 transient effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図はこの考案の一実施例によるデータ保護
回路を示す回路図、第２図は第１図に示したデー
タ保護回路の動作を説明するためのタイミング図
、第３図は従来のデータ保護回路を示す回路図、
第４図は第３図に示したデータ保護回路の動作を
説明するためのタイミング図である。
図において、１及び９は入力端子、２は出力端
子、７はＡＮＤ回路である。なお、図中の同一符
号は同一または相当部分を示す。
Figure 1 is a circuit diagram showing a data protection circuit according to an embodiment of this invention, Figure 2 is a timing diagram for explaining the operation of the data protection circuit shown in Figure 1, and Figure 3 is a conventional data protection circuit. a circuit diagram showing the circuit;
FIG. 4 is a timing diagram for explaining the operation of the data protection circuit shown in FIG. 3. In the figure, 1 and 9 are input terminals, 2 is an output terminal, and 7 is an AND circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
制御装置によつて制御される外部記憶装置に送出
するためのデータ保護回路において、前記制御装
置の電源電圧の過渡状態の直後及び直前の充分長
い時間前記データ書込許可信号を送出しないよう
にする信号送出手段を備えたことを特徴とするデ
ータ保護回路。 (2) 信号送出手段は、ホスト・システムから入
力され、電源電圧がその過渡状態の直後及び直前
の充分長い時間を除く定常状態「Ｈ（高電位）」
にある場合にのみ定常状態「Ｈ」となるＰＯＫ信
号と、データ書込許可信号とが入力されるＡＮＤ
回路によつて構成されていることを特徴とする実
用新案登録請求の範囲第１項記載のデータ保護回
路。[Claims for Utility Model Registration] (1) In a data protection circuit for sending a data write permission signal from a control device to an external storage device controlled by the control device, A data protection circuit comprising signal sending means for not sending out the data write permission signal for a sufficiently long period of time immediately before and immediately before a transient state. (2) The signal sending means receives input from the host system, and the power supply voltage is in a steady state "H (high potential)" excluding a sufficiently long period immediately before and immediately before the transient state.
AND signal in which the POK signal, which becomes steady state "H" only when the data write permission signal is input, and the data write permission signal are input.
The data protection circuit according to claim 1, characterized in that the data protection circuit is constituted by a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14429485U JPS6253738U (en) | 1985-09-24 | 1985-09-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14429485U JPS6253738U (en) | 1985-09-24 | 1985-09-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6253738U true JPS6253738U (en) | 1987-04-03 |
Family
ID=31054754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14429485U Pending JPS6253738U (en) | 1985-09-24 | 1985-09-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6253738U (en) |
-
1985
- 1985-09-24 JP JP14429485U patent/JPS6253738U/ja active Pending
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