JPS6253038A - Duplicated system for data transmission equipment - Google Patents
Duplicated system for data transmission equipmentInfo
- Publication number
- JPS6253038A JPS6253038A JP19258885A JP19258885A JPS6253038A JP S6253038 A JPS6253038 A JP S6253038A JP 19258885 A JP19258885 A JP 19258885A JP 19258885 A JP19258885 A JP 19258885A JP S6253038 A JPS6253038 A JP S6253038A
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- switch
- signal
- parallel
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野)
本発明は、データ伝送を行なう装置における二重化シス
テムにIllする。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is directed to a duplex system in a device that transmits data.
従来、この種のシステムにおいては、送信装置−)ドラ
イバー)伝送路→レシーバ→受信装置から成る伝送装置
2系列並列に接続し、一方の系列が故障のとき他方の系
列へ切替を行なっていた。Conventionally, in this type of system, two series of transmission apparatuses, each consisting of a transmitter, a driver, a transmission path, a receiver, and a receiver, are connected in parallel, and when one series fails, switching to the other series is performed.
このため、たとえば一方の送信装置と他方の伝送路の2
個所のトラブルが発生したとき、的確にこれらに対応が
できず、故障回復まで多くの時間、データ伝送が途絶す
るという事態が生起していた。For this reason, for example, two transmission lines between one transmitter and the other
When a problem occurs in a particular location, it is not possible to respond appropriately, resulting in a situation where data transmission is interrupted for a long time until the problem is recovered.
(発明の目的)
ここにおいて本発明は、従来例の難点を克服し、デジタ
ルデータのシリアル伝送装置での部品破壊、伝送路Ig
i線等の故障による伝送不能状態に陥る危険を減少させ
たデータ伝送装置の二重化システムを提供することを、
その目的とする。(Object of the Invention) Here, the present invention overcomes the difficulties of the conventional example, and solves the problem of component destruction in a digital data serial transmission device.
To provide a redundant system for data transmission equipment that reduces the risk of becoming unable to transmit due to failure of i-line, etc.
That purpose.
(発明の概要)
本発明は、上記目的を達成ザるために、デジタルデータ
をシリアル伝送する伝送装置において、
並行する2つの伝送路の送、受両端に、P/S変換を行
なう送信装置、ラインドライバ、ラインレシーバ、S/
P変換を行なう受信装置を各々2台づつ用い、
ラインドライバ、ラインレシーバ、受信装置から成る伝
送経路を、2経路並列に接続し、2伝送路に接続される
送信装置のA、Bいずれかを選択するスイッチSW1と
、
受信データを伝送路のA側、B側のいずれかを選択する
スイッチSW2と、
送信装置△、Bから、それぞれの送信装置の状態を示す
信号を受tjとり、スイッチSW1を制御する第1の故
障検出回路と、
受信装置A、Bから、おのおのの受信R1’fの状態を
表わす信号を受けとり、スイッチSW2をmil制御す
る第2の故障検出回路と、
を有する。(Summary of the Invention) In order to achieve the above object, the present invention provides a transmission device that serially transmits digital data, and a transmitting device that performs P/S conversion at both sending and receiving ends of two parallel transmission paths. Line driver, line receiver, S/
Using two receiving devices each that perform P conversion, two transmission paths consisting of a line driver, line receiver, and receiving device are connected in parallel, and either transmitting device A or B connected to the two transmission paths is connected. A switch SW1 selects the received data, a switch SW2 selects either the A side or the B side of the transmission path, and the switch SW1 receives signals tj indicating the status of each transmitter from the transmitters △ and B. and a second failure detection circuit that receives signals representing the states of the respective receivers R1'f from the receivers A and B and controls the switch SW2 in a mil manner.
ことを特徴とするデータ伝送装置の二重化シス゛アムで
ある。This is a duplex system of data transmission equipment characterized by the following.
本発明の一実施例における回路構成を表わすブロック図
を第1図に示す。FIG. 1 shows a block diagram showing a circuit configuration in an embodiment of the present invention.
1.2はP/S変換(パラレル信号をシリアル信号に変
換)して、デジタルデータをシリアルにに伝送する送信
装置Δ、B、3.4はシリアル信号からパラレル信号へ
のS/P変換を行なう受信装′eIA、B、5.6はデ
ータを伝送路へ送出するラインドライバA、B、7.8
はデータを伝送路から受け入れるラインレジーバA、B
、9.10はデータを伝送する伝送路A、8.11は1
,2の送信装HA、Bからの情報に基づき第1の故障検
出切替回路12からの指令によりそのいずれの送信装置
を伝送路に接続するか切替を行なうスイッチ(SWI)
、13は3.4の受信装置A、Bからの情報に基づき第
2の故障検出切替回路14の指令によりいずれかの受信
装置を内部機器15へ接続するか切替を行なうスイッチ
(SW2)である。1.2 is a transmitting device Δ, B that performs P/S conversion (converts a parallel signal to a serial signal) and transmits digital data serially; 3.4 performs S/P conversion from a serial signal to a parallel signal. The receiving devices 'eIA, B, 5.6 are line drivers A, B, 7.8 that send data to the transmission path.
are line receivers A and B that accept data from the transmission path.
, 9.10 is transmission path A for transmitting data, 8.11 is 1
, 2 transmitting devices HA, B, and a switch (SWI) that switches which transmitting device is connected to the transmission line based on a command from the first failure detection switching circuit 12.
, 13 is a switch (SW2) that connects or switches one of the receiving devices to the internal device 15 in response to a command from the second failure detection switching circuit 14 based on the information from the receiving devices A and B in 3.4. .
−f %わち、本発明は、ラインドライバ5.6、伝送
路9.10、レシーバ7.8、受信装置!13゜4から
成る伝送路を△およびBと2経路を並列に設ける。-f % That is, the present invention includes a line driver 5.6, a transmission line 9.10, a receiver 7.8, and a receiving device! Two transmission paths, △ and B, consisting of 13°4 are provided in parallel.
送信装置1.2とA、82台用い、たとえばリレー、3
ステートバツフ?[アクティブのハイH電圧とロウLf
fl圧とノンアクティブ(ハイインピーダンス)の3状
態をもつバッファ]等からなるスイッチ11(SWI)
を配備し、]、2の送信RffiA、Bを選択すること
により、データの送りの流れを切り苔えられるようにす
る。Transmitting device 1.2 and A, using 82 units, e.g. relay, 3
State batshu? [Active high H voltage and low Lf
A switch 11 (SWI) consisting of a buffer with three states: fl pressure and non-active (high impedance).
], 2 transmission RffiA, B, the flow of data transmission can be controlled.
そして、データは5.6のドライバA、B→9゜10の
伝送路A、B→7.8のレシーバA、Bを経由して3.
4の受信装置A、Bに至る。The data then passes through transmission lines A and B of 5.6 drivers A and B → 9 degrees and 10 of 3.8 and receivers A and B of 7.8.
4 to receiving devices A and B.
ここで、3.4の受信装aA、Bからのデータを選択す
るスイッチ13(SW2)をmi:Jる。このスイッチ
SW2は送信側のスイッチSW1と同様な手段が適用さ
れる。Here, the switch 13 (SW2) for selecting data from the receiving devices aA and B of 3.4 is set mi:J. The same means as the switch SW1 on the transmitting side is applied to this switch SW2.
つぎに、第1の故障検出切替回路12は送信装ff1A
、Bの出力状態を常時覧視し、異常を検出すると明石信
号を出してスイッチ(SWl )11を切口える。もつ
とも、送信装置1,2が正常の場合はA側へ接続するこ
とを優先させるなど、それらは自由である。Next, the first failure detection switching circuit 12 is connected to the transmitting device ff1A.
, B are constantly checked, and when an abnormality is detected, an Akashi signal is output and the switch (SWl) 11 is turned off. However, if the transmitting devices 1 and 2 are normal, they are free to give priority to connecting to the A side.
同様に、第2の故障検出回路14は受信装に3゜4の状
態を常に監視し、異常を検出すると、切替スイッチ(S
W2)13をA、Bいずれか正常の方へ切替える。Similarly, the second fault detection circuit 14 constantly monitors the state of the receiver, and when an abnormality is detected, it switches the switch (S
W2) Switch 13 to either A or B, whichever is normal.
しかして、第1、第2の故障検出切替回路12゜14の
一例として第2図の回路構成が考えられる。Therefore, the circuit configuration shown in FIG. 2 can be considered as an example of the first and second failure detection switching circuits 12 and 14.
140は一定周期のパルスを連続して発生しているり0
ツク、141.142はカウンタで、そのCLKE子へ
入るりOツクをJ1数し、そのCLK Ga子からのデ
ータパルスによってリセットしており、そのQ。端子は
カウンタがオバーフローしたときの出力端である。14
3はアンド(論理積)回路、もっとも出力位相を反転さ
せているからナンド回路である。カウンタのCLR端子
、ナンド回路143の下端の入力端子のそれぞれに付し
た0印は入力位相を反転させるシンボルである。140 continuously generates pulses with a constant period or 0
141 and 142 are counters that count the number of inputs to the CLKE child by J1, and are reset by the data pulse from the CLKGa child. The terminal is the output terminal when the counter overflows. 14
3 is an AND (logical product) circuit, and since the output phase is inverted, it is a NAND circuit. The 0 mark attached to each of the CLR terminal of the counter and the input terminal at the lower end of the NAND circuit 143 is a symbol for inverting the input phase.
たとえば、伝送路Aでデータ伝送中で、全てが正常のと
き、カウンタCLKはりOツクが連続して入力するが、
CLK端子にはデータ入力が位相反転して受け入れられ
ず、端子Q。からオバーフロー出力が連続するので、ナ
ンド143は切替信号をスイッチ13へ指令しない。For example, when data is being transmitted on transmission line A and everything is normal, the counter CLK and Otsuk are input continuously.
The data input to the CLK terminal is not accepted due to phase inversion, and the data input to the Q terminal is not accepted. Since the overflow output continues from 1 to 1, the NAND 143 does not issue a switching signal to the switch 13.
ところが、伝送路Aが故障すると、カウンタ141のオ
バーフローが出力しなくなり、かつカウンタ142のオ
バーフロー出力が出力しナンド143の入力側で反転し
て入るからナンド回路143は切替信号をスイッチ(S
W2)13へ与え、スイッチIa片は受信装置Ff14
側へ倒れ、内部機器15へは伝送路Bを経由してデータ
が伝送される。However, when the transmission line A fails, the overflow of the counter 141 is no longer output, and the overflow output of the counter 142 is output and inverted at the input side of the NAND 143, so the NAND circuit 143 switches the switching signal to the switch (S
W2) 13, and the switch Ia piece is connected to the receiving device Ff14.
It falls to the side, and data is transmitted to the internal device 15 via transmission path B.
かくして本発明によれば、たとえば送信装回△および伝
送路Bが故障、lli線のような異系路2個所のトラブ
ルにも、スイッチSW1およびSW2を適切に切替える
ことにより、十分な伝送が可能となり、データ伝送りl
置の二重化システムにおけるデータ伝送の効率を大きく
し、とくにデータ伝送の信頼性を著しく向上させること
から、当該分野に寄与するところが多い。Thus, according to the present invention, even if there is a failure in the transmitter circuit △ and the transmission line B, or there is a problem in two different lines such as the LLI line, sufficient transmission is possible by appropriately switching the switches SW1 and SW2. Therefore, data transmission l
It has many potential contributions to this field because it increases the efficiency of data transmission in redundant systems, and in particular significantly improves the reliability of data transmission.
第1図は本発明の一実施例の回路構成を表わすブロック
図、第2図はその故障検出回路回路の路線図である。
1.2・・・送信装昭A、B、3.4・・・受信装Wi
A。
B、5.6・・・ラインドライバA、B、7.8・・・
ラインドライバA、B、9.10・・・伝送路A、B、
11・・・スイッチ(SWI)、12・・・第1の故障
検出切替回路、13・・・スイッチ(SW2)、14・
・・第2の故障検出回路、15・・・内部機器。FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 2 is a route diagram of the failure detection circuit. 1.2... Transmitter A, B, 3.4... Receiver Wi
A. B, 5.6... Line driver A, B, 7.8...
Line drivers A, B, 9.10...transmission lines A, B,
DESCRIPTION OF SYMBOLS 11... Switch (SWI), 12... First failure detection switching circuit, 13... Switch (SW2), 14...
...Second failure detection circuit, 15...Internal equipment.
Claims (1)
と、そのシリアル信号を伝送路へ送出するラインドライ
バと、送信側から受信側へ信号を伝送する伝送路と、伝
送路から信号を受け入れるラインレシイバと、この受け
入れたシリアル信号をパラレル信号へ変換する受信装置
とをそれぞれ2台づつ配設するとともに、送信装置→ラ
インドライバ→伝送路→ラインレシイバ→受信装置から
成る伝送経路を2経路並列に接続する手段と、2つの伝
送路に接続される送信装置の一方か他方かのいずれかを
選択する第1のスイッチと、受信データを伝送路の一方
か他方かのいずれかを選択する第2のスイッチと、 2つの送信装置からそれぞれの送信状態を示す信号を受
けとり、第1のスイッチの切替を制御する第1の故障検
出回路と、 2つの受信装置からおのおのの受信状態を表わす信号を
受けとり、第2のスイッチの切替を制御する第2の故障
検出回路と、 を具備することを特徴とするデータ伝送装置の二重化シ
ステム。[Scope of Claims] 1. A device for serially transmitting digital data, which includes a transmitting device that converts a parallel signal to a serial signal, a line driver that sends the serial signal to a transmission path, and a signal from the transmitting side to the receiving side. A transmission path for transmitting a signal, a line receiver for receiving a signal from the transmission path, and a receiving device for converting the received serial signal into a parallel signal are installed. →Means for connecting two transmission paths consisting of receiving devices in parallel, a first switch for selecting one or the other of the transmitting devices connected to the two transmission paths, and a means for connecting received data to the transmission path. a second switch that selects either one or the other; a first failure detection circuit that receives signals indicating respective transmission states from the two transmitters and controls switching of the first switch; 1. A duplex system for data transmission equipment, comprising: a second fault detection circuit that receives signals representing respective reception states from the reception equipment and controls switching of a second switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19258885A JPS6253038A (en) | 1985-08-31 | 1985-08-31 | Duplicated system for data transmission equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19258885A JPS6253038A (en) | 1985-08-31 | 1985-08-31 | Duplicated system for data transmission equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6253038A true JPS6253038A (en) | 1987-03-07 |
Family
ID=16293775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19258885A Pending JPS6253038A (en) | 1985-08-31 | 1985-08-31 | Duplicated system for data transmission equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6253038A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748170A1 (en) * | 1996-04-25 | 1997-10-31 | France Telecom | Automatic transmission line switching device for digital communications |
JP2012212810A (en) * | 2011-03-31 | 2012-11-01 | Renesas Electronics Corp | Semiconductor integrated circuit and method of laying out the same |
-
1985
- 1985-08-31 JP JP19258885A patent/JPS6253038A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2748170A1 (en) * | 1996-04-25 | 1997-10-31 | France Telecom | Automatic transmission line switching device for digital communications |
JP2012212810A (en) * | 2011-03-31 | 2012-11-01 | Renesas Electronics Corp | Semiconductor integrated circuit and method of laying out the same |
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