JPS6252940U - - Google Patents
Info
- Publication number
- JPS6252940U JPS6252940U JP14504185U JP14504185U JPS6252940U JP S6252940 U JPS6252940 U JP S6252940U JP 14504185 U JP14504185 U JP 14504185U JP 14504185 U JP14504185 U JP 14504185U JP S6252940 U JPS6252940 U JP S6252940U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- heat dissipation
- constructed
- dissipation structure
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000017525 heat dissipation Effects 0.000 claims description 6
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は、本考案に係る放熱構造を示す斜視図
、第２図は、本考案の他の実施例を示す断面図で
あり、第３図ａは従来の集積回路をプリント基板
に取付けた状態を示す斜視図、第３図ｂは第３図
ａにおけるＡ―Ａ′断面図である。
図において、１は集積回路、２はプリント基板
、３１は放熱フイン、４１は放熱シート、４２は
放熱シート４１に設けた放熱フインである。
Fig. 1 is a perspective view showing a heat dissipation structure according to the present invention, Fig. 2 is a sectional view showing another embodiment of the invention, and Fig. 3 a shows a conventional integrated circuit mounted on a printed circuit board. A perspective view showing the state, FIG. 3b is a sectional view taken along line AA' in FIG. 3a. In the figure, 1 is an integrated circuit, 2 is a printed circuit board, 31 is a heat dissipation fin, 41 is a heat dissipation sheet, and 42 is a heat dissipation fin provided on the heat dissipation sheet 41.
Claims (1)
り構成したことを特徴とする集積回路の放熱構造
。 1. A heat dissipation structure for an integrated circuit, characterized in that it is constructed by providing unevenness on a mold portion of the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14504185U JPS6252940U (en) | 1985-09-20 | 1985-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14504185U JPS6252940U (en) | 1985-09-20 | 1985-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6252940U true JPS6252940U (en) | 1987-04-02 |
Family
ID=31056209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14504185U Pending JPS6252940U (en) | 1985-09-20 | 1985-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6252940U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60127747A (en) * | 1983-12-15 | 1985-07-08 | Matsushita Electric Ind Co Ltd | Resin-sealed semiconductor device |
-
1985
- 1985-09-20 JP JP14504185U patent/JPS6252940U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60127747A (en) * | 1983-12-15 | 1985-07-08 | Matsushita Electric Ind Co Ltd | Resin-sealed semiconductor device |