JPS6251260A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6251260A
JPS6251260A JP18962685A JP18962685A JPS6251260A JP S6251260 A JPS6251260 A JP S6251260A JP 18962685 A JP18962685 A JP 18962685A JP 18962685 A JP18962685 A JP 18962685A JP S6251260 A JPS6251260 A JP S6251260A
Authority
JP
Japan
Prior art keywords
gate electrode
layer
electrode
potential
thyristor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18962685A
Other languages
Japanese (ja)
Inventor
Yoshitaka Sugawara
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18962685A priority Critical patent/JPS6251260A/en
Publication of JPS6251260A publication Critical patent/JPS6251260A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect

Abstract

PURPOSE:To obtain a field effect semiconductor device, which can implement high withstanding voltage even in AC driving, by providing means and resistor components having a rectifying function in the forward direction toward a gate electrode between main electrodes and the gate electrode. CONSTITUTION:Means and resistor components, which have rectifying characteristics in the forward direction toward a gate electrode 7 are provided between main electrodes 5 and 8 and the gate electrode 7. For example, a high concentration (n) layer 103 is formed in a boundary region between an island 101 is semiconductor substrate and an insulating film 102. In this island 101, a PB laye 2 and a PE layer 4 are formed by impurity diffusion. An nE layer 1 is formed in the PB layer 2. A part, in which impurities are not diffused, works as a thyristor nB layer 3. On a substrate 100, a silicon oxide film 104 is provided. Through holes provided in the film 104, the cathode electrode 5, the gate electrode and the MOS electrode 6 and 7, and the anode electrode 8 are provided. Resistors and diodes 10-13, 9 and 12 are connected between the gate electrode 7 and the anode electrode 8 and between the gate electrode 7 and the cathode electrode 5 as shown in the Figure.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係わり、特に交流で使用する上で
好適な電界効果型高耐圧半導体装置に関する。  ・ 〔発明の背景〕 一般に電界効果型高耐圧半導体装置には高電圧を印加す
るとドレインからのもれ電界でゲート電極が帯電し、こ
の帯電ゲート電圧のために比較的低いソース・ドレイン
間印加電圧でゲート電極下が反転しチャネルが形成され
るために、ソース・ドレイン間の耐圧が低下するという
問題がある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a field effect type high voltage semiconductor device suitable for use in alternating current.・ [Background of the Invention] Generally, when a high voltage is applied to a field effect type high voltage semiconductor device, the gate electrode is charged due to the leakage electric field from the drain, and this charged gate voltage causes a relatively low voltage to be applied between the source and drain. Since the area under the gate electrode is inverted and a channel is formed, there is a problem in that the withstand voltage between the source and drain decreases.

・このゲート電極の帯電を少なくし高耐圧を実現する方
法として従来MO8電界効果型半導体装置等について■
ドレイン接合近傍のゲート電極下の酸化膜を厚くする方
法が工業調査会発行エレクトロニクス技術全書筒3巻M
OSデバイスp276に開示されている。又■オフセッ
トゲート構造にする方法が同文献あるいはアイイーイー
イー トランザクション オン エレクトロン デバイ
セス、ボリューム イーディー29の1171頁(19
82)(IE8tl Transaction on 
IElactron Devices Vo Q 。
- Regarding conventional MO8 field effect semiconductor devices, etc., as a method to reduce the charge on the gate electrode and achieve high withstand voltage.
A method to thicken the oxide film under the gate electrode near the drain junction is described in Electronics Technology Complete Book Volume 3 M published by Kogyo Kenkyukai.
It is disclosed in OS Device p276. Also, the method of creating an offset gate structure is described in the same document or in IEE Transactions on Electron Devices, Volume E.D. 29, page 1171 (19
82) (IE8tl Transaction on
IELactron Devices VoQ.

E D −29、pH71(1982) )  等に開
示されている。
ED-29, pH71 (1982)), etc.

しかし、これらはいずれも直流で使用することを目的と
した装置であり、交流で使用する場合は一方の極性の印
加電圧では高耐圧を実現できるが逆極性の場合は数十V
以下の耐圧であり高耐圧を実現できない。又、交流で使
用可能な方法については言及されてもいない。
However, these are all devices intended to be used with direct current, and when used with alternating current, a high withstand voltage can be achieved with an applied voltage of one polarity, but in the case of the opposite polarity, a voltage of several tens of volts can be achieved.
The breakdown voltage is below, and high breakdown voltage cannot be achieved. Furthermore, there is no mention of methods that can be used for alternating current.

前者の方法を取り上げて交流で使用する場合の問題点を
以下に詳述する。
The problems encountered when using the former method in exchange will be detailed below.

第5図は上記の文献に開示されたMOS−FETk示す
。高耐圧を実現するためにゲート電極7の下のゲート酸
化膜に段差を形成し、ドレイン25の近傍の酸化膜27
を厚くせしめである。
FIG. 5 shows a MOS-FETk disclosed in the above-mentioned document. In order to achieve high breakdown voltage, a step is formed in the gate oxide film under the gate electrode 7, and the oxide film 27 near the drain 25 is
It is recommended to make it thicker.

本装置の場合、ドレイン25を負、ソース24を正とす
るいわゆる順方向の極性の電圧を印加する場合、もれ電
界によるゲート電極7の帯電をおさえより高耐圧を確保
するためにドレイン25近傍の酸化11127をより厚
くする必要があり、ドレイン25から離れた部分のゲー
ト酸化膜28との間に著しい段差を設ける必要がある。
In the case of this device, when applying a so-called forward polarity voltage in which the drain 25 is negative and the source 24 is positive, the drain 25 is It is necessary to make the oxide layer 11127 thicker, and it is necessary to provide a significant step difference between the gate oxide film 28 and the portion away from the drain 25.

従って段差形成プロセスを追加したり、段差部でのゲー
ト電極の段切れを防止するプロセスを追加したりする必
要が生じプロセスが著しく複雑になるという問題がある
Therefore, it is necessary to add a step forming process or a process to prevent the gate electrode from breaking at the step, resulting in a problem that the process becomes extremely complicated.

更に、この方法の場合、交流駆動の電界効果型高耐圧半
導体装置には適用できないという本質的な問題がある。
Furthermore, this method has the essential problem that it cannot be applied to AC-driven field effect type high voltage semiconductor devices.

即ち、印加電圧が第5図においてドレイン25が正、ソ
ース24が負になるような逆方向の極性で駆動し高い耐
圧を実現しようとする場合、逆にバイアスされるソース
接合近傍のゲート電極7下の酸化膜28も厚くする必要
があるからである。この場合、順方向動作時に所定のゲ
ート電圧を印加してもソース24より離れた薄いゲート
酸化膜28に対応する部分ではチャネルが形成できるが
、ソース24近傍の厚いゲート酸化膜に対応する部分で
はチャネルが形成されず動作不能となってしまう。
That is, when trying to realize a high withstand voltage by driving the applied voltage with reverse polarity such that the drain 25 is positive and the source 24 is negative in FIG. 5, the gate electrode 7 near the source junction is biased in the opposite direction. This is because the underlying oxide film 28 also needs to be thick. In this case, even if a predetermined gate voltage is applied during forward operation, a channel can be formed in the part corresponding to the thin gate oxide film 28 away from the source 24, but in the part corresponding to the thick gate oxide film near the source 24. A channel is not formed and the device becomes inoperable.

〔発明の目的〕[Purpose of the invention]

本発明の目的はかかる従来技術の問題を克服し交流駆動
でも高耐圧を実現できる電界効果型半導体装置を提供す
ることにある。
An object of the present invention is to overcome the problems of the prior art and to provide a field effect semiconductor device that can achieve high breakdown voltage even when driven with AC.

〔発明の概要〕[Summary of the invention]

本発明の目的は、一対の主電極A、Bをもつ電界効果型
半導体装置において順バイアス時に高電位となる主電極
Aとゲート電極とが略等しい電位になるようにし、逆バ
イアス時には高電位となる主電極Bとゲート電極とが略
等しい電位になるようにせしめることによって達成され
る。
An object of the present invention is to provide a field effect semiconductor device having a pair of main electrodes A and B so that the main electrode A and the gate electrode, which have a high potential when forward biased, have approximately the same potential, and have a high potential when reverse biased. This is achieved by making the main electrode B and the gate electrode have approximately the same potential.

すなわち、主電極Aとゲート電極間及び主電極Bとゲー
ト電極間にダイオードのような整流特性を有する短絡手
段を各々上記の動作を示す向きに接続することによって
達成されるものである。
That is, this is achieved by connecting short-circuiting means having rectifying characteristics, such as diodes, between the main electrode A and the gate electrode and between the main electrode B and the gate electrode, respectively, in directions that exhibit the above-mentioned operation.

〔発明の実施例〕[Embodiments of the invention]

以下、実施例にもとづき本発明の詳細とその効果を説明
する。
Hereinafter, the details of the present invention and its effects will be explained based on Examples.

第1図は本発明になる第1の実施例であるMOS電界効
果型ラテラルサイリスタを示す。
FIG. 1 shows a MOS field effect type lateral thyristor which is a first embodiment of the present invention.

第1図において、100は誘電体絶縁分離基板で、10
1は絶縁fil102を介して埋込まれた1個のn型の
半導体単結晶島である。半導体基体としての島101の
絶縁膜102との境界領域には高濃度n層103が形成
されている。島101にはpa層2、pE層4が不純物
拡散により形成され、pa層2にnE層1が形成され、
不純物が拡散されなかった部分はサイリスタn1層3と
して働く。基板100上にはシリコン酸化膜104が設
けられ、該膜104に設けた開孔を通してカッ−ド電極
5、電気並びにMOSゲート電極6,7、アノード電極
8が設けられる。ゲート電極7とアノード電極8の間、
ゲート電極7とカソード電極5の間に抵抗、ダイオード
10〜13,9.12が図示の如く接続されている。
In FIG. 1, 100 is a dielectric insulation isolation substrate;
Reference numeral 1 denotes one n-type semiconductor single crystal island embedded through an insulating film 102. A high concentration n layer 103 is formed in the boundary region between the island 101 serving as a semiconductor substrate and the insulating film 102 . A pa layer 2 and a pE layer 4 are formed on the island 101 by impurity diffusion, and an nE layer 1 is formed on the pa layer 2.
The portion where the impurity is not diffused functions as the thyristor n1 layer 3. A silicon oxide film 104 is provided on the substrate 100, and a quad electrode 5, electrical and MOS gate electrodes 6, 7, and an anode electrode 8 are provided through openings provided in the film 104. Between the gate electrode 7 and the anode electrode 8,
Resistors and diodes 10 to 13, 9 and 12 are connected between the gate electrode 7 and the cathode electrode 5 as shown.

尚、以下では各層1〜4は単にnE # Pa * n
BIPEと略記する。
In addition, below, each layer 1-4 is simply nE#Pa*n
It is abbreviated as BIPE.

まず本装置のオフ状態における高耐圧を実現する機構を
説明する。アノード端子Aがカソード端子により高電位
となるいわゆる順バイアス状態ではPH2とnE3とで
形成されるpn接合が逆バイアスされる。この時ダイオ
ード9と抵抗10を介してゲート電極7とPE4が接続
されているためダイオード9は順バイアスされる一方、
ダイオード12と抵抗11を介してゲート電極7とpa
2が接続されているためダイオード12は逆バイアスさ
れる。この結果、サイリスタが順バイアス時にはゲート
電極7の電位はnE3の電位に略等しくなり、もれ電界
によるゲート電極の帯電が防止されるのでゲート電極7
の下のnベース表面のチャネル形成はおさえられ高い順
方向耐圧を実現できる。
First, a mechanism for achieving high withstand voltage in the OFF state of this device will be explained. In a so-called forward bias state in which the anode terminal A has a higher potential than the cathode terminal, the pn junction formed by PH2 and nE3 is reverse biased. At this time, since the gate electrode 7 and PE4 are connected through the diode 9 and the resistor 10, the diode 9 is forward biased, while
Gate electrode 7 and pa via diode 12 and resistor 11
2 is connected, the diode 12 is reverse biased. As a result, when the thyristor is forward biased, the potential of the gate electrode 7 becomes approximately equal to the potential of nE3, and charging of the gate electrode due to a leakage electric field is prevented, so that the gate electrode 7
Formation of a channel on the n-base surface below is suppressed and a high forward breakdown voltage can be achieved.

又、サイリスタが逆バイアス状態ではpI!4とna 
3とで形成される接合が逆バイアスされるが。
Also, when the thyristor is in a reverse bias state, pI! 4 and na
Although the junction formed with 3 is reverse biased.

この場合ダイオード9も逆バイアスされる一方ダイオー
ド12が順バイアスされる。この結果、ゲート電極7の
電位はやはりnu 3の電位に略等しくなりn83表面
のチャネル形成が抑えられ高い逆方向耐圧を実現できる
In this case, diode 9 is also reverse biased while diode 12 is forward biased. As a result, the potential of the gate electrode 7 is substantially equal to the potential of nu3, suppressing the formation of a channel on the surface of n83, and achieving a high reverse breakdown voltage.

以上のように、本装置では、ゲート電極7のシリコン酸
化膜104の厚さに関係なく順逆とも高耐圧が実現でき
るので、シリコン酸化膜104の厚さは他の特性からの
要求により自由に選択できる利点がある。
As described above, in this device, a high breakdown voltage can be achieved regardless of the thickness of the silicon oxide film 104 of the gate electrode 7, both in the forward and reverse directions, so the thickness of the silicon oxide film 104 can be freely selected according to the requirements of other characteristics. There are advantages that can be achieved.

次に本装置をオンさせる動作機構を説明する。Next, the operating mechanism for turning on this device will be explained.

サイリスタが順バイアス状態でゲート端子Gをオープン
状態から所定の電位vOにした場合、アノード電位V^
に比ベゲート端子電位が低いとアノード端子Aからダイ
オード9と抵抗10を介してゲート端子Gに電流が流れ
、アノードとゲート端子間に(V^−Vo)の電位差が
維持される。
When the thyristor is in a forward bias state and the gate terminal G is changed from an open state to a predetermined potential vO, the anode potential V^
When the gate terminal potential is low compared to , a current flows from the anode terminal A to the gate terminal G via the diode 9 and the resistor 10, and a potential difference of (V^-Vo) is maintained between the anode and the gate terminal.

VoもしくはV^が変化し、この電位差(■^−Vo)
がn83表面が反転するしきい値電圧以上になると反転
層が形成される。従って、アノード端子A→pg→反転
層→pa→抵抗13→カソード端子にの経路で電流が流
れる。この結果、抵抗13の両端の電位がnB ・pa
接合がビルド アップ(build  uP)  する
電圧以上になると、nElから注入が起りnE!”pB
 ・nBトランジスタ部分がオンする。ついでpE−n
B−pBトランジスタ部分もオンし、両トランジスタ間
の正帰還によりサイリスタが点弧するに到る。
Vo or V^ changes, and this potential difference (■^-Vo)
When the voltage exceeds the threshold voltage at which the n83 surface is inverted, an inversion layer is formed. Therefore, a current flows along the path from anode terminal A→pg→inversion layer→pa→resistance 13→cathode terminal. As a result, the potential across the resistor 13 is nB ・pa
When the voltage at which the junction builds up (build up) is exceeded, injection occurs from nEl and nE! "pB
・The nB transistor part turns on. Then pE-n
The B-pB transistor section is also turned on, and the positive feedback between both transistors causes the thyristor to fire.

尚、本装置は逆バイアス状態からオンさせることはでき
ない。即ち、順逆とも高い耐圧を実現できる点において
交流駆動を達成している。
Note that this device cannot be turned on from a reverse bias state. In other words, AC drive is achieved in that high withstand voltage can be achieved in both forward and reverse directions.

本実施例において、na濃度、pI!とPBの表面濃度
、nBの表面濃度を各々2X101番国−8゜I X 
10 ”a++−”、  I X 10 ”am−”と
し、pa と   pE!間の距離を30μmとした場
合的230Vの順・逆面方向耐圧を実現できた。又本実
施例に於てゲート電極7の下の酸化膜厚を約0.4μm
とし抵抗13を約6にΩとした場、命、端子G、A間に
約3.5vの電位差(■^−Vo)を形成することによ
りサイリスタを点弧できた。
In this example, na concentration, pI! The surface concentration of PB, and the surface concentration of nB are each
10 "a++-", I X 10 "am-", pa and pE! When the distance between them was 30 μm, a breakdown voltage of 230 V in the forward and reverse directions could be achieved. In addition, in this embodiment, the thickness of the oxide film under the gate electrode 7 is approximately 0.4 μm.
When the resistor 13 was set to approximately 6 Ω, the thyristor could be ignited by forming a potential difference (■^-Vo) of approximately 3.5 V between the terminals G and A.

第2図は本発明になる第2の実施例のM、O8電界効果
形ラテラルサイリスタを示す。尚、第1図に示すものと
同−物相当物には同一符号を付けている。
FIG. 2 shows an M, O8 field effect lateral thyristor according to a second embodiment of the present invention. Components equivalent to those shown in FIG. 1 are given the same reference numerals.

本実施例は第1の実施例と同じ機能をより少ない素子構
成で、すなわちIC化した場合はより小さな占有面積で
実現できるという特長を有する。
This embodiment has the advantage that the same functions as those of the first embodiment can be realized with a smaller number of element configurations, that is, when integrated into an IC, the same functions can be realized with a smaller occupied area.

本実施例は、第1の実施例の高耐圧ダイオード9がpH
4とno 3とで形成する接合で兼用され、且つ高耐圧
ダイオード12がpa 2とnB3とで形成される接合
で兼用され、抵抗10と11が抵抗14で兼用される点
を除けば第1の実施例と全く同じ構成であり、且つ同じ
動作機構である。このため3個の素子が削減でき、IC
化した場合。
In this embodiment, the high voltage diode 9 of the first embodiment has a pH value of
4 and no. 3, the high voltage diode 12 is shared by the junction formed by pa. 2 and nB3, and the resistors 10 and 11 are used as the resistor 14. This embodiment has exactly the same configuration and the same operating mechanism as the embodiment. Therefore, three elements can be reduced, and the number of IC
If it becomes

占有面積が第1の実施例の約60%に縮小できる。The occupied area can be reduced to about 60% of that of the first embodiment.

本実施例になる素子の特性は第1の実施例と同等であり
、順逆耐圧が約230V、サイリスタを点弧させるゲー
ト重用が約3.5vである。
The characteristics of the device of this example are the same as those of the first example, with a forward and reverse breakdown voltage of approximately 230V and a gate duty for firing the thyristor of approximately 3.5V.

第3図は本発明になる第3の実施例である相補ゲート形
MO8電界効果ラテラルサイリスタを示す。
FIG. 3 shows a complementary gate MO8 field effect lateral thyristor according to a third embodiment of the present invention.

本装置では第1の実施例と同様にno a上にMOSゲ
ート電極7を設ける一方、pH2上にもMOSゲート電
極19を設けることにより、ゲート電位がアノードやカ
ソード電位に対し高・低いずれの場合でもサイリスタを
点弧できるようにせしめである。
In this device, the MOS gate electrode 7 is provided on noa as in the first embodiment, and the MOS gate electrode 19 is also provided on pH2, so that the gate potential can be high or low with respect to the anode or cathode potential. The thyristor should be able to fire even if the

又サイリスタが順バイアス時にMOSゲート電極19が
帯電し、p−16とpa l上にチャネルが形成され耐
圧が低下するのを抑えるためにGK−に間にダイオード
29を具備せしめである。更にオンさせる際に電極19
の下にチャネルを形成する電位をえるために抵抗30を
具備せしめである。又、p一層17.18を設けること
によりpl!・nB−pBで構成されるMOS −FE
Tをオフセット構造にする一方、p一層16を設けてゲ
ート電極19下のpa接合の電界緩和を計り更に高い耐
圧を実現できるようにせしめである。
In addition, a diode 29 is provided between GK- in order to prevent the MOS gate electrode 19 from being charged when the thyristor is forward biased, a channel is formed on p-16 and pal, and the withstand voltage is lowered. When turning on the electrode 19
A resistor 30 is provided below to obtain a potential to form a channel. Also, by providing p layer 17.18, pl!・MOS-FE composed of nB-pB
While the T has an offset structure, the P layer 16 is provided to relax the electric field of the PA junction under the gate electrode 19, thereby realizing a higher withstand voltage.

p一層16.17はpH2を取囲む一体化層であり、G
KとG^の両端子は外部接続されている。
The p layer 16.17 is an integrated layer surrounding pH2, and the G
Both terminals K and G^ are connected externally.

まずオフ状態において高耐圧を実現する動作機構につい
て説明する。
First, the operating mechanism that achieves high breakdown voltage in the off state will be explained.

第1の実施例では例えばサイリスタを順バイアスした時
にゲート電wA7の電位が略アノード電位に固定される
ために、pB”nB接合近傍のゲート電極7下のn8表
面の空乏化が抑制され空乏層が十分nu側に拡がらない
ために電界集中が激しくなり、低い電圧で降伏現象が発
生してしまい順方向耐圧が比較的低い。又サイリスタが
逆バイアス時にも同様の現象がゲート電極7の下のPE
  ・nB接合近傍で発生し逆方向耐圧が比較的低い。
In the first embodiment, for example, when the thyristor is forward biased, the potential of the gate voltage wA7 is fixed to approximately the anode potential, so depletion of the n8 surface under the gate electrode 7 near the pB"nB junction is suppressed, and the depletion layer does not spread sufficiently to the nu side, the electric field becomes concentrated, and a breakdown phenomenon occurs at low voltages, resulting in a relatively low forward breakdown voltage.Also, when the thyristor is reverse biased, a similar phenomenon occurs under the gate electrode 7. PE of
- Occurs near the nB junction and has a relatively low reverse breakdown voltage.

しかるに、本実施例の場合はp一層17.18を所定の
濃度にすることによりより高耐圧を実現できる。例えば
サイリスタが順バイアスの場合、ゲート電極7の下のp
B’nB接合近傍における空乏層のnts 3側への拡
がりは第1の実施例とほぼ同程度であるが、P一層17
の表面濃度を約5×1.0”an−”程度にすることに
よりP一層17側にも空乏層を拡げることができ電界集
中を著しく緩和できる。サイリスタが逆バイアス時にも
同様にPE’nB接合近傍において空乏層をP一層18
側にも拡げることができ電界集中を著しく緩和できる。
However, in the case of this embodiment, a higher breakdown voltage can be achieved by setting the p layer to a predetermined concentration of 17.18. For example, if the thyristor is forward biased, p below the gate electrode 7
The expansion of the depletion layer near the B'nB junction toward the nts 3 side is approximately the same as in the first embodiment, but the P layer 17
By setting the surface concentration of P to about 5.times.1.0 "an-", the depletion layer can be extended to the P layer 17 side, and electric field concentration can be significantly alleviated. Similarly, when the thyristor is reverse biased, the depletion layer near the PE'nB junction is
It can also be extended to the sides, significantly reducing electric field concentration.

なおこの場合pa 2に対向しないPE4の近傍におい
てはPE’nB接合をこえてnu側に張り出したアノー
ド電極8がもたらす、いわゆるフィールドプレート効果
により接合近傍の電界集中が緩和できる。これらの結果
、各層を第1の実施例と同様の不純物濃度にしP一層1
.6,17゜18の各々の長さを15μm、p一層17
.18間の間隔を25μmとし、且っpEよりnu側に
張り出した電極長を25μmとした場合約450Vの高
い順逆両方向の耐圧を実現できた6次にサイリスタの点
弧機構について説明する。
In this case, in the vicinity of the PE4 not facing pa2, the electric field concentration near the junction can be alleviated due to the so-called field plate effect brought about by the anode electrode 8 extending beyond the PE'nB junction to the nu side. As a result, each layer was made to have the same impurity concentration as in the first embodiment, and P layer 1
.. 6,17゜18 each length is 15 μm, p layer 17
.. The ignition mechanism of the sixth-order thyristor that can achieve a high forward and reverse breakdown voltage of about 450 V when the interval between the electrodes 18 and 18 is 25 μm and the length of the electrode protruding toward the nu side from pE is 25 μm will be described.

本装置は先に述べたようにサイリスタが順バイアス状態
で且つゲート端子G^をオープン状態がら所定の電位V
oにした場合、サイリスタのアノ−ド電位V^及びカソ
ード電位VKとゲート電位Vaの高低関係いかんにかか
わらずサイリスタを点弧できる。以下、3種類の電位関
係に分類して説明する。なお、nu 3J−のMOSゲ
ート電極7とその端子G^を一括してOp、pB4上の
MOSゲート電極19とその端子GKを一括してGnと
記述することにする。
As mentioned earlier, this device operates at a predetermined potential V while the thyristor is in a forward bias state and the gate terminal G^ is open.
When set to o, the thyristor can be fired regardless of the level relationship between the anode potential V^ and cathode potential VK of the thyristor and the gate potential Va. Hereinafter, three types of potential relationships will be classified and explained. Note that the MOS gate electrode 7 of nu 3J- and its terminal G^ will be collectively described as Op, and the MOS gate electrode 19 on pB4 and its terminal GK will be collectively described as Gn.

(1)v^がVoより低電位の場合 MOSトランジスタpp ns pa部分はMOSゲー
ト電1m G p下のnu3の蓄積化が促進され駆動さ
れない。一方、縦形MOSトランジスタn[! PBn
B部分はVaとPR電位の差がしきい値電圧より大きい
とMOSゲート電極電極上n下チャネルが形成される。
(1) When v^ is a lower potential than Vo, the MOS transistor pp ns pa portion is not driven because the accumulation of nu3 under the MOS gate voltage 1mGp is promoted. On the other hand, vertical MOS transistor n[! PBn
In the B portion, when the difference between Va and PR potential is larger than the threshold voltage, an upper n lower channel of the MOS gate electrode is formed.

この結果、アノード端子A−)pE4→ne→nチャネ
ル→npl→カソード端子にの経路で電流が流れ、この
電流がトリガとなっていわゆる公知のサイリスタのアノ
ードゲート駆動機構でもってサイリスタが点弧する。
As a result, a current flows through the path from the anode terminal A-) pE4 → ne → n channel → npl → cathode terminal, and this current serves as a trigger to fire the thyristor using the so-called known thyristor anode gate drive mechanism. .

(2)vにがVoより高電位の場合 縦形MO8)−ランジスタnE pa n8部分はMO
Sゲート電゛極Gn下のpa 2及びp−16の蓄積化
が促進され駆動されない。一方、横形MOSトランジス
タpE nu p8部分はVoとnB電位の差がしきい
値電圧より大きいとMOSゲート電極GP下にpチャネ
ルが形成される。
(2) When v is higher potential than Vo, vertical MO8) - transistor nE pa n8 part is MO
Accumulation of pa2 and p-16 under the S gate electrode Gn is promoted and is not driven. On the other hand, in the lateral MOS transistor pE nu p8 portion, when the difference between the Vo and nB potentials is larger than the threshold voltage, a p channel is formed under the MOS gate electrode GP.

この結果、アノード端子A→ps4→Pチャネル→pB
→抵抗12→カソード端子にの経路で電流が流れ、この
電流がトリガとなっていわゆる公知のサイリスタのカソ
ードゲート駆動機構でもってサイリスタが点弧する。
As a result, anode terminal A → ps4 → P channel → pB
A current flows through the path from →resistor 12 →cathode terminal, and this current serves as a trigger to fire the thyristor using a so-called known thyristor cathode gate drive mechanism.

(3)(1)、(2)以外の場合すなわちVoがVAよ
り低電位でvKより高電位の場合(1)、(2)のいず
れかの機構でサイリスタが点弧する。
(3) In cases other than (1) and (2), that is, when Vo is at a lower potential than VA and higher than vK, the thyristor is fired by either mechanism (1) or (2).

本実施例の場合、ゲート電極7下の酸化膜厚を0.4μ
m、ゲート電極19下の酸化膜厚を0.3μmとし抵抗
12を約6にΩとすることにより、各々約3.5v及び
4.5V(7)電位差(−VA −Va )を形成する
ことによりサイリスタのアノード・力ソード端子電位と
ゲート電位の関係いかんによらずサイリスタを点弧でき
た。サイリスタのオン電圧は100mA通電時に1.2
v、オン抵抗は8Ωであり実用上全く問題のないもので
ある。
In the case of this example, the oxide film thickness under the gate electrode 7 is set to 0.4 μm.
By setting the oxide film thickness under the gate electrode 19 to 0.3 μm and setting the resistor 12 to about 6 to Ω, potential differences (-VA - Va ) of about 3.5 V and 4.5 V (7) are formed, respectively. As a result, the thyristor could be fired regardless of the relationship between the thyristor's anode/power sword terminal potential and the gate potential. The on-voltage of the thyristor is 1.2 when 100mA is applied.
v, on-resistance is 8Ω, which poses no practical problem.

第4図は本発明になる第4の実施例のMO8電界効果形
ラテラルサイリスタを示す。
FIG. 4 shows an MO8 field effect lateral thyristor according to a fourth embodiment of the present invention.

第1の実施例において高耐圧ダイオード9゜12を高耐
圧nチャネルMO8−FET20゜23に置換した点を
除けば第1の実施例と同じ素子構成である。本装置のオ
フ状態における高耐圧を実現する機構は次のとおりであ
る。サイリスタが順バイアス時にnチャネルMO8−F
ET20はソース・ゲート間が短絡されており、p層の
電位よりも高電位がゲート電極に印加されることになる
のでチャネルが形成されオンする。一方n形MO8−F
ET23はソース・ゲート間が短絡されているがp層の
電位と略等電位がゲート電極に印加されることになるの
でオフのままである。この結果ゲート電極7にはアノー
ドと同等の高電位が現われnB3と略等電位になるので
na 3へのチャネルの発生が抑えられ、高い順方向耐
圧を実現できる。次にサイリスタが逆バイアス時にはn
チャネルMO5−FET23はソース・ゲート間が短絡
されておりp層の電位よりも高電位がゲート電極に印加
されることになるのでチャネルが形成されオンする。一
方nチャネルMO8−FET20はソース・ゲート間が
短絡されているがp層の電位と略等しい電位がゲート電
極に印加されることになるのでオフのままである。この
結果ゲート電極7にはカソードと同等の高電位が現われ
na 3と略等しい電位になるのでnflへのチャネル
の発生が抑えられ高い逆方向耐圧を実現できる。
The device configuration is the same as that of the first embodiment except that the high breakdown voltage diode 9.12 in the first embodiment is replaced with a high breakdown voltage n-channel MO8-FET 20.23. The mechanism for achieving high withstand voltage in the OFF state of this device is as follows. n channel MO8-F when thyristor is forward biased
The source and gate of the ET 20 are short-circuited, and a higher potential than the potential of the p-layer is applied to the gate electrode, so a channel is formed and turned on. On the other hand, n-type MO8-F
Although the source and gate of ET23 are short-circuited, a potential approximately equal to the potential of the p-layer is applied to the gate electrode, so it remains off. As a result, a high potential equivalent to that of the anode appears on the gate electrode 7 and becomes approximately equal to nB3, so that the generation of a channel to na3 is suppressed, and a high forward breakdown voltage can be realized. Next, when the thyristor is reverse biased, n
The source and gate of the channel MO5-FET23 are short-circuited, and a potential higher than the potential of the p-layer is applied to the gate electrode, so that a channel is formed and turned on. On the other hand, although the source and gate of the n-channel MO8-FET 20 are short-circuited, a potential approximately equal to the potential of the p-layer is applied to the gate electrode, so it remains off. As a result, a high potential equivalent to that of the cathode appears on the gate electrode 7, which becomes a potential substantially equal to na3, so that the generation of a channel to nfl is suppressed and a high reverse breakdown voltage can be realized.

次に本装置の点弧動作機構を説明する。サイリスタ部が
順バイアス時にゲート端子Gにアノード電位よりも低電
位を印加するとnチャネルMO8・FET20がオンす
るのでアノード→MO8・FET20→抵抗21→ゲー
ト端子の経路で電流が流れる。nチャネルMO8−FE
T20のオン抵抗及び抵抗21の値が十分高いと微小電
流を流すだけでpHnB pHより構成されるpチャネ
ルMOS −FETのしきい値電圧以上にできn8表面
にpチャネルを形成できるのでアノード端子A→pE4
→Pチャネル→pn 2→抵抗13→カソード端子にの
経路で電流が流れ、いわゆる公知のカソードゲート駆動
機構でサイリスタが点弧する。
Next, the ignition mechanism of this device will be explained. When the thyristor section is forward biased and a potential lower than the anode potential is applied to the gate terminal G, the n-channel MO8/FET 20 is turned on, so a current flows through the path of the anode -> MO8/FET 20 -> resistor 21 -> gate terminal. n-channel MO8-FE
If the on-resistance of T20 and the value of the resistor 21 are sufficiently high, the threshold voltage of the p-channel MOS-FET consisting of pHnB can be increased simply by passing a small current, and a p-channel can be formed on the surface of n8, so that the anode terminal A →pE4
A current flows along the path →P channel →pn 2 →resistance 13 →cathode terminal, and the thyristor is fired by a so-called known cathode gate drive mechanism.

本実施例の場合、第1の実施例のダイオードに比べてM
OS−FET20及び23のオン抵抗を容易に大きくで
き□るので、抵抗21及、び22の抵抗値を小さくして
も−等の微小電流を□アノ、−ド・ゲート両端子A、G
間に流すのみでサイリスタを7.□5いうゆ□あ、。−
□。:、、1よ、。8・FETに比べ同じ抵抗値を実現
する上で占有面積が大きいので本装置をIC化した場合
、全体の占有面積を実施例1よりも小さく一一″るもの
である。
In the case of this embodiment, compared to the diode of the first embodiment, M
Since the on-resistance of OS-FETs 20 and 23 can be easily increased □, even if the resistance values of resistors 21 and 22 are reduced, minute currents such as □ anode, - gate terminals A, G
The thyristor can be adjusted to 7. □5 Say □ Ah. −
□. :,,1. Since the device occupies a larger area compared to an 8-FET to achieve the same resistance value, if this device is integrated into an IC, the overall area it occupies will be 11'' smaller than that of the first embodiment.

以上、4実施例にもとづいて本発明の効果と詳細を説明
したが1本発明はこれらの1実施例に限定されるもので
はなく各種の変形応用が可能である。
Although the effects and details of the present invention have been described above based on four embodiments, the present invention is not limited to these one embodiment, and various modifications and applications are possible.

例えば主スィッチであるサイリスタは順逆両方向の耐圧
が必要なpチャネル・ラテラルMO8・FETでもよい
。又、第4の実施例におけるnチャネルMO8−FET
はpチャネルMO8−FETやバイポーラトランジスタ
等の他の整流機能を有する素子でもよく、且つ第1.第
3の実施例の抵抗11や第4の実施例の抵抗22は削除
してもよい。又部4の実施例でMOS−FET20,2
3としてオン抵抗□の十分大きい素子を用いることによ
り抵抗21.2’*を削除することができる。更に、主
スィッチがラテラル構造の実施例について言′I!tシ
たが、電力用サイリスタ等のような縦形構造にしてもよ
い。□ □また、各装置は、I’C化する場合誘電体絶縁分離基
板でなく、′pn接合分離基板等、各種の分離基□、板
トおいて実現できる。
For example, the thyristor serving as the main switch may be a p-channel lateral MO8 FET that requires voltage resistance in both forward and reverse directions. Also, the n-channel MO8-FET in the fourth embodiment
may be an element having another rectifying function such as a p-channel MO8-FET or a bipolar transistor, and the first . The resistor 11 of the third embodiment and the resistor 22 of the fourth embodiment may be deleted. In addition, in the embodiment of section 4, MOS-FET20,2
By using an element with a sufficiently large on-resistance □ as the resistor 21.2'*, it is possible to eliminate the resistor 21.2'*. Furthermore, let's talk about an embodiment in which the main switch has a lateral structure! However, it may also be a vertical structure such as a power thyristor. □ □ Also, when each device is converted into an I'C, it can be realized using various isolation substrates or plates such as a pn junction isolation substrate instead of a dielectric insulation isolation substrate.

〔発明の効果〕  5 ゛ 以上、本発明によれば、電界効果形半導体装置にお
いてゲート電極の帯電をおさえることができるので、順
逆両方向の耐圧をともに向上できるという効果がある。
[Effects of the Invention] 5. As described above, according to the present invention, since charging of the gate electrode in a field effect semiconductor device can be suppressed, the withstand voltage in both forward and reverse directions can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明になる第1の実施例であるMO5電界効
果形ラテラルサイリスタの断面図、第2図。 第3図、第4図は各々本発明になる第2.3.4の実施
例であるMO8電界効果形ラテラルサイリスタの断面図
、第5図は公知例であるラテラルMO8−FETの断面
図である。 1.2,3.4−・・サイリスタのnl! * PB+
 rlB。 pE層、5,6.8・・・サイリスタのカソード、ゲー
ト、アノード電極、7・・・MOSゲート電極、9゜1
2・・・ダイオード、10,11..13・・・抵抗。 104・・・シリコン酸化膜。
FIG. 1 is a sectional view of an MO5 field-effect lateral thyristor according to a first embodiment of the present invention, and FIG. 3 and 4 are cross-sectional views of an MO8 field-effect lateral thyristor, which are embodiments of 2.3.4 of the present invention, and FIG. 5 is a cross-sectional view of a lateral MO8-FET, which is a known example. be. 1.2, 3.4-... Thyristor nl! *PB+
rlB. pE layer, 5, 6.8... Thyristor cathode, gate, anode electrode, 7... MOS gate electrode, 9°1
2...Diode, 10, 11. .. 13...Resistance. 104...Silicon oxide film.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基体が順次導電型が異なる少なくとも3個の
半導体層を有し、両最外層にそれぞれ主電極、中間の層
に絶縁膜を介してゲート電極が設けられた半導体装置に
おいて、各主電極とゲート電極の間にゲート電極に向つ
て順方向となる整流機能を有する手段と抵抗成分が設け
られていることを特徴とする半導体装置。
1. In a semiconductor device in which a semiconductor substrate has at least three semiconductor layers having sequentially different conductivity types, each main electrode is provided in each of the outermost layers, and a gate electrode is provided in an intermediate layer with an insulating film interposed therebetween. 1. A semiconductor device comprising: a means having a rectifying function in a forward direction toward the gate electrode; and a resistive component provided between the gate electrode and the gate electrode.
JP18962685A 1985-08-30 1985-08-30 Semiconductor device Pending JPS6251260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18962685A JPS6251260A (en) 1985-08-30 1985-08-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18962685A JPS6251260A (en) 1985-08-30 1985-08-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6251260A true JPS6251260A (en) 1987-03-05

Family

ID=16244442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18962685A Pending JPS6251260A (en) 1985-08-30 1985-08-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6251260A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124065A (en) * 1989-10-06 1991-05-27 Toshiba Corp Integrated circuit element
EP0616365A1 (en) * 1993-03-18 1994-09-21 ABB Management AG MOS-controlled power semiconductor device
US5389811A (en) * 1994-04-14 1995-02-14 Analog Devices, Incorporated Fault-protected overvoltage switch employing isolated transistor tubs

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124065A (en) * 1989-10-06 1991-05-27 Toshiba Corp Integrated circuit element
EP0616365A1 (en) * 1993-03-18 1994-09-21 ABB Management AG MOS-controlled power semiconductor device
US5389811A (en) * 1994-04-14 1995-02-14 Analog Devices, Incorporated Fault-protected overvoltage switch employing isolated transistor tubs

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