JPS6250313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal head in which a silicon chip having a driving circuit for the heating elements and a shift register is mounted on the head in which a plurality of heating elements are arranged in a straight line.

Conventional thermal heads, for example, have 32 dots in one
Since the blocks are divided into a plurality of blocks and each block is sequentially driven, the recording speed is slow.

Therefore, one of the thermal heads capable of high-speed recording
Recently, a silicon chip containing a shift register and a drive circuit for a heat generating element has been mounted on the same head as the heat generating element using a film carrier. , 5m due to poor heat dissipation
Temperature rise has been a problem with high-speed drive such as sec/line. Furthermore, if all dots are driven at once,
Wiring has become difficult because a large current flows through the ground wire.

The present invention solves the problem of heat dissipation, which is a disadvantage of film carriers, and the problem of grounding lines, which is a disadvantage of silicon chips with built-in shift registers.
This will be explained using the drawings of FIGS. 1 to 5.

FIG. 1 shows the mounting state of a silicon chip of a thermal head according to the present invention. In the figure, 1 indicates a plurality of heating elements arranged in a straight line, and 2 indicates one end of this heating element 1 connected to a power source. Common leads 3 for connection are MN silicon chips containing 32 sets of serial-in/parallel-out shift registers and heating element drive circuits, and one end is connected to the 32 heating elements 1. 4 is N gate lines, and the first gate line 4 is connected to the first to Mth silicon chips 3.
In the second case, one gate line 4 is connected to the (M+1)th to 2Mth silicon chips 3, and so on.
M silicon chips 3 are connected to. FIG. 1 shows the case where M=2. A signal line 5 is connected to the signal input terminal D.IN of the first, (M+1), (2M+1), . . . silicon chips 3.

5' is the i-th signal line (where i=M,
2M......) silicon chip 3 signal output terminal
D.OUT and (i+1)th silicon chip 3
This is to connect to the signal input terminal D.IN of the.
6 and 6' are two clock lines, and the clock line 6 is connected to the clock terminals CLK of the first to Mth and (2M+1)th to 3Mth silicon chips 3, and the clock line 6 is ' is the (M+1)th to 2Mth
It is connected to the clock terminal CLK of the silicon chips 3, (3M+1)th to 4Mth silicon chips 3. 7 is the power supply line of the logic circuit, 8 is the ground line,
These are connected to the power supply terminal Vcc and the ground terminal GND of the entire silicon chip 3, respectively.

In the circuit shown in FIG. 1, an image signal is inputted from a signal line 5, and is inputted to a 32 Mbit shift register of M silicon chips 3 by a clock signal inputted from a clock line 6. Next, when a signal is applied to the first gate line 4, the silicon chip 3 connected to that gate line 4 is activated for that period.
The drive circuit for the 32M-bit heating element is driven, and a voltage is applied to the heating element 2.

At the same time, the next image signal is input to the 32 Mbit shift registers of the M silicon chips 3 by the clock signal from the clock line 6'. Then, when a signal is applied to the next second gate line 4, the drive circuit of the silicon chip 3 connected to that gate line 4 is driven for that period, and a voltage is applied to the heating element 2.

In this way, the heating elements 2 connected to the M silicon chips 3 can be sequentially applied with voltage to generate heat as one unit. In addition, M
=1, gate line 4, clock line 6,
6' need only one line each, which corresponds to the case of printing all dots at once.

As is clear from FIG. 1, in such a thermal head, when the silicon chip 3 is mounted on the same head on which the heating elements 1 are arranged, multilayer wiring is required between the silicon chip 3 and various wirings on the head. It requires.

The present invention solves these drawbacks, and first, the structure of a thermal head according to the present invention will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows the heat generating elements and various wirings in five silicon chips, and the same parts as in FIG. 1 are given the same numbers.

That is, in the thermal head of the present invention, a plurality of gate lines 4 are provided at the farthest positions from a plurality of heat generating elements 1 arranged in a straight line, and a ground line 8 is provided at the closest position parallel to the heat generating elements 1. form,
In the region between the plurality of gate lines 4 and the ground line 8, at least signal lines 5, 5', two clock lines 6, 6', and a power supply line 7 for the logic circuit are arranged.

Here, the first one of the gate lines 4 is
The second silicon chip may be placed at the closest position to the heating element 1 and has a length that can be connected to the gate terminal Gate of the first to Mth silicon chips 3. It is sufficient that it has a length that can be connected to the gate terminal Gate of the (M+1) to 2Mth silicon chips 3, and the Nth silicon chip is placed farthest from the heating element 1, and the length is the same as that of the heating element 1. Almost equal to the array length of 1. Further, the length of the grounding wire 8 is also approximately equal to the array length of the heating elements 1.

Furthermore, the signal line 5 is the first one, the (M+1)th one
The signal line 5' is connected to the signal input terminal D.IN of the i-th silicon chip 3, and the signal line 5' is connected to the signal output terminal D.OUT of the i-th silicon chip 3. and the signal input terminal D.IN of the (i+1)th silicon chip 3. Further, the clock lines 6 are the 1st to Mth, the (2M+1)th to 3Mth, . . .
..., and the clock line 6' is connected to the clock terminal CLK of the silicon chip 3 of...
+1) pieces to 2Mth pieces, (3M+1) pieces to 4Mth pieces
Eye, clock terminal of silicon chip 3
Placed to connect to CLK. Further, the power line 7 and the ground line 8 are arranged so as to be connected to the power terminal Vcc and the ground terminal GND of all the silicon chips 3, respectively.

Figure 3 shows 5 mounted on a film carrier.
A silicon chip 3 is shown corresponding to FIG. 2, and the silicon chip 3 has at least a serial-in/parallel-out shift register and a drive circuit for the heating element 2, and at least a gate terminal and a signal It has an input terminal D.IN, a signal output terminal D.OUT, a clock terminal CLK, and a logic circuit power supply terminal Vcc, and can be grounded on the back side. These various terminals are connected to a copper finger 9 consisting of a group of L-shaped conductors arranged in a row at one end of the silicon chip 3, and drive terminals for the 32 heating elements 1 are connected to the other end of the silicon chip 3. Copper fingers 10 to be connected are arranged. Further, the bold line portions of the copper fingers 9 and 10 in FIG. 3 indicate the connection points with various wirings in FIG. 2, and the connection points on both sides of the silicon chip 3 are orthogonal. Gate terminal Gate is connected to gate line 4, signal input terminal D.IN is connected to signal line 5, signal output terminal D.OUT is connected to signal line 5', and clock terminal CLK is connected to clock line 6.
The power supply terminal Vcc is connected to the power supply line 7, and the back surface of the chip is connected to the ground line 8.

That is, the silicon chip shown in FIG.
By connecting with the various wirings shown in the figure, the equivalent circuit shown in FIG. 1 can be satisfied. Therefore, even if multilayer wiring is not specifically formed, multilayer wiring can be equivalently formed by utilizing the three-dimensional arrangement of various wirings and silicon chips, and the connection shown in Figure 1 can be achieved. can do.

FIG. 4 shows a specific structure of a thermal head according to an embodiment of the present invention. In the figure, copper fingers 9 and 10 are made of polyimide insulating film 1.
1 is held above. Copper fingers 9 made of an L-shaped conductor group are connected to various wirings at connection parts 12, and copper fingers 10 are connected to electrodes 1' of heating element 1 at connection parts 13. Here, since the gate lines 4 are arranged in a wide area, there are no restrictions on the number of lines, and since the ground lines 8 are arranged in a wide area under the silicon chip 3, the conductor resistance can be lowered.

Further, the electrode 1' and the connection part 13 of the heating element 1 are on the same substrate as the heating element 1, but the various wirings are located on the same substrate as the heating element 1, with the line A-A' in FIG. It is not necessary to do so, and various wirings may be formed on a separate substrate such as a printed circuit board or a ceramic substrate.

FIG. 5 shows an example of the mounting state of the silicon chip 3 part in FIG. Yes, the ceramic substrate 1
It may be the same substrate as 4.

The back side of the silicon chip 3 is soldered through a nickel film, and a ground wire 8 made of copper foil, thick film conductor, or thin film conductor is connected to the substrate 15.
The connection is fixed by solder reflow.

Here, the method for die-bonding the inner lead bonded silicon chip 3 to the conductor of the film carrier will be described. First, the copper fingers 10 are connected at the connecting portion 13 by outer lead bonding.

Next, the center of the surface of the silicon chip 3 is heated with a heated tool and left for a few seconds to melt the solder and connect the ground wire 8 and the silicon chip 3. Then, the tool is cooled and lifted several seconds after the temperature drops below the melting point of the solder, completing the die bonding. Thereafter, outer lead bonding is performed on the tip of the copper finger 9 consisting of an L-shaped conductor group. Since the arrangement density of the tips of the copper fingers 9 is as low as 2 fingers/mm, misalignment during die bonding poses no problem at all. Note that the die bonding may be performed using a conductive resin method.

According to such a thermal head of the present invention,
The following effects can be obtained.

(1) Die-bonding improves heat dissipation characteristics, and mounting a silicon chip using a film carrier enables drive at 5 msec/line.

(2) Die-bonding simplifies the process of wiring the ground wire, eliminating the need for a grounding finger on the film carrier.

(3) Grounding resistance can be reduced because the entire back surface of the silicon chip can be grounded.

(4) There is no need for a grounding wire for the silicon chip, and the wiring area is significantly reduced.

(5) The back side of the silicon chip can be effectively used for grounding, enabling high-density packaging.

(6) Multilayer wiring can be equivalently realized without specifically forming multilayer wiring.

(7) Since various wiring lines such as signal lines and gate lines are all parallel, there are no short circuits or disconnections in the wiring, and the yield can be increased.

In the embodiment of the present invention, a case has been described in which all the heating elements are connected to one common lead 2, but of course the common lead 2 may be divided into a plurality of groups.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the mounting state of a silicon chip in a thermal head related to the present invention, and FIG.
3 is a schematic diagram showing a silicon chip incorporated in the circuit of FIG. 2, and FIG. 4 is a specific structure of a thermal head according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing an example of a silicon chip die-bonded to a film carrier in the thermal head of the present invention. 1... Heat generating element, 3... Silicon chip, 4...
...gate line, 5,5'...signal line, 6...clock line, 7...power supply line, 8...ground line, 9,10...
...copper fingers.

Claims (1)

[Claims] 1. A plurality of heating elements arranged in a straight line;
The silicon chip has a built-in drive circuit and a shift register for the heat generating element, and has a group of L-shaped conductors that are inner lead-bonded to the power supply terminal, gate terminal, signal terminal, and clock terminal of the logic circuit. A ground line and a gate line connected to the ground terminal and gate terminal of the chip are formed by arranging the ground line at a position close to the heating element and the gate line at a distant position parallel to the arrangement direction of the heating element. At the same time, a power line, a signal line, and a clock line are formed between the ground line and the gate line to be connected to the power terminal, signal terminal, and clock terminal of the silicon chip, respectively. A thermal head characterized in that a group of conductors connected to a signal terminal and a clock terminal are connected to the power supply line, the gate line, the signal line and the clock line, respectively, and the back surface of the silicon chip is die-bonded to a ground line. 2. The thermal head according to claim 1, wherein the power line, ground line, gate line, signal line, and clock line are formed on a substrate different from the substrate on which the heating element is formed.