JPS58153672A - Recording head with built-in thin film transistor circuit - Google Patents

Abstract

PURPOSE:To eliminate the individual bonding of an integrated circuit chip and each lead of recording elements and to make it possible to perform connection of a photolithography process, by forming the thin film transistor circuit on the same substrate for the recording elements (heating resistor bodies) instead of an integrated circuit chip. CONSTITUTION:In the recording head wherein a plurality of recording elements (e.g. heating bodies) 1a1-1a9 are arranged, driving amplifiers 471-499, which drive the driving elements 1a, and recording control circuits 451-459, 44, and 43, which control the amplifiers in response to a picture signal, are constituted by the thin film transistors 51-56. The recording elements 1a and the thin film transistors 51-56 are arranged on the same substrate 57. For example, the thin film transistor, which comprises a semiconductor thin film 51, source and drain electrodes 52, an insulating film 53, a gate electrode 54, and the like, is provided on the substrate 57. The thin film material of the semiconductor thin film 51 and the source or drain electrode 52 are elongated and the thin film resistor 58 is constituted. Thus the thin film transistor circuit and the heating resistor body are simultaneously formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording head used in facsimile machines, printers, etc., and specifically relates to a recording head incorporating a thin film transistor circuit.

In recent years, scanning reliability,
Due to its high speed and simplicity, solid-state scanning methods, in which scanning is performed electronically, have become mainstream. Fax 1
Regarding the imaging system at the uli 1 position, most of the devices that use electrostatic imaging or recognition imaging as a recording method employ a solid-state scanning system.

Hereinafter, explanation will be given taking a heat-sensitive arrangement as an example.

FIG. 1 is a diagram showing a thermal head and its scanning drive circuit in a conventional thermographic image. In this figure, 1 is a thermal head, 1a is a thermal resistor, 1b is a matrix diode,
2 is an M-bit shift register, 3 is a latch circuit, 4 is an AND circuit, 2 is an energization time setting circuit, 6 is a 1/M 4-cycle generator, 1 is an N-bit) shift register, 8 is an X-side driver,
S is a Y driver, and also a CLK signal and a P
IX is one signal, and PH8 is a synchronization signal.

The operation shown in FIG. 1 will be briefly explained as follows. The shift register 2 outputs the image signal P in synchronization with the p-switch signal CLKK.
Read IX in l piF increments and generate M-bit image signal PIX
Once accumulated, it is transferred in parallel to the latch circuit 3 in synchronization with the output of the l/M frequency divider 6. At this time, the energization time setting circuit S energizes the AND circuit 4 for a predetermined time, so during that period, the M X-side drivers 8 are selectively turned on in response to one signal P I XM of the latch circuit 3. It will be done.

On the other hand, the N-bit shift register 7 reads the synchronizing signal P)1B generated every time one line is scanned, and transfers it to 17M
The N Y-side drivers S are selectively turned on by shifting to the right in synchronization with the output of the frequency divider 6. Therefore, for example, Y
When the l Y-Yu driver is turned on, the common KIII
! The M number of wired heating resistors 1a are xl...
The image signal P of the latch circuit 3 is transmitted through each X side driver 8 of XM.
Electricity is applied to generate heat according to IXK. Similarly below,
M clock KY 婁# Y@ ＊ ・・・・・・IY
4M commonly connected to each Y side driver 9 of N
One field of heating resistors is sequentially energized to generate heat.

FIG. 2 shows a conventional specific configuration example of the thermal head 1.
11 is a high resistance substrate, 11 is a 1-trix wiring section, 12 is a diode chip in which the matrix diodes 1b&M are integrated, 13 is a group of X side input terminals, and 14 is a group of Y input terminals. By the way, in the case of this FIG.
This requires wiring processing and bonding of a large number of diode chips 11. Both of these steps are time-consuming and are one of the factors that increase the price of the thermal head 1.

FIG. 3 shows the bonded diode chip 12, where 1s is the bonded X side terminal, 16 is the bonded Y side terminal, 17 is the X side lead, and 18 is the bonded diode chip 12.
is the Y side. The matrix diode 1b needs to be connected to the heating resistor 1a by 1K. For example, if the arrangement density of the heating resistor 1a is 8/mm and the number of l blocks is 32, the X side terminal 15 and the X side lead 1T
It is necessary to connect 32 points at a density of 8 points/mm 2 per l chip.

In the past, although it took a lot of effort to actually cut the diode chip 12, the diode chip 1
The internal circuit of No. 2 only has XM matrix diodes 1b integrated as shown in FIG. 311, and in order to drive the thermal head 1, a scanning drive circuit as shown in FIG. However, it turned out to be expensive overall.

The fourth @ shows a second example of the conventional thermal head 1'. In this figure, 1s is an integrated circuit chip for image signal distribution;
20 is an image signal input terminal, 21 is a single signal input terminal,
22 is a synchronization signal input terminal, 23 is a 1/M branch signal input terminal, 24 is an energization time setting signal input terminal, 25 is a power supply terminal for the integrated circuit chip IS, 26 is a ground terminal;
T is a recording voltage supply terminal, and 2I is a connector. There are N chips in the integrated circuit chip 19, and it corresponds to the image signal PIXK.

Selecting M heating resistors 1a per l chip,
The heating resistor 1aK is energized for a predetermined period of time.

As is clear from FIG. 4, this recording head does not have a matrix arrangement 4111111 as shown in FIG. 2, and the external circuitry is much simpler than that in FIG. #I1. On the other hand, although the internal circuit of the integrated circuit chip 19 is somewhat complicated,
The chip mounting method is matrix diode 1b in Figure 3.
This is almost the same as in the case of , and since the scanning drive circuit is built-in, it is advantageous in terms of miniaturization of the image arrangement. In addition, each terminal 20-
27 is an example, and is set according to the internal circuit of the integrated circuit chip 91@.

FIG. 5 is a diagram showing an example of the internal circuit of the integrated circuit board 1s. In this figure, 211 to 32 constitute an image signal distribution circuit, 2s is an M-bit shift register, 30.31 is an AND circuit, and 32 is a D-type flip 7p tube. Reference numeral 33 indicates a gate circuit (AND circuit) for controlling the output of the two shift registers, and reference numeral 34 indicates M driver circuits. Further, 35 to 40 are input/output terminals for various control signals, 35 is an input terminal for the above-mentioned - signal PIX, 3 is an input terminal for the above-mentioned clock signal CLK, and 3T is an input terminal for the above-mentioned synchronization signal P
An input terminal of H8, 3- is an output terminal of a synchronization signal PH8 to be supplied to the next stage integrated circuit chip 19, 39 is an input terminal of a signal MCLK obtained by dividing the clock signal CLK by 1/M,
40 is an input terminal for a timing signal T for setting the energization time, and 41 is an input terminal of the image signal distribution circuit shown by 2-33.
The input terminal for the power supply voltage VCC for the LA path, 42, is a ground terminal. Among the terminals 3s to 42, the input terminal S7. Terminals other than output terminal 3@ are commonly connected between chips. This thermal head 1'' is built into an integrated circuit chip 19 on which a large number of image signal distribution functions are mounted, and has higher functionality than the thermal head 1 shown in FIG. , the number of bonds during the head tower battle is reduced.However, a large number of heat generating resistors 1a and bonding are still required, the absolute number is large, and the disadvantage is that such a high-performance integrated circuit chip 1s of J3 is expensive. There is.

This invention was made to eliminate the above-mentioned drawbacks, and instead of the conventional integrated circuit chip (a thin film transistor circuit is formed on the same surface as the arrangement elements, the trouble of bonding is eliminated.Hereinafter, A detailed description of the invention will be given with reference to the drawings.

FIG. 6 is a diagram showing one embodiment of the present invention, in which nine heating resistors of 1 ml to 1a are driven. In this figure, 43 is a shift register, 44 is a latch circuit, 45. to 4L is an Y gate F, 4@ is a counter decoder, 41. to 41° is an output transistor, 48
1 to 4 are level shifters, 491 to 4I are signal terminals, and SO is a power supply terminal. Image signal PIX is signal terminal 40
．． The signal is then input to the shift register 43 via the level switch 411m. Shift register 4sxt lines (
When the input of data (in this case 9 bits) is completed, all the data is transferred to 44 km of latch circuits and held by the strobe signal input from the signal terminal 411g. The data held in the latch circuit 44 is transferred to the counter decoder 4S.
Follow the instructions of 7nd Gut 45, ~45. The output transistors 411 to 47 are driven through the predetermined heating resistors 11. ~1m.

selectively energize.

In this embodiment, the image distribution of l line is divided into ts times, and the reset F signal from the signal terminal 491 and the signal terminal 4
Shift kurtsuk signal from 9s.

Signal terminal 49. AND gate 45. in response to a pulse width signal from AND gate 45. ~4Sm, 454~4's6.451~4s,
Each block is sequentially selected and becomes H level for a predetermined time.

The basic operation of FIG. 6 is almost the same as that of FIG. 4, but the elements constituting the circuit are different. That is, the output transistor of FIG. 6 and the logic 1lIi! The path is constituted by a thin film transistor circuit, and the heating resistor 11. ~11. is formed on the same substrate.

Therefore, as shown in Fig. 4, there is no need to individually bond the integrated circuit chip 1- and the X-side lead 17 of the heating resistor '1a, and by photoringer fibrosis etc.
Accurate and economical KII can be constructed.

FIG. 7 is a sectional view showing an example of a thin film transistor cell constituting the circuit of FIG. 6. In this figure VC, 51 is a semiconductor thin film (for example, amorphous silicon).

S2 is a source and drain electrode (e.g., a high starch n-layer such as amorphous silicon, polycrystalline silicon, etc.), 53 is an insulating film (e.g., 5tun), S4 is a gauge electrode (e.g., AI ), SS.

5@ is a lead (e.g. AI), sy is a substrate (e.g. glass, glazed glass), and the thin film material for thin film transistors is a-81 (amorphous silicon).
, polycrystalline silicon e Cd8@*T@, Tn8b, etc., but at present 1-81 is promising because it is economical because there are few manufacturing plants, and it can have a high off-resistance. In general, thin film transistors are manufactured using existing thin film formation technology (
Vapor deposition, sputtering, CVD, etc.) allows the required number of 1liIK to be formed on a relatively wide area on an insulating substrate such as glass, and mass productivity is good because no bonding is required.

Figure #18 is a cross-sectional view of the heat-generating falcon of the thermal imaging head, where SI is a thin film resistor, 5s is a lead, 60 is an oxidation-resistant layer, and -1 is an abrasion-resistant layer. *Thermal resistors 1ml to 1& are thick film or thin film resistors, but these days, dimensional accuracy is required.

For reasons such as accuracy in setting resistance values and high speed of thermal response, it is mainstream to form heat generating resistors using thin film resistors. Currently, Ta, N
+Si-Ta+Ta-8IOs etc. have been put into practical use as heating element resistance materials for thermal recording sickle heads.

If the heating resistor can be formed at the same time as the thin film transistor circuit, mass productivity will be further improved. Therefore, by using the thin film material of the semiconductor thin film S1 or the source or drain electrode s2 of FIG. 7, the thin film resistor SS of FIG.
1), the thin film transistor circuit and the heat-generating resistor can be formed at the same time. In Figure #8, 58' indicates the heat-generating portion.

Similarly, the oxidation-resistant layer @o and the wear-resistant layer-1 of the heating resistor
For example, the insulating film S3 in FIG. 7 and the oxidation-resistant layer 60 in FIG. 8 can be formed simultaneously with the thin film transistor.
0m, and a passivation film covering the entire circuit in Figure 7 and the 81st! ! The wear-resistant layer 61 of S is
If it is configured with N + T a"'j 01 etc., the heat generating part 58
The oxidation-resistant layer and wear-resistant layer can be formed simultaneously with the thin film transistor circuit.

Note that when *-81 is used for the backing 1, a laser treatment is usually performed to lower the mobility, but it takes a long time when the area is large like a recording head. Therefore, it is economical to perform laser annealing only on the surface of the recording head where the thin film transistor circuit is formed, particularly at the location where the transistor is formed, because the processing time can be shortened and it is economical.

The 9th WA is a block diagram showing the second embodiment of Takamei, and 43A to 4SA414SB1 to 43B4 are D-type flip-flops constituting the A system and B system of the shift register 43, 44A1 to 44A4°44B, -44B4 is the A system of the latch circuit 44.

D type flip-flop constituting B system @2. H is a cuttable lead, @4-841~1i 1@S嘗~654
is an AND circuit. If all seven layers of thin film transistor circuits and heat generating resistors as shown in Fig. 6 are configured on the same substrate, pinholes etc. will occur! The probability of occurrence of cause L is large, and the overall yield is reduced. Therefore, the 9th
The figure shows a redundant shift register and latch circuit. The example in FIG. 9 shows a circuit for four heating resistors, which originally consisted of flip-flops 43A3 to 43A4 and 4.
4A1 to 44A4 is enough, but 43B Karasu to 43B
4 and 44B1 to 44B4 are added as extra. If all the 7-lips are normal, the A-system and B-system ID% 7lips 70 all operate in the same way, resulting in the desired operation as a whole. However, if, for example, the D-type flip-flop 43A is defective, it will not operate normally as a whole, but the AND circuit 641 and the D-terminal of the D-type flip-flop 4mA, the proverbial Q terminal of the D-type flip-flop 4SA, and the By disconnecting the gate 63 of the AND circuit 64, normal operation is achieved as a whole. However, the AND circuit $4. -644 means that the input terminal becomes open due to disconnection, and the open terminal needs to have a configuration equivalent to an H level input.

Furthermore, the relationship between the D-type flip-flops 44A, 44A4 and 44B, 44B4, which constitute the latch circuit 44, is exactly the same. In addition, the AND circuit 65. ~654
and 45. 〜454 can be integrated and configured with an AND circuit powered by three people. Since it has such a two-electrification structure, the decrease in yield due to defects in the shift register 43 and latch circuit 44 that distributes the image signal PIXt is greatly improved. be done.

FIG. 1θ shows a cross-sectional view of the wiring location to be cut in FIG. 9, where is is the output lead (for example, the q output of the D-shaped lip prop 43A in FIG. D flip-flop p of AND circuit 64 in Figure 9
4 mA, side input), 68 is a connection lead (same as lead @ 2.6B in FIG. 9), which is formed on the badge page anti-corrosion film 6s. TO is a through hole that connects the pre-distributed cable drawer and the connection lead 6S or the input cable drawer T and the connection lead 1@. This configuration is applied to all the duplicated wiring in Figure 9.
Leads 112.63 are exposed on the surface to be cut depending on the defective location. Therefore, among the places marked as 21,
It is easy to inspect and remove defective parts; for example, if a defective part is found to be glossy during inspection after completion, a predetermined lead can be immediately cut with a laser or the like.

FIG. 11 is a block diagram showing a third embodiment of the present invention, in which 71 is an output section of a logic circuit, T2 is an image voltage supply lead, T3 is an individual lead for a heating element, and T4 is a source electrode of the output transistor 4T. , 75 is a gate electrode, 1s is an output lead from the output section 71, and T7 is a drain electrode. In the case of thermosensitive recording, it is necessary to supply a current of several lO - 410 mA to the heating resistor 1aK. When the output transistor 41 is composed of a thin film transistor, the gate electrode width (φ channel width of the FET) W depends on its output power.
becomes wider, and the arrangement pitch of the heating resistor 1a! (For example, C
G3 fax compliant with CITYK! (transmission time of version 14 is about 1 minute) is 8 dots/mn+, so 1=1
25 μm). In FIG. 11, the length direction of the gate electrodes TS is perpendicular to the arrangement direction of the heating resistors 1a, and a certain number of M pieces are arranged in N columns to form a matrix arrangement of MXN. A thin film transistor with a gate electrode width of <w can be applied.

FIG. 12 is an example in which the arrangement direction of the transistors (thin film FETs) shown in FIG. 11 is arranged obliquely with respect to the arrangement direction of the heating resistor 1m. As is clear from FIG. 12, there is an advantage that the outlet door 6 and the heating element individual leads 73 are arranged on the same plane without crossover.

Note that, for convenience of explanation, the above description has been made using a thermal image distribution device head as an example of a dispersion head, but the present invention is also applicable to recording heads other than the thermal configuration, for example, electrostatic image distribution. Needless to say, it can be used. Further, although FIG. 6 has been described as an example of the bone marking control circuit, it is not limited to this.

As explained above, this invention has the following advantages.

■ One signal distribution circuit using a thin film transistor circuit using A-8L can be formed on the substrate of one mother head, and since the individual recording elements are connected by batch wiring technology such as FOF lithography, it is possible to connect the external lead edge. There are few.

■ Since there is no need to connect multiple expensive monolithic drive ICs by bonding as in the past, it is highly suitable for mass production and is economical.

%, when applying RAD to an arrangement in which the thin film transistor circuit of the present invention is built into a thermal recording head, the heating resistor thin film as a recording element can be formed at the same time as the thin film transistor circuit, making it extremely economical. It is.

(2) Furthermore, by adding a redundant circuit configuration to the image signal distribution circuit, the overall yield is greatly improved, and the economical efficiency of the optical head according to the present invention is further improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the thermal head and its scanning drive circuit in a conventional heat-sensitive brass distribution, Figure 2 is a boot diagram showing the specific configuration of the conventional thermal head, and Figure 3 is the diode chip shown in Figure 2. 4 is a block diagram showing a second example of a conventional thermal head, FIG. 5 is a block diagram showing an example of the internal circuit of the integrated circuit chip of FIG. 4, and FIG. 6 is a block diagram showing a second example of a conventional thermal head. Fig. 7 is a cross-sectional view showing an example of a thin film transistor cell constituting the circuit of Fig. 6, Fig. 8 is a cross-sectional view of a thermal recording heating element, and Fig. 9 is a cross-sectional view showing an example of the heat recording element of the present invention. A block diagram showing the second embodiment, FIG. 10 is a sectional view showing the wiring locations to be cut in FIG. 9, FIG. 411 is a block diagram showing the third embodiment of the present invention, and FIG. FIG. 3 is a configuration diagram showing an example in which the arrangement direction of the transistors shown in the figure is arranged obliquely with respect to the arrangement direction of the heating resistors. In the figure, 1m to 1a are heating resistors, 43 is a shift register, 44 is a latch circuit, 451 to 45 are 7-nd gates, 46. ~46. is Kawanta decoder, 471-47
．． are output transistors, 411 to 48@ are level sick, 4s1 to 4s, ' are signal terminals, 50 are power supply terminals, 51
is a semiconductor thin film, S2 is a source and drain electrode, 53
is an insulating film, 54 brush-)tli, 55,511.5st
tv-code, sy is a substrate, 58 is a thin film resistor, 6o is an oxidation-resistant layer, 61 is a wear-resistant layer, @2. @3 is! - Possible leads,
64 to 644 and SS, to 654 are AND circuits, 6
6 is the output lead, sl is the input lead, 68 is the connection lead, 6s is the badge page 1 membrane, 70 is the through hole, T
1 is an output section, 72 is a recording voltage supply y-dore, 73 is a heating element individual lead, and T4 is a source electric ring. 71 is a gate electrode, T@ is an output lead, and TT is a drain electrode. 1st. Figure 2 Figure 1 4 Figure 3 Figure 4 Figure 10 Figure 6 Glaze Figure 7 Figure 8 Figure 9 Figure 10 Figure 7 Figure 11 Seal---172-

Claims (5)

[Claims] (1) In a recording head in which a large number of arrangement elements are arranged, there are a number of drive amplifiers that drive the III arrangement brass elements, and a memory head that controls the drive amplifiers according to image signals.
The control path is formed by thin film transistors, and the large number of storage elements, the large number of drive amplifiers, and the arrangement control circuits are integrated on the same substrate, and the thin film transistor path is incorporated in the control path. statue head. (2) The recording element is a thermal clouding element using a thin film resistor, and when the thin film transistor is thin, it is not formed of the same thin film material as the thin film transistor. Claim 11 Ie-head incorporating a thin film transistor path according to paragraph 11(t). (3) The thin IK# material used to form the thin film transistor is amorphous silicon, and after the thin film material is uniformly formed on the head substrate, only the active region where the thin film transistor is formed is laser annealed. A brass head incorporating a thin film transistor circuit according to claim 11 or claim 2. (4) A patent claim that divides a large number of arrangement elements and a plurality of drive amplifiers into a predetermined number of groups, and arranges each 1# in a direction perpendicular or diagonal to the arrangement direction of the arrangement elements. An imaging head incorporating a thin film transistor path according to item (1). (5) In an imaging head in which a large number of 2-brass elements are arranged, a large number of drive amplifiers that drive the 1-brass elements and a memory control path that controls the drive amplifiers according to image signals are connected by thin film transistors. forming a large number of 15-electrode elements, a large number of drive amplifiers, and a wiring control circuit on the same substrate; A thin film transistor circuit with a built-in thin film transistor circuit characterized in that the number of circuit elements is larger than that of the imaging elements.
5 heads.