JPS6249633B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit system for a thin film EL element with a memory, in which a capacitor or the like is used as a voltage source, and the voltage drop thereof is used as a full erase voltage.

Display devices using thin-film EL elements have transparent electrodes arranged in stripes on a glass substrate, and on top of this, for example,
A dielectric material such as Y ₂ O ₃ , Si ₃ N ₄ , TiO ₂ , Al ₂ O _{3 ,} etc. is further layered on top of this, for example, a phosphor layer such as Mn-doped ZnS, _ZnSe , _etc. , _{Si3N4 , TiO2} ,
A dielectric material such as Al ₂ O ₃ is deposited on each layer to a thickness of 500 to 10,000 Å using a thin film technique such as vapor deposition or sputtering, and a double-insulated three-layer structure is formed. Striped back electrodes are arranged in a direction orthogonal to the matrix to form a matrix electrode, and when one of the transparent electrode groups and one of the back electrode groups are selected and an appropriate AC voltage is applied, these two electrodes intersect. A tiny area (corresponding to one picture element on the screen) held between the two lights emits light, and by combining these lights, characters, symbols, patterns, etc. are displayed.

EL elements with this structure have superior characteristics compared to conventional distributed EL elements in terms of brightness, lifespan, and stability, but this EL element also has new characteristics that improve the applied voltage and light emission. Shows hysteresis characteristics during brightness. In other words, when a pulse with voltage amplitude V ₁ is applied as a sustaining voltage, the brightness decreases to the low level brightness B ₁
It is in. Here, the sustaining voltage V ₁ is set to be V ₁ >Vth, where Vth is the emission threshold voltage. The brightness is maintained at B ₁ during the period of continuous application of the maintenance voltage V ₁ . Next, when the write voltage V ₂ (V ₂ > V ₁ ) is applied, the brightness increases all at once to the high level brightness B ₃ , and thereafter, even if the voltage returns to the maintenance voltage V ₁ again, the brightness remains the same as before. B ₁
The brightness settles to _B2 , which is greater. The brightness is maintained at _B2 by continuous application of the sustaining voltage _V1 . In this state, when the erase voltage V ₃ (V ₃ <V ₁ ) is applied next, the brightness level decreases rapidly, and when it is returned to the sustaining voltage V ₁ again, it settles to the previous low level of brightness B ₁ . This hysteresis phenomenon can take any small loop depending on the amplitude, pulse width, and pulse frequency of the write voltage. That is, it is also possible to display halftones.

In this way, once a write voltage or an erase voltage is applied, each picture element continues to emit light without losing the gradation given by the sustain pulse.
This is a major feature that other display devices do not have. The above voltages vary greatly depending on the physical conditions of composition and film thickness, manufacturing conditions, and applied waveform, but in a prototype example, Vth = 200V, V ₁ = 210V, V ₂ = 210 ~
The values are 280V and V ₃ = 190V.

The drive circuit for this thin film EL panel was developed by the present inventors in Japanese Patent Application No. 52-126948 entitled "Drive Circuit for Thin Film EL Element".
and Japanese Patent Application No. 52-130529 ``Driving circuit for thin film EL element'', this is shown in FIG. 1 as a prior invention and will be described below.

Reference numeral 10 denotes the thin film EL element, in which column (X) electrodes X ₁ to X _n are made of transparent electrodes 11 and row (Y) electrodes Y ₁ to Y _o are made of aluminum electrodes 12.
only shown.

Reference numeral 20 denotes a circuit that supplies a positive sustaining voltage V _s1 to the Y electrode from the power supply line A, and is composed of transistors 21 and 22 operated by the sustaining signal T ₁ .
Y ₁ to _{Y o} are the diodes 23 connected to each electrode,
23,...

A circuit 30 connects all the X electrodes to ground during sustain drive, and is comprised of a transistor 31 operated by a sustain signal _T4 , and is connected to each of the electrodes _X1 to _Xn via diodes 32, 32, . . .

40 is a circuit that supplies a positive sustaining voltage V _s1 from line B to all X electrodes, and transistor 4 is operated by a sustaining signal T ₃ applied to line C.
1 and 42, and are connected to each of the electrodes X ₁ to X _n via diodes 43, 43 .

50 is a circuit that connects all Y electrodes Y ₁ to Y _o to the ground, and each electrode is connected to a transistor 5 operated by a sustain signal T ₂ via diodes 51, 51, . . .
Connected to 2.

Reference numeral 60 denotes a switching circuit for selecting Y electrodes Y ₁ to _{Y o} , which includes high voltage P-type switching transistors 61, . . . and diodes 62, . is connected, and the transistor 61 is selectively operated by a decoder (not shown) operated by a vertical binary address signal. The decoder drives the base of the transistor 61 directly with a high voltage transistor, or shifts the level of the binary address signal using an opto-isolator, etc., and drives the base of the transistor 61 with an output of about 5 volts.
configured to drive the base of the A write voltage, an erase voltage, and a read voltage are selectively output to the power supply line D according to the operation mode of the thin film EL element, and the various voltages are applied to one of the selected Y electrodes through one of the transistors 61. Apply.

Reference numeral 70 denotes a switching circuit that leads the X electrode to the ground, and high voltage N-type transistors 71, . . . are connected to each of the electrodes X ₁ to _{X n} between the electrodes X ₁ to _{X n} and the ground. The base of this transistor has a write signal
WRITE and ERASE signals are applied via analog switches (not shown) operated by horizontal pinary address signals. These transistors 71, . . . act as switching elements for selecting electrodes during writing, erasing, and reading.

The operation of this drive circuit will be explained with reference to the time chart shown in FIG.

Γ Maintain Drive At the first timing, the signal T ₁ is applied to the circuit 20 and the signal T ₄ is applied to the circuit 30. Therefore, the sustaining voltage V _s1 is the transistor 22→
It is applied via the diode 23,...→Y electrode→X electrode→diode 32,...transistor 31.

At the second timing, the signal T ₂ is applied to the circuit 50, and the diode 44→diode 43,...→X
The electric charge remaining in the circuit of electrode→Y electrode→diode 51,...→transistor 52 is discharged.
This is to prevent breakdown of the thin film EL element due to residual charges.

At the third timing, the signal T ₂ is applied to the circuit 50 and the signal T ₃ is applied to the circuit 40. Therefore, the sustaining voltage V _s1 is from transistor 42 to diode 4
3,...→X electrode→Y electrode→diode 51,...→
is applied via transistor 52. At this time, the sustaining voltage is applied to the thin film EL element in the opposite direction to that described above.

At the fourth timing, the signal _T4 is applied to the circuit 30, and the diode 24→diode 23,...→Y
The residual charge is discharged in the circuit of electrode → X electrode → diode 32, . . . transistor 31 →.

The above four timings are sequentially repeated to perform maintenance drive.

ΓWrite, erase, read drive The power supply 63 is set to the write voltage according to the drive mode of the thin film EL element, for example, write, erase, read drive.
Vw, erase voltage Ve, and read voltage Vr are output to line D.

Then, the transistors 61 and 71 of the X electrode and Y electrode connected to the picture element desired to be written, erased, or read are selectively turned on by the electrode selection signal. The electrode selection signal is applied after the fourth timing of sustain driving ends and before the first timing starts. Therefore, the write voltage Vw, erase voltage Ve or read voltage Vr is changed from line D to transistor 6.
1→diode 62→Y electrode→X electrode→transistor 71. Driving at this time is performed by a point sequential method or a line sequential method.

The drive circuit shown in Figure 1 is simplified and a thin film EL
FIG. 3 shows a drive circuit whose circuit component is a full erase circuit for an element. In the figure, the same reference numerals as in FIG. 1 represent the same contents, and the explanation will be omitted. still,
The diodes 24 and 44 are thin film EL after applying the sustaining voltage.
This is for forming a current path opposite to that of the transistors 52 and 31 when short-circuiting both ends of the element to release charge.

Reference numeral 80 denotes a full-face erase voltage generation unit, which supplies the voltage Vs applied from the sustain voltage source 25 as a sustain voltage Vs ₁ during sustain drive and as a full-face erase voltage Ve during full erase. Its circuit configuration consists of a transistor 81 connected to a sustaining voltage source 25;
The transistor 82 is connected to the base of the transistor 82 through resistors R ₂ and R ₃ , and the resistors R ₃ and R ₂
A capacitor C and a resistor _R1 are connected between the common connection point of the sustain voltage source 25 and the transistor 81.
A common connection point between the capacitor C and the resistor _R1 is connected to the base of the transistor 81.

During normal sustain driving, the transistor 82
is off, transistor 81 is on, and the thin film
A sustaining voltage Vs ₁ is supplied to the EL element, but when erasing the entire surface, transistor 82 is on and transistor 81 is on.
is off, and therefore the base voltage V _B of the transistor 81 is V _B =Vs/R ₁ +R ₂ +R ₃ ( _{R 2 +} R ₃ -R ₁ R ₂ /R
₁ +R ₃ e ^- 〓〓〓) ...(1) (However, Re=R ₂ (R ₁ +R ₃ )/R ₁ +R ₂ +R ₃ ). The resistor _R2 is a resistor for discharging the charge in the capacitor C with a time constant _CR2 when the transistor 82 is turned on for full erase and then turned off for normal sustain driving. Since ₂ ≫ R ₁ and R ₃ are set, the above equation can be simplified as follows.

V _B ≒V _S (1-R ₁ /R ₁ +R ₃ e ^- 〓〓〓) ...(2) (However, Re≒R ₁ +R ₃ ) In this case, the time of the voltage supplied from the full erase voltage generation section 80 Fig. 4 shows the changes in characteristics. In FIG. 4, transistor 82 is turned on at time _t1 .

The drive circuit having the full erase voltage generating circuit shown in FIG. 3 has the following drawbacks.

During normal maintenance drive, transistor 81 is always on, but the initial current that flows when charging the thin film EL element (maximum 2A for a 6-inch panel)
Therefore, even if hfe is set large, transistor 8
A current of about 2 mA flows through the base of No. 1 for hfe≈1000, and the value of the base voltage V _B does not match the calculated value shown by equation (2), resulting in a voltage drop of R ₁ ×2 mA. Since the resistors R ₁ and R ₃ are set to about 10 kΩ so as not to place an excessive load on the sustaining voltage source 25, the voltage drop across the resistor R ₁ is about 20 V. As charging progresses, the collector current of transistor 81 decreases, so eventually the thin film EL
A predetermined sustaining voltage is applied to the element, but the rise is slow. Also, the base voltage V _B of the transistor 81
Since the transistor 81 performs an emitter follower operation at each point in time when a large initial current flows when a voltage is applied to the thin film EL element whose voltage is lower than the sustaining voltage V _S1 and when a full erase voltage is generated, its emitter voltage is also approximately the base voltage V Since it is equal to _B , the power consumption of the transistor 81 is also excessively consumed during such a linear operation. Furthermore, the delay in the rise characteristic promotes this problem.

It is an object of the present invention to provide a new and useful full erase circuit for a thin film EL display device that eliminates the above-mentioned drawbacks by making full use of technical means.

Hereinafter, the present invention will be explained in detail according to embodiments with reference to the drawings.

FIG. 5 is a schematic circuit configuration diagram illustrating one embodiment of the present invention.

A sustaining voltage source 25, a capacitor 84 having a capacitance C _S , and one end of a thin film EL element 10 having a capacitance C _EL are connected in parallel, and switching elements 91 and 92 are interposed between the respective connection points. The other end is grounded, and a switching element 93 is further connected in parallel with the thin film EL element 10. Switching element 91 corresponds to transistor 81 in FIG. 3, and switching element 92 corresponds to transistors 22 and 42.
Similarly, switching element 93 corresponds to transistors 52 and 31, respectively.

Hereinafter, the operation of this embodiment will be explained in detail based on the charging operation of the thin film EL element 10 by the switching element 92 and the discharging operation from the thin film EL element 10 by the switching element 93. FIG. 6 is a timing chart for explaining the operation of FIG. 5.
In the figure, T ₉₂ , T ₉₃ , and T ₉₁ indicate on-timings of switching elements 92, 93, and 91, respectively. During normal sustain driving, the switching element 91 is turned on, and the sustain voltage V from the sustain voltage source 25 is applied.
_S1 is applied to the thin film EL element 10 through the operation of switching elements 92 and 93. When a voltage is applied, the capacitor 84 contributes, and since it is set as C _S >>C _EL , when a large transient current flows during switching of the switching element 92, the switching element 91
The charge from the capacitor 84 is supplied to the thin film EL element 10 without placing a burden on the capacitor 84, and therefore there is no unnecessary power consumption of the transistor 81, which was a problem in the drive circuit of FIG. The charge equivalent to the charge transferred to the thin film EL element 10 can be charged with a small average current by the switching element 91 while the switching element 92 is off. The voltage becomes almost equal to the sustaining voltage V _S1 of the sustaining voltage source 25,
Fully saturated operation is possible, eliminating extra power consumption due to linear operation. During the full erase period, if the switching element 91 is turned off, charge replenishment from the sustaining voltage source 25 to the capacitor 84 is cut off, so the voltage applied to the thin film EL element 10 of the capacitor 84 is changed before the switching element 92 is turned on. The voltage after the switching element 93 is turned off is V _O
Then, each time the switching element 92 is turned on, Q _S =
The charge of C _S ² ·V _O /C _S +C _EL is repeatedly charged to the thin film EL element 10 via the switching element 92, and the thin film EL
The electric charge charged to the element 10 is transferred to the switching element 9.
The voltage of the capacitor 84 returns to the original V _S1 because it is dissipated through a discharge circuit that is repeatedly formed every time 3 is turned on (the switching element 92 is turned off during this period).
After the switching elements 92 and 93 are opened and closed n times from , V _CS =(C _S /C _S +C _EL ) ⁿ ·V _S.

For example, if C _S =10 μF and C _EL =0.3 μF, C _S /C _S +C _EL =0.97. In order to erase the entire area, the value of V _CS should be gradually reduced to about 0.8V _S1 , but since when n = 8, V _CS ≒ 0.78V _S1 , if the switching element 91 is turned off during this period, the entire area will be erased. The purpose of erasure is achieved.

When the switching element 91 is turned on again after the desired voltage is generated, the capacitor 84 is charged to the original voltage V _S1 and thereafter maintains the normal maintenance voltage. The switching element 91 may simply perform a switching operation, and a specific circuit configuration diagram of this portion is shown in FIG. The power consumption of the switching element 91 is much lower than that of the circuit shown in FIG. 3, and it can be implemented using a transistor with a smaller capacity and a heat sink with a smaller area than the transistor 81.

Incidentally, instead of always turning on the switching element 91, the switching element 9 is turned on as shown by the broken line in FIG.
The switching element 91 may be turned on at an appropriate time during the second off period, and the capacitor 84 may be charged only during this period. In this case, it is also possible to use a thyristor, photothyristor, etc. as the switching element to form a simple circuit configuration as shown in FIGS. 8A and 8B. In this circuit configuration, charging of the capacitor 84 is almost completed after the thyristor is turned on by the trigger, and when the flowing current becomes less than the holding current, the thyristor is automatically turned off. Thyristors have a low on-voltage even at high currents, so the power consumption of the element itself can be reduced.

As explained in detail above, according to the full erase circuit system of the present invention, the power consumption of the switching element for the full erase operation can be set to be low without delaying the response speed of the thin film EL element, and the circuit configuration is extremely simple. It becomes a technology with remarkable practical effects.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a drive circuit that controls the basic operation of a thin film EL element. FIG. 2 is a time chart for explaining the operation of FIG. 1. FIG. 3 is a driving circuit diagram of a conventional thin film EL element having an entire erase voltage generating section. FIG. 4 is an explanatory diagram for explaining the operation of the drive circuit shown in FIG. 3. Figure 5 shows part 1 of the present invention.
FIG. 2 is a schematic circuit configuration diagram illustrating an example. FIG. 6 is a time chart for explaining the operation of FIG. 5. FIG. 7 is a circuit diagram of a full erase circuit section using one embodiment of the switching element of the present invention. FIGS. 8A and 8B are circuit configuration diagrams showing one embodiment of the present invention using a thyristor. 10... thin film EL element, 25... maintenance voltage source,
84... Capacitor, 91, 92, 93... Switching element.

Claims (1)

[Claims] 1. A charge written between the matrix electrodes in a thin film EL element in which a thin film emitting layer that emits light in response to an applied voltage is interposed between mutually orthogonal matrix electrodes, and exhibits hysteresis characteristics between the applied voltage and the luminance. In the method for driving a full erase operation of a thin film EL element in which all the data are erased all at once based on the hysteresis characteristic, the matrix electrode and the capacitor are connected in parallel to a sustain voltage source that applies a sustain voltage to the thin film EL element via a switching element; The switching element is turned off during a full erasing period, and the accumulated charge of the capacitor is repeatedly charged to the entire capacitance between the matrix electrodes, and the charge charged to the capacitance is dissipated in accordance with the repeated opening and closing operation of the discharge circuit. A thin film characterized by
Full erase drive method for EL elements.